Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

Microsoft PowerPoint - EECE426_Flash_all

1,317 views

Published on

  • Be the first to comment

  • Be the first to like this

Microsoft PowerPoint - EECE426_Flash_all

  1. 1. Lecture Goals • Understanding – Operations of Flash memory Introduction to Flash Memory Operation March 19, 2008 Sungjoo Yoo Embedded System Architecture Lab. Agenda Context: SSD in Notebook and PDA • SSD Benefits • Comparison of Flash memory cells – High performance, low power, and reliability • Flash memory organization • Flash commands – Read, program, and erase • ECC (error correction code) 10 Flash memory chips • Weal leveling • Bad sector management
  2. 2. [Source: J. Lee, 2007] An Example: Intel SSD NOR vs. NAND Summary • NOR Flash • NAND Flash • Especially good for random accesses w.r.t. Random, direct access Block I/O access interface Higher density, lower cost HDD Better performance for Fast random reads erase and write Slow erase and write Mainly for (sequential) data Mainly for code storage storage [Source: Samsung, 2000] [Source: Micron, 2006] Area Efficiency NAND/NOR Characteristics • Metal contacts in NOR cell are the limiting • NAND is currently favored thanks to better factor: 2.5X difference in area/cell write (erase) performance and area efficiency
  3. 3. [Source: Micron, 2006] NAND vs. NOR: Required Pins NAND Flash Cells • NAND utilizes multiplexed I/O (I/O[7:0] in the table) for commands and data – NAND operation: command address data • NOR has separate address and data buses [Source: J. Lee, 2007] [Source: Micron, 2006] Flash Operations NAND Flash Architecture: 2Gb Case • Operations – Read – Write or Program 1 1 1 1 1 1 1 1 • Changes a desired state from 1 to 0 tR write – Erase tPROG 1 0 1 1 0 0 1 0 • Changes all the states from 0 to 1 • Unit erase 1 1 1 1 1 1 1 1 – Page (sector) • Read/Write unit (in NAND) – Block • Erase unit
  4. 4. [Source: Micron, 2007e] [Source: Micron, 2007e] Small vs. Large Block Performance Comparison Small block tR = 15us 12.65MB/s for read tPROG = 200us 2.33MB/s for program Large block tR = 25us 16.13MB/s for read tPROG = 300us 5.20MB/s for program Runtime reduction! Note: The same erase time per block! [Source: Micron, 2006] [Source: Micron, 2006] Read Operation Pin Description 25us Data
  5. 5. [Source: Micron, 2006] [Source: Micron, 2006] Commands & I/O Multiplexing Erase Operation [Source: Micron, 2006] [Source: Micron, 2006] Program Operation Program with Random Data Input • Often used for partial page program
  6. 6. [Source: Micron, 2006] [Source: Micron, 2006] Page Storage Methods Read Operation (Revisited) [Source: Micron, 2006] [Source: Micron, 2007] Comparison between Normal Read Page Read Cache Mode and Page Mode Cache Read
  7. 7. [Source: Micron, 2006] [Source: Micron, 2007] Commands & I/O Multiplexing Page Read Cache Mode Operation [Source: Micron, 2007] [Source: Micron, 2006] Performance Comparison Program Page Cache Mode
  8. 8. [Source: Micron, 2006] [Source: Micron, 2006] Overlapping Program Data Cycles Commands & I/O Multiplexing and tPROG [Source: Micron, 2007b] [Source: Micron, 2007b] Program Page Cache Mode Performance Comparison Operation
  9. 9. [Source: Micron, 2007c] Internal Data Move Single Page Write Case Error… • Remember “erase-before-write” means “no overwrite”! (tR + tRC + tWC + tPROG )*(# pages/block) + tERASE = (25us + 105.6us*2 + 300us)*64 + 2ms = 36.32ms for a single-page (2KB) write operation [Source: Micron, 2006] [Source: Micron, 2007c] Commands & I/O Multiplexing Internal Data Move Operations • Internal data move • Internal data move with random data input
  10. 10. [Source: Micron, 2007c] [Source: Micron, 2007d] Read Status • Read status can be issued during other operations Removed! [Source: Micron, 2006] Command, Address, and Data The Simplest NAND Flash Controller Selection • NAND Flash Control by Processor • Which operation? int * cmd = 0xFFF010; int * addr = 0xFFF020; int * data = 0xFFF000; * cmd = 0x80; * addr = ColL; * addr = ColH; …
  11. 11. [Source: Samsung, 2000] [Source: Z. Wu, 2007] NAND Program & Erase SLC vs. MLC • SLC (single level cell) vs. MLC SLC MLC probability 1 0 11 10 00 01 Vth voltage -Fast, less error -Slow, more error -Low bit density -High bit density + ECC (error correction code) E.g., RS, LDPC, BCH, … E.g., 4bit ECC for 512B [Source: Samsung, 2000] [Source: Micron, 2006] NAND Flash Lifetime MLC vs. SLC: Characteristics • # of erase operations is limited due to • MLC degradation wear leveling & ECC are needed! – 2x inferior performance to SLC – 10x shorter lifetime than SLC
  12. 12. [Source: Micron, 2006] Two Methods to Enhance ECC Algorithms Endurance (& Effective Capacity) • ECC (error correction code) • SLC: Hamming • Wear leveling • MLC: RS, BCH, LDPC, etc. [Source: Micron, 2007f] [Source: Micron, 2007f] Hamming Code on a Byte-Wide Hamming Code of A Single Data Old ECC Data Packet 0 0^0^0^1 1^1^0^1 101 0^1^0^0 010 0 0 Corruption: 01010001 01010101 New ECC with the corrupted data 0 Error detection by XORing old and new ECCs 1 bit error location (=correction) by XORing old and new odd ECCs 2n data 2*n bits for ECC
  13. 13. [Source: Micron, 2007f] [Source: Micron, 2007f] Hamming Code on a Byte-Wide Hamming Code on a Byte-Wide Data Packet Data Packet [Source: Micron, 2007f] [Source: Micron, 2007f] Hamming Code on a Byte-Wide Hamming Code on a Byte-Wide Data Packet Data Packet
  14. 14. [Source: Micron, 2007f] [Source: Micron, 2007f] Hamming Code on a Byte-Wide Hamming Code: Data Packet Single Bit Error Correction Case [Source: Micron, 2007g] [Source: Z. Wu, 2007] Spare Area to Store ECC ECC for MLC (Example) • Total 24 bits (=18+6) – Byte: 512 29 2*9 = 18, Bit: 8 23 2*3 = 6 4 level (2 bit) cell vs. 8 level (3 bit) cell (511, 451) Reed-Solomon code -Applied to 8 level cell -Code rate = 451/511 = 0.883 -Effective bits = 3*451/511 ~ 2.6 bits/cell >30% better capacity than 2 bit MLC
  15. 15. [Source: Micron, 2008] [Source: Micron, 2006e] Copyback to Enhance Data Wear Leveling Integrity • If # errors (of a block) increases, then read data • Two scenarios of MLC NAND Flash usage and re-write it (to the same or other block) (512MB, 4096 blocks, 10k erase cycles) – Similar to self refresh in DRAM – Update 6 files/hour, 50 blocks/file, 24 hours • Only 200 blocks are used • All 2096 blocks are evenly used [Source: Micron, 2006e] [Source: Micron, 2006b] Two Wear Leveling Methods Initial Bad Block Identification • Method #1 The first page in the block – Monitor the erase counts of The data @ 2048 all blocks – On write, select the one with the least count – Additional data migration is needed – Lifetime is maximized with write performance overhead • Method #2 – Use only a part (e.g., 25%) of total storage as a pool of available blocks – On write, use the available (free of data) block with the least count • Performed on boot up – No write performance overhead, but gives a shorter • If(data at 0x2048 on Pages 0 and 1 == 0xFF) life time It’s a good block
  16. 16. [Source: Micron, 2006b] Block Degradation and Tracking Reference at Runtime • Important to track the blocks that go bad during • • [Samsung, 2000] Samsung Electronics, Samsung NAND Flash Memory, 2000. [Micron, 2006] Micron, NAND Flash 101 - An Introduction to NAND Flash and How to normal device operation Design It In to Your Next Product, Nov. 2006. • [Micron, 2007] Micron, NAND Flash Performance Increase - Using the Micron® PAGE READ • When and how to check? CACHE MODE Command, June 2007. • [Micron, 2007b] Micron, NAND Flash Performance Increase with PROGRAM PAGE CACHE – Issue a Read Status command after any Erase and MODE Command, June 2007. Program operation • [Micron, 2007c] Micron, NAND Flash Performance Improvement Using Internal Data Move, June 2007. • Two types of failure • [Micron, 2007d] Micron, Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash Devices, June 2007. – Permanent: add the block to the bad block table • [Micron, 2007e] Micron, Small Block vs. Large Block NAND Devices, June 2007. • [Micron, 2006b] Micron, NAND Flash Design and Use Considerations, Aug. 2006. – Temporary • [Micron, 2006e] Micron, Wear-Leveling Techniques in NAND Flash Devices, Aug. 2006. • Program disturb: e.g., neighbor page data are corrupted • [Micron, 2007f] Micron, Hamming Codes for NAND Flash Memories, June 2007. • Read disturb: e.g., due to too many reads of a single page • [Z. Wu, 2007] Flash memory with coding and signal processing, US Patent 2007/0171714 A1, Published, 2007 • Over-programming: e.g., all data look like ‘0’ • [Micron, 2008] Micron, Using COPYBACK Operations to Maintain Data Integrity in NAND Flash Devices, Oct. 2008. • Data loss: e.g., due to charge loss or gain • [Micron, 2007g] Micron, Micron ECC Module for NAND Flash via Xilinx™ Spartan™-3 FPGA, • Solution: erase the corresponding block and re-program it June 2007.

×