Memory System

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Memory System

  1. 1. The Memory System <ul><li>Common features . </li></ul><ul><li>User requirement / Ideal viewpoint of a memory system. </li></ul><ul><li>The typical Memory organization in reality. </li></ul><ul><li>System Programmers’ viewpoint of a memory system. </li></ul><ul><li>The actual Memory Hierarchy in a modern day computer. </li></ul><ul><li>Classification from various angles. </li></ul><ul><li>The characteristics & classifications of each levels of the Memory Hierarchy . </li></ul><ul><li>The Organizational Features of Primary / Physical Memory. </li></ul><ul><li>The Cache Memory Features. </li></ul><ul><li>The Secondary Memory Features. </li></ul><ul><li>Logical Address, Virtual Address & Physical Address vis a vis role of Memory Management Unit [MMU] </li></ul><ul><li>Concept of Virtual Memory & its implementation. </li></ul>
  2. 2. Common Features of the Memory System <ul><li>Brain of the computer . </li></ul><ul><li>Data Library OR Storage Repository . </li></ul><ul><li>Houses the File System ( Filing Cabinet ). </li></ul><ul><li>Widest possible range & types. </li></ul><ul><li>Normally built independent of the CPU except for the integrated portions ( Registers ) . </li></ul><ul><li>Integral portion of almost ALL peripheral interfaces [ Command/ Status Registers and Local Store ( Buffers ) ]. </li></ul><ul><li>Oblivious about the following : </li></ul><ul><li>1) The Operand Size of the CPU. </li></ul><ul><li>2) The Instruction Set of the CPU as well as the available addressing modes . </li></ul><ul><li>3) The content of it’s storage. </li></ul><ul><li>4) Various Interface protocols between the CPU and the Peripherals . </li></ul><ul><li>5) The various management Techniques in use / employed by the Memory Management Unit [MMU] </li></ul><ul><li>an integrated Architectural & O.S. Feature. </li></ul>
  3. 3. User Requirement/ Ideal View point of the Computer Memory <ul><li>Must represent a reliable form of storage repository. </li></ul><ul><li>Must be versatile enough to store anything ( Text, Pictures, Video, Audio ) i.e. must represent some Universal form of storage . </li></ul><ul><li>Should be infinite sized / capable of storing very large amount of data </li></ul><ul><li>. Should retain it’s content for a reasonable period of time even if power is not there ( Non Volatile ). </li></ul><ul><li>Should be modifiable / user alterable . </li></ul><ul><li>Should possess high speed of access both for Storage & Retrieval . </li></ul><ul><li>Should be of Low Cost . </li></ul><ul><li>Must be flexible & adaptable to change in size ( Expansion / Reduction). </li></ul><ul><li>Must be compatible with new emerging technologies. </li></ul>
  4. 4. Typical Memory Organization in Reality Addressable Unit / Block #1 Addressable Unit / Block #i Addressable Unit / Block #N S E L E C T I O N Input Buffer Output Buffer READ WRITE Data In Data Out ADDRESS OUT DATA BUS IN DATA BUS
  5. 5. Typical Memory Write Sequence into a specific block <ul><li>i) Set up Data to be written on the Data In Bus . </li></ul><ul><li>ii) Assert Address of the destination block on the Address Bus thereby selecting the relevant address block. </li></ul><ul><li>iii) Assert Write Signal on the control bus . </li></ul><ul><li>iv) Wait for receipt acknowledgement via control bus . </li></ul>
  6. 6. Typical Memory Read Sequence from a specific block <ul><li>i) Assert Address of the source block on the Address Bus thereby selecting the relevant address block. </li></ul><ul><li>ii) Assert Read Signal on the control bus . </li></ul><ul><li>iii) Wait for Ready Signal via control bus . </li></ul><ul><li>iv) Probe Data Out Bus to obtain the Data to be read . </li></ul>
  7. 7. Access Restriction <ul><li>Most memories happen to be Single Port i.e. presents only one access point to the underlying memory by means of </li></ul><ul><li>a) Single Address Bus . </li></ul><ul><li>b) Single Data Bus . </li></ul><ul><li>Hence Simultaneous Read Write access for the same memory module i.e. writing into one location while reading from some other location is not possible. </li></ul><ul><li>However there exists some 2 –Port memory (to be illustrated later). </li></ul>
  8. 8. System Programmers’ view point of the Memory System - 1 <ul><li>The actual memory as depicted before , can be viewed as a large , fixed size , one dimensional array of individual storage blocks with a single access port . </li></ul><ul><li>Any user should not be affected by the available / existing memory capacity . Any one user process’s space requirement may exceed the total available / existing memory capacity but still can be run in the system with no marked degradation in response time / performance. </li></ul><ul><li>There will be more than one user process together with the operating system resident in the existing memory at any point of time. </li></ul><ul><li>The existing memory capacity , if enhanced , will not force a regeneration of the system but rather will improve response time . </li></ul>
  9. 9. The Typical Memory Hierarchy Registers On Chip CACHE ( Split, Associative ) Off Chip Cache ( Unified , Static/ Associative ) Main/ Primary Memory [ Static ( ROM, EPROM, EEROM ), Dynamic ( SDRAM, DDRRAM, FLASH )] Fixed Secondary Memory [ Magnetic Disk ( Platter, Winchester ), Internal (IDE, SCSI, SATA), External ( USB, Parallel ) ] Secondary Memory ( Removable Media ) [ Tape, DAT,CD, DVD, FLASH ] SIZE COST & SPEED
  10. 10. Objectives & Motivation behind a Hierarchical Memory Structure <ul><li>Maximize CPU Utilization by ensuring no WAIT state for memory. </li></ul><ul><li>Satisfy ideal viewpoints by creating an environment such that every user feels : </li></ul><ul><li>1) Available Memory Size = Number of Secondary removable medias being used i.e. Infinite Sized. </li></ul><ul><li>2) Accessing Speed of Memory = Comparable with Cache Memory access speed i.e. high speed. </li></ul><ul><li>Achieved through effective management of available / existing Memory Space throughout the Memory Hierarchy. </li></ul>
  11. 11. The Configuration of various Memory Levels ( Look Through Configuration ) SIZE COST & SPEED CPU Registers On Chip MMU Cache [ On Chip + Off Chip ] Cache _ Main Interface Main Memory Secondary Memory + Associated Interface Each Hierarchical Level represents a Higher Speed Version that contains some portion of its immediate Next Hierarchical Level
  12. 12. Memory System Key Performance Parameters <ul><li>a) Access Time (Latency) : For random access memory , this is the time it takes to perform a read or write operation, that is, the time from the instant that is, the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. For non-random-access memory, access time is the time it takes to position the read-write mechanism at the desired location. </li></ul><ul><li>b) Memory Cycle time : Access Time + Any additional time required like Data Set Up Time before a 2 nd access can commence. This is related to the system bus only not the processor. </li></ul><ul><li>c) Transfer Rate : The rate at which Data can be transferred into or out of a memory unit. </li></ul><ul><li>For Electronic Memory this rate = 1 / Memory Cycle Time. </li></ul><ul><li>For Non Electronic Memory the following relationship hold </li></ul><ul><li>T N = T A + N / R where T N = Average time to read or write N bits. </li></ul><ul><li>T A = Average Access Time . </li></ul><ul><li>N = Number of bits. </li></ul><ul><li>R = Transfer rate, in bits per second (bps). </li></ul>
  13. 13. Classification of Memory from Various Angles <ul><li>Proximity to the CPU. </li></ul><ul><li>Accessible Units . </li></ul><ul><li>User/Programmer Accessibility as well as modifiability. </li></ul><ul><li>Technology Used. </li></ul><ul><li>Access Mechanism. </li></ul><ul><li>Volatility / Data Retention Capacity. </li></ul>
  14. 14. Classification of Memory – A Proximity to the CPU - A1 <ul><li>Registers within the CPU : Part of CPU itself. </li></ul><ul><li>a. Special Purpose Registers </li></ul><ul><li>Stack Pointer, Instruction Pointer, Memory Address Register [MAR], Memory Buffer Register [MBR] , Index Register, Base Register, Bound Registers. </li></ul><ul><li>b. General Purpose Registers [GPRS ] Number & Sizes may vary. Some special features are : </li></ul><ul><li>(1) Used as the CPU Scratch Pad. </li></ul><ul><li>(2) Organized as a Bank / Register File. </li></ul><ul><li>(3) Normally possess 2-Port accessibility i.e. at any point of time the program can read from one register as well as write into some other register. </li></ul>
  15. 15. Classification of Memory – A Proximity to the CPU – A2 <ul><li>2. Cache Memory (On Chip & Off Chip) : </li></ul><ul><li>a. On Chip Cache [ Level 1 / L1 Cache ] Fabricated along with the CPU die usually split into separate Program Memory / Instruction Memory & Data Memory along with dedicated Bus connectivity to the CPU like Instruction Address Bus, Instruction Fetch Bus, Data Address Bus , Data Fetch Bus on one side as well as connected to the next level cache [ L2 Cache ] through another set of unified bus ( Address & Data ) on the other side. . Contains a portion of the next level cache [ L2 Cache ]. </li></ul><ul><li>b. Off Chip Cache [ Level 2 / L2 Cache & Level 3 / L3 Cache ] Fabricated separately from the CPU die but either put in the same plastic package (L2) OR put as a separate module outside (L3 wherever present ) . Usually unified. Connected to L1 Cache via a dedicated unified Bus ( Address & Data ) on one side as well as connected to the next level ( Primary/ Main memory ) through another set of bus ( Address & Data ) on the other side. Contains a portion of the main memory . </li></ul>
  16. 16. Classification of Memory – A Proximity to the CPU – A3 <ul><li>3. Primary / Main Memory : This is commonly referred as the memory of any computer system . Before execution, any program has to be brought/loaded into this memory. The CPU primarily looks for anything in this level itself. First. It is an unified memory connected to L2 Cache. In some cases it also possesses a dedicated connectivity to the CPU. It is also accessible to some of the peripherals { Direct Memory Access (DMA) to be illustrated later }. Main memory can be regarded as partitioned into the following two : </li></ul><ul><li>a. System Memory </li></ul><ul><li>Houses the Device Drivers and other system packages . It contains resident Operating System code and code portions of the system modules currently in use , their associated data as well as the System Stack. Some portion of it is non volatile and most of it remains inaccessible to the ordinary user. The volatile portion ’s size varies depending on the current system load. </li></ul><ul><li>b. User Memory </li></ul><ul><li>Separately maintained for each user in a multi –user system. Contains currently relevant ( working portion ) of the user program, data as well as User stack . Normally protected from outside / unauthorized users. This portion remains user alterable and volatile. In </li></ul>
  17. 17. Classification of Memory – A Proximity to the CPU – A4 <ul><li>4. Secondary / Back Up Memory : It is an unified memory connected to the main/primary memory. This level acts as the Filing cabinet of any computer system and acts as the back up store . This represents the widest types of memory media and peripherals. Most of these peripherals happens to be user alterable but non volatile and possess the capability of transferring data at a very fast rate and hence employs Direct Memory Access (DMA) technique. It is of following types: </li></ul><ul><li>a. Fixed & Internal : Hard Disk drives. Winchester Disk Drives. </li></ul><ul><li>b. Removable & Internal : Floppy Disk Drives, CD_ROM Drives , DVD Drives , Tape Drives, DAT drives which are fixed and the associated media (Floppy, CD_ROM, DVD Disk, Tape Spool, DAT Cartridge ) which are removable. </li></ul><ul><li>c. Removable & External : External Hard Disk Drive, USB Flash Drives. </li></ul>
  18. 18. Classification of Memory – B1 Accessible Units <ul><li>Word : The natural unit of organization of Memory as viewed by the CPU. The size of the word is typically equal to the number of bits used to represent an integer and to the instruction length. However there are many exceptions like Pentium –IV which has a 64 bit word length but a 4 Byte long Integer representation. </li></ul><ul><li>Addressable Unit : In some systems, addressable unit is the word. However, many systems allow addressing at the byte level. In any case, the relationship between the length in bits A of an address and the number N of addressable units </li></ul><ul><li>is 2 A = N. </li></ul><ul><li>Unit of transfer : For main memory, this is the number of bits read out or written into memory at a time. The unit of transfer need not equal a word or an addressable unit. For external memory, data often are transferred in much larger units than a word commonly referred as blocks. </li></ul><ul><li>Programmer / System Accessible Units : Varies widely as illustrated next.. </li></ul>
  19. 19. Classification of Memory – B2 Programmer / System Accessible Units <ul><li>Accessible Units : Size / Width of each memory block that is accessed at one go . </li></ul><ul><li>It can vary widely across levels a few of which is illustrated below : </li></ul><ul><li>Individual Bit accessibility : Applicable to General Purpose Registers (GPRs) lying within the CPU as well as user writable locations in the main/primary memory. </li></ul><ul><li>Individual Byte ( 8 bits / One ASCII Character) : CPU Registers as well as Cache Memory / Main Memory location. </li></ul><ul><li>Individual Word ( Integral Multiple of Bytes) : CPU Registers as well as Cache Memory / Main Memory location. </li></ul><ul><li>Integral Multiple of Words : </li></ul><ul><li>i) Cache Lines. </li></ul><ul><li>ii) Main Memory Pages. </li></ul><ul><li>iii) FLASH Memory Blocks. </li></ul><ul><li>iv) Disk Cluster. </li></ul><ul><li>e) Files : Applicable to secondary/ back up memory only. </li></ul>
  20. 20. Classification of Memory – C User / Programmer accessibility & modifiability <ul><li>CPU Registers : User accessible & modifiable except some of the special purpose registers like MAR & MBR </li></ul><ul><li>Cache Memory (All types): User / Programmer inaccessible but modifiable by the O.S. </li></ul><ul><li>Main Memory : Read only area (ROM, PROM, EPROM , EEROM, FLASH ) are non modifiable by the user but accessible in an indirect way. </li></ul><ul><li>User Read Write Area both accessible as well as modifiable by the user. </li></ul><ul><li>Secondary Memory : Normally accessible to any user , some of which are modifiable normally while some are modifiable under some special condition. </li></ul>
  21. 21. Classification of Memory – D Technology in Use <ul><li>Electronic Memory : Used in building all forms of electronic storage like registers, cache as well as primary/main memory. Some form of secondary media like USB Flash also employs this memory. </li></ul><ul><li>Magnetic Memory : Used exclusively to build some secondary / back up medias like Hard Disk, Floppy etc. </li></ul><ul><li>Optical : Secondary medias like CD – ROM, CD, DVD etc. </li></ul>
  22. 22. Classification of Memory – D Electronic Technology <ul><li>2 – Level Combinational Circuit Read Only Memory [ROM] , Erasable Programmable Read only Memory [EPROM], Electrically erasable Read only Memory [EEROM]. Composed of a single transistor cells each with a programmable fuse link. </li></ul><ul><li>b) Static Random Access Memory [RAM] or Read Write Memory [RWM] : Data stored in terms of static charges in Flip Flops / Back to back connected Transistor cells needs no refreshing . Requires 4/6 transistors per bit of storage. </li></ul><ul><li>c) Dynamic Random Access Memory [ DRAM ] : Data stored as charge at the load capacitance of a Transistor cell . Requires one transistor per cell. This again can be of various types (widest possible range). </li></ul><ul><li>d) FLASH Memory : Non volatile but alterable at block level only by using a single electronic signal termed as a flash . </li></ul>
  23. 23. Classification of Memory – D contd. Dynamic Random Access Memory ( DRAM ) <ul><li>It stores each bit of data in a separate capacitor within an integrated circuit . </li></ul><ul><li>Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. </li></ul><ul><li>Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. </li></ul><ul><li>Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. </li></ul><ul><li>This allows DRAM to reach very high package density . Hence this is mostly in use today as RAM Modules. Of late 1 GByte modules have come out. </li></ul><ul><li>Since DRAM loses its data when the power supply is removed, it is in the class of volatile memory devices. </li></ul>
  24. 24. Dynamic Random Access Memory ( DRAM ) Typical structure
  25. 25. Dynamic Random Access Memory ( DRAM ) Key Features <ul><li>Requires periodic refreshing hence separate refresh circuit is needed. </li></ul><ul><li>Slower than CPU and it’s associated bus. </li></ul><ul><li>Very high packing density ( Typical 256 Mbyte module.) </li></ul><ul><li>Individual chips is one bit wide hence 256 Mbyte is produced by 256 Mbit X 8 DRAM chips. </li></ul><ul><li>Electrical & magnetic interference inside the computer system may cause a single DRAM bit to flip it’s original state hence an extra parity bit chip is provided for error correction. Hence 256 Mbyte module will be framed by 8 nos of 256 Mbit DRAM module + One 256 Mbit parity bit module i.e a total of 9 (nine) modules. </li></ul>
  26. 26. Dynamic Random Access Memory ( DRAM ) Various Types in Use <ul><li>Fast Page Mode DRAM ( FPM). : Enables accessing in a row-wise fashion. </li></ul><ul><li>Extended Data Out (EDO) DRAM : A new access cycle can be started keeping the data output of the previous cycle active. This , in principle allows a certain amount of operation overlap (Pipelining). </li></ul><ul><li>Synchronous DRAM (SDRAM) : DRAM which possesses a synchronous interface where the access can be synchronized with the CPU clock albeit with a reduced pre-specified max. permissible clock rate. This facilitates pipelined read & write. </li></ul><ul><li>Double Data Rate RAM (DDR RAM) : A variation of SDRAM that uses both rising as well as falling edges of a clock cycle to transfer data thereby effectively doubling the clock rate It is organized in rows or memory pages. Each memory page is divided into four (4) sections / banks. While accessing a row address, memory bank , coloumn address as well as a chip select needs to be present. Read or Write access occurs in burst of 4 typically which is enough to fill a 32 byte ( 4 X 8 Bytes ) cache line one go in a Pentium machine which possesses a 64 bit / 8 byte wide data bus. Typical operation states are </li></ul><ul><li>(1a) Idle (1b) Row Active (1c) Read (1d) Write { Ready to accept further commands } </li></ul><ul><li>(2) Pre charging (3) Refreshing. Last two are un-interrupt able states . </li></ul>
  27. 27. Flash Memory ( The Latest Novelty) - 1 <ul><li>Flash memory (sometimes called &quot;flash RAM&quot;) is a type of constantly-powered nonvolatile memory that can be erased and reprogrammed in units of memory called blocks . It is a variation of electrically erasable programmable read-only memory ( EEPROM ) which, unlike flash memory , is erased and rewritten at the byte level, which is slower than flash memory updating. Flash memory is often used to hold control code such as the basic input/output system ( BIOS ) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written to in block (rather than byte) sizes, making it easy to update. On the other hand, flash memory is not useful as random access memory ( RAM ) because RAM needs to be addressable at the byte (not the block) level. </li></ul><ul><li>Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or &quot;flash.&quot; The erasure is caused by Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove an electronic charge from a floating gate associated with each memory cell. Intel offers a form of flash memory that holds two bits (rather than one) in each memory cell, thus doubling the capacity of memory without a corresponding increase in price. </li></ul>
  28. 28. Flash a Full Featured Memory Solution
  29. 29. Flash vs. Other Types of Memory <ul><li>Memory Type Features </li></ul><ul><li>--------------------------------------------------------------------------------------- </li></ul><ul><li>FLASH Low-cost, high-density, high-speed architecture; </li></ul><ul><li>low power; high reliability </li></ul><ul><li>---------------------------------------------------------------------------------------- </li></ul><ul><li>ROM Read-Only Memory, Mature, high-density, reliable, low cost; </li></ul><ul><li>time-consuming mask required, suitable for high production with </li></ul><ul><li>stable code </li></ul><ul><li>------------------------------------------------------------------------------------------------- </li></ul><ul><li>SRAM Static Random-Access Memory, Highest speed, high-power, low-density memory; </li></ul><ul><li>limited density drives up cost </li></ul><ul><li>----------------------------------------------------------------------------------------------------------------------------- </li></ul><ul><li>EPROM Electrically Programmable Read-Only Memory, High-density memory; </li></ul><ul><li>must be exposed to ultraviolet light for erasure </li></ul><ul><li>------------------------------------------------------------------------------------------------------------------------------ </li></ul><ul><li>EEPROM or E2 Electrically Erasable Programmable Read-Only Memory, Electrically byte-erasable; </li></ul><ul><li>lower reliability, higher cost, lowest density </li></ul><ul><li>------------------------------------------------------------------------------------------------------------------------------- </li></ul><ul><li>DRAM Dynamic Random Access Memory, High-density, low-cost, high-speed, high-power </li></ul>
  30. 30. Flash Memory ( The Floating Gate Transistor )
  31. 31. Flash Memory ( The Floating Gate Transistor )
  32. 32. Flash Memory Cell ( The Operating Principle) <ul><li>The floating gate transistor is a variant of transistor that is commonly used for non-volatile storage such as flash , EPROM and EEPROM memory. Floating gate transistors are almost always floating gate MOSFETs . Floating gate MOSFETs are useful because of their ability to store an electrical charge for extended periods of time even when they have no power. Floating gate MOSFETs are composed of a normal MOSFET and one or more capacitors used to couple control voltages to the floating gate. Oxide surrounds the floating gate entirely, so charge trapped on the floating gate remains there. The charge stored on the floating gate can be modified by applying voltages to the source, drain, and control gate terminals such that the fields result in phenomena like Fowler-Nordheim tunneling and hot carrier injection . Flash programming occurs when electrons are placed on the floating gate. The charge is stored on the floating gate, with the oxide layer allowing the cell to be electrically erased through the source. </li></ul>
  33. 33. Typical Flash Memory Array
  34. 34. Flash Memory Usage <ul><li>Used as the internal System memory </li></ul><ul><li>[ Flash BIOS ]. </li></ul><ul><li>Used as a secondary store [ USB Flash ] . </li></ul><ul><li>Electronic, static, random access, user alterable but non volatile. </li></ul>
  35. 35. Magnetic Memories Key Features <ul><li>Hard Disk : Data is recorded on / retrieved from a rotating magnetic media by a linearly moving electromagnetic head assembly through magnetic induction . </li></ul><ul><li>Floppy Disk : Data is recorded on / retrieved from a rotating magnetic media by a linearly moving electromagnetic head through direct contact . </li></ul><ul><li>Tape drive : Data is recorded on / retrieved from a linearly moving magnetic media by a fixed electromagnetic head through direct contact . </li></ul><ul><li>DAT Drive : Data is recorded on / retrieved from a linearly moving magnetic media in a Helical fashion by a high speed rotating electromagnetic head through direct contact . </li></ul><ul><li>Common Features : 1) High Data Retention. </li></ul><ul><li>2) Degradation of some media due to physical wear and tear. </li></ul><ul><li>3) Both fixed as well as removable medias are used. </li></ul>
  36. 36. Optical Memories Key Features <ul><li>Data is recorded on / retrieved from a rotating Optical media by a linearly moving Laser head assembly . </li></ul><ul><li>Common Features : </li></ul><ul><li>1) High Data Retention. </li></ul><ul><li>2) Degradation of some media due to wrong handling. </li></ul><ul><li>3) Only removable medias are used. </li></ul><ul><li>4) Various Data Compression as well as recording techniques are used. </li></ul>
  37. 37. Classification of Memory - E & F Access Mechanism & Volatility <ul><li>a) Random Access: CPU Registers, CACHE, Main Memory </li></ul><ul><li>[ ROM , EPROM, EEROM , FLASH & RAM(RWM) ] i.e. all types of electronic Memory. In some CACHE a special access termed as Associative Access is used. All are volatile except ROM & FLASH. </li></ul><ul><li>b) Direct Access & Non Volatile : Hard Disks, Winchester Disks (Non Removable) , Floppy/Flexible Disks (Removable) , CDs & DVDs. </li></ul><ul><li>c) Sequential Access & Non Volatile : Spool Tapes , DAT Cartridges (all removable) . </li></ul>
  38. 38. Features of different Hierarchical Levels of Memories - 1 <ul><li>A) CPU Registers: </li></ul><ul><li>1) General Purpose & Special Purpose . </li></ul><ul><li>2) Volatile , Electronic, Read Write & Random Access at bit level . </li></ul><ul><li>3) Some (GPRs) are Programmer Accessible. </li></ul><ul><li>4) Too few in numbers. </li></ul><ul><li>5) Speed Compatible with CPU. </li></ul><ul><li>6) Acts as Operand (address & value) & Result Storage Scratch Pads . </li></ul>
  39. 39. Features of different Hierarchical Levels of Memories - 2 <ul><li>B) On Chip Cache [ L1 Cache] & Off Chip Cache [ L2 & L3] </li></ul><ul><li>1) L1 Fabricated along with the CPU die , L2 fabricated separately but packaged along with CPU while L3 represents a shared Cache . </li></ul><ul><li>2) L1 Cache is split into Program Cache & Data Cache along with separate bus connectivity to the CPU. </li></ul><ul><li>2) Volatile , Electronic, Read Write & a mixture of random access + content addressable associative access. </li></ul><ul><li>3) Programmer & MMU inaccessible managed solely by Cache Controller(s). </li></ul><ul><li>4) Larger than number of GPRs. </li></ul><ul><li>5) Some (L1) is speed compatible with CPU. </li></ul><ul><li>6) Acts as CPU Local Storage . </li></ul><ul><li>7) Represents a High Speed Window of the next lower level. </li></ul><ul><li>8) None of these Caches contributes to Main / Primaryl Memory Space. </li></ul>
  40. 40. Features of different Hierarchical Levels of Memories - 3 <ul><li>C) Main Memory </li></ul><ul><li>1) Represents the Primary / Physical Memory. </li></ul><ul><li>2) Normally composed of DDR RAM (DRAM) or ROM / EPROM , Flash RAM. </li></ul><ul><li>3) Volatile , Electronic, Read Write & random access . </li></ul><ul><li>4) Programmer & MMU accessible. </li></ul><ul><li>5) Much Larger than CACHE. </li></ul><ul><li>6) Usually much slower than CPU also need not be size compatible with the CPU. </li></ul><ul><li>7) Acts as a sharable Storage among CPU & Peripherals . </li></ul><ul><li>7) Represents a High Speed Window of the Secondary Memory Space. </li></ul><ul><li>8) Usually represents the Universal Storage space of any Computer System. </li></ul>
  41. 41. Features of different Hierarchical Levels of Memories - 4 <ul><li>C) Secondary Memory </li></ul><ul><li>1) Represents the Virtual Memory . </li></ul><ul><li>2) Normally composed of Magnetic Disks, Floppy Disk Drive + Disk, Tape Drive+ Tapes, CD/DVD Drives + CDs,DVDs. , USB FLASH Drives. </li></ul><ul><li>3) Non- Volatile , Magnetic OR Optical, Read Write OR WORM & Direct / Sequential access. </li></ul><ul><li>4) Programmer & MMU accessible via Virtual Addresses . </li></ul><ul><li>5) Theoretically infinite sized because of the presence of removable Media. </li></ul><ul><li>6) Usually the slowest. </li></ul><ul><li>7) Storage / Recording Format as well as retrieval Format as supported by the associated interface need be compatible with the CPU access protocol. </li></ul><ul><li>8) May adopt high speed Data Transfer Mechanism like DMA to transfer Large Blocks of Data between Main Memory & itself . </li></ul><ul><li>9) Houses the File System i .e. represents the Filing Cabinet of any Computer System. </li></ul>

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