Chapter 1: Introduction to 68HC11 The 68HC11 Microcontroller
What is a computer ? Software Hardware Computer organization Control unit Arithmetic logic unit Registers common bus memory program storage data storage output unit input unit Figure 1.1 Computer organization
The processor Registers -- storage locations in the processor Arithmetic logic unit Control unit program counter keeps track of the address of the next instruction to be executed status register flags the instruction execution result The microprocessor A processor implemented on a very large scale integration (VLSI) chip Peripheral chips are needed to construct a product The Microcontroller The processor and peripheral functions implemented on one VLSI chip
Features of the 68HC11A8 microcontroller 8-bit CPU 256 bytes SRAM 512 bytes EEPROM 8 KB ROM 3 input capture channels 5 output compare functions one 8-bit pulse accumulator one serial communication interface (SCI) one serial peripheral interface (SPI) real-time interrupt (RTI) circuit 8-channel 8-bit A/D converter computer operate properly (COP) watchdog system - - - - - - - - - - - -
pulse accumulator TIMER periodic interrupt COP watchdog PAI OC2 OC3 OC4 OC5 IC1 IC2 IC3 O C 1 ROM-8K bytes RAM-256 bytes EEPROM-512 bytes PORT A PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SPI SS SCK MOSI MISO TxD RxD d a t a d i r e c t i o n D port D PD5 PD4 PD3 PD2 PD1 PD0 SCI M68HC11 CPU ADDRESS/DATA BUS data direction C PORT B PORT C HANDSHAKE I/O P B 7 P B 6 P P B P P P P B B B B B 5 4 3 2 1 0 P P P P P P P P C 7 6 5 4 3 2 1 0 C C C C C C C STRA STRB parallel I/O single chip Figure 1.2 68HC11A8 block diagram A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 A D 0 R/W AS expanded A/D converter port E PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 V V REFH REFL interrupts RESET XIRQ IRQ oscillator XTAL EXTAL E MODA (LIR) MODB (V STB ) mode select power V V DD SS
Examples of microcontroller applications controller of the following machines displays printers keyboards modems charge card phones refrigerators washing machines microwave ovens automobile engine fuel injection fax machines etc. - - - - - - - - - - -
Semiconductor memory Random-access memory (RAM): same amount of time is required to access any location on the same chip Read-only memory (ROM): can only be read but not written by the processor - - Random-access memory - Dynamic random-access memory (DRAM): periodic refresh is required to maintain the contents of a DRAM chip - Static random-access memory (SRAM): no periodic refresh is required Read-only memory - Mask-programmed read-only memory (MROM): programmed when being manufactured - Programmable read-only memory (PROM): the memory chip can be programmed by the end user
- Erasable programmable ROM (EPROM) 1. electrically programmable many times 2. erased by ultraviolet light (through a window) 3. erasable in bulk (whole chip in one erasure operation) - Electrically erasable programmable ROM (EEPROM) 1. electrically programmable many times 2. electrically erasable many times 3. can be erased one location, one row, or whole chip in one operation - Flash memory 1. electrically programmable many times 2. electrically erasable many times 3. can only be erased in bulk
Computer software Computer programs are known as software A program is a sequence of instructions Machine instruction A sequence of binary digits which can be executed by the processor Hard to understand for human being Assembly language Defined by assembly instructions An assembly instruction is a mnemonic representation of a machine instruction Assembly programs must be translated before it can be executed -- translated by an assembler
High-level language Syntax of a high-level language is similar to English A translator is required to translate the program written in a high-level language -- done by a compiler Source code A program written in assembly or high-level language Object code The output of an assembler or compiler
The 68HC11 Registers 7 Accumulator A 0 7 Accumulator B 0 15 Double accumulator D 0 15 Index register IX 0 15 Index register IY 0 15 Stack pointer 0 15 Program counter 0 S X H I N Z V C A:B D IX IY SP PC CCR Carry Overflow Zero Negative I interrupt mask Half-carry (from bit 3) X interrupt mask Stop disable Figure 1.3 M68HC11 programmer’s model
Data transfer between CPU and memory involves address bus and data bus CPU memory address bus lines data bus lines Figure 1.5 Data transfer between CPU and memory address contents Memory Addressing Memory consists of addressable locations A memory location has 2 components: address and contents
68HC11 addressing modes Table 1.1 Prefix for number representation Base Prefix binary octal decimal hexadecimal % @ nothing* $ *Note: Some assemblers use & Immediate mode The actual argument is contained in the byte or bytes immediately following the instruction opcode Operands needed in an instruction are specified by one of the 6 addressing modes LDAA #22 ADDA #@32 LDD #1000
Direct mode A one-byte value is used as the address of a memory operand ADDA $10 SUBA $20 LDD $30 Extended mode A two-byte value is used as the address of a memory operand LDAA $1000 LDX $1000 ADDD $1030 Indexed mode The sum of one of the index registers and an 8-bit value is used as the address of a memory operand ADDA 10,X LDAA 3,Y
Inherent mode Operands are implied by the instruction No address information is needed ABA INCB INX Relative mode Used in branch instructions to specify the branch target Specified using either a 16-bit value or a label (preferred) ... BEQ there ADDA #10 ... DECB there
A Sample of 68HC11 Instructions The LOAD instructions A group of instructions that place a value or copy the contents of a memory location (or locations) into a register LDAA <opr> LDAB <opr> LDD <opr> LDX <opr> LDY <opr> LDS <opr> <opr> can be immediate, direct, extended, or index mode Examples LDAA $10 LDX #$1000
The ADD instruction A group of instructions perform addition operation ABA ABX ABY ADDA <opr> ADDB <opr> ADDD <opr> ADCA <opr> ADCB <opr> <opr> is specified using immediate, direct, extended, or index mode Examples. ADDA #10 ADDA $20 ADDD $30
The SUB instruction A group of instructions that perform the subtract operation SBA SUBA <opr> SUBB <opr> SUBD <opr> SBCA <opr> SBCB <opr> <opr> can be immediate, direct, extended, or index mode Examples SUBA #10 SUBA $10 SUBA 0,X SUBD 10,X
The STORE instruction A group of instructions that store the contents of a register into a memory location or memory locations STAA <addr> STAB <addr> STD <addr> STX <addr> STY <addr> STS <addr> <addr> can be direct, extended, or index mode Examples: STAA $20 STAA 10,X STD $10 STD $1000 STD 0,X
The 68HC11 Machine Code A 68HC11 instruction consists of 1 to 2 bytes of opcode and 0 to 3 bytes of operand information Assembly instruction Machine instructions (in hex format) LDAA #29 86 1D STAA $00 97 00 ADDA $02 9B 02 STAA $01 97 01 INY 18 08 Examples
Decoding machine language instructions Procedure Step 1: compare the first one or two bytes with the opcode table to identify the corresponding assembly mnemonic and format. Step 2: identify the operand bytes after the opcode field. Step 3: write down the corresponding assembly instruction. Step 4: repeat step 1 to 3 until the machine code file is exhausted. A sample of machine codes and assembly instruction format machine code assembly instruction format 01 NOP 86 LDAA IMM 96 LDAA DIR C6 LDAB IMM D6 LDAB DIR CC LDD IMM DC LDD DIR 8B ADDA IMM 9B ADDA DIR CB ADDB IMM
DB ADDB DIR C3 ADDD IMM D3 ADDD DIR 97 STAA DIR D7 STAB DIR DD STD DIR machine code assembly instruction format Example . Disassemble the following machine code to its corresponding assembly instructions. 96 30 8B 07 97 30 96 31 Solution: The disassembly process starts from the leftmost byte. We next look up the machine code table to see which instruction it corresponds to. Instruction 1. Step 1. The first byte 96 corresponds to the instruction LDAA DIR. Step 2. The second byte, 30, is the direct address. Step 3. Therefore, the first instruction is LDAA $30.
Instruction 2. Step 1. The third byte (8B) corresponds to the instruction ADDA IMM. Step 2. The immediate value is 07. Step 3. Therefore, the second instruction is ADDA $07. Instruction 3. Step 1. The fifth byte (97) corresponds to the instruction STAA DIR. Step 2. The DIR address is the next byte 30. Step 3. Therefore, the third instruction is STAA $30. Instruction 4. Step 1. The seventh byte (96) corresponds to the instruction LDAA DIR. Step 2. The DIR value is the next byte 31. Step 3. Therefore, the four instruction is LDAA $31.
The 68HC11 Instruction Execution Cycle - Perform a sequence of read cycles to fetch instruction opcode byte and address information. - Optionally perform read cycle(s) required to fetch the memory operand. - Perform the operation specified by the opcode. - Optionally write back the result to a register or a memory location.