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An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems Chin-Hsien Wu  and  Tei-Wei Kuo Dept....
Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL  ...
Why Flash Memory <ul><li>Diversified Application Domains </li></ul><ul><ul><li>Portable Storage Devices </li></ul></ul><ul...
Organization of a Typical NAND Flash Memory Erasing of a block time (2ms) > Writing of a page time (200us) >  Reading of a...
Flash Memory Characteristics <ul><li>Write-Once </li></ul><ul><ul><li>No writing on the same page unless its residing bloc...
Example: Garbage Collection Flash Memory Characteristics A live page A dead page A free page This block is to be recycled....
Example: Garbage Collection L L D L L L D L F L L L L D L L F L L F D L L D D D D A live page A dead page A free page Live...
Example: Garbage Collection A live page A dead page A free page <ul><li>The block is then erased. </li></ul><ul><li>Overhe...
Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL  ...
System Architecture Garbage Collection Address Translation FTL/NFTL Layer File system (FAT, EXT2, NTFS......) Device Drive...
System Architecture – FTL  Flash Translation Layer
Memory Space Requirements – FTL <ul><li>The problem is large memory space requirements. </li></ul><ul><ul><li>FTL adopts a...
System Architecture  – NFTL  <ul><li>A logical address is divided into  </li></ul><ul><ul><li>a virtual block address (VBA...
Memory Space Requirements - NFTL <ul><ul><li>NFTL does not need large memory space requirements, compared to FTL. </li></u...
Address Translation Time - NFTL <ul><li>The address translation performance of read and write requests can be deteriorated...
Garbage Collection Overhead - NFTL 3. Overhead is 2 block erases and 5 page writes. <ul><li>Copy the most-recent content t...
Space Utilization - NFTL 3 free pages are wasted.
Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL  ...
Motivation <ul><li>An adaptive two-level management design of a flash translation   layer ,  called   AFTL .  </li></ul><u...
AFTL – Coarse-to-Fine Switching <ul><li>AFTL doesn’t erase the two blocks immediately. </li></ul>2.  AFTL moves the mappin...
AFTL – Fine-to-Coarse Switching <ul><li>The number of the fine-grained slots is limited.  </li></ul><ul><ul><li>Some least...
AFTL – Fine-to-Coarse Switching <ul><li>Coarse-to-fine switches would introduce fine-to-coarse switches and overhead in va...
The Advantages of AFTL <ul><li>Improve the address translation performance. </li></ul><ul><ul><li>It is because the moving...
Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL  ...
Performance Evaluation <ul><li>Performance Setup </li></ul><ul><ul><li>The characteristics of the experiment trace was ove...
Performance Evaluation <ul><li>Performance Setup </li></ul><ul><ul><li>The maximum number of fine-grained slots is control...
Memory Space Requirements <ul><li>1.   MFS  ranged from 2,500, 5,000, 7,500, 10,000, 12,500, to 15,000. </li></ul><ul><li>...
Address Translation Performance <ul><ul><li>1 .   Larger  MFS  => smaller address translation time  - More address transla...
Garbage Collection Overhead <ul><li>AFTL outperforms NFTL.  </li></ul><ul><ul><li>- Coarse-to-fine switches can avoid imme...
Space Utilization <ul><li>The Space utilization might be better under AFTL. </li></ul><ul><ul><li>- Coarse-to-fine switche...
Conclusion <ul><li>AFTL is  proposed  to </li></ul><ul><ul><li>exploit the advantages of fine-grained/coarse-grained addre...
Q & A <ul><li>Question  </li></ul><ul><li>& Answer </li></ul>
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ICCAD AFTL presentation (PPT)

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ICCAD AFTL presentation (PPT)

  1. 1. An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems Chin-Hsien Wu and Tei-Wei Kuo Dept. of Comp. Sci. & Info. Engr. National Taiwan University ICCAD 2006
  2. 2. Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL </li></ul><ul><li>Performance Evaluation </li></ul><ul><li>Conclusion </li></ul>
  3. 3. Why Flash Memory <ul><li>Diversified Application Domains </li></ul><ul><ul><li>Portable Storage Devices </li></ul></ul><ul><ul><li>Consumer Electronics </li></ul></ul><ul><ul><li>Industrial Applications </li></ul></ul><ul><li>SoC and Hybrid Devices </li></ul><ul><ul><li>Critical System Components </li></ul></ul>
  4. 4. Organization of a Typical NAND Flash Memory Erasing of a block time (2ms) > Writing of a page time (200us) > Reading of a page time (50us) … Block 0 Block 1 Block 2 Block 3 Erase one block 1 Page = 512B + 16B 1 Block = 32 pages … Read/Write one page Flash Memory Characteristics 512B 16B User Area Spare Area
  5. 5. Flash Memory Characteristics <ul><li>Write-Once </li></ul><ul><ul><li>No writing on the same page unless its residing block is erased! </li></ul></ul><ul><ul><li>Pages are classified into valid, invalid, and free pages. </li></ul></ul><ul><li>Bulk-Erasing </li></ul><ul><ul><li>Pages are erased in a block unit to recycle used but invalid pages. </li></ul></ul><ul><li>Wear-Leveling </li></ul><ul><ul><li>Each block has a limited lifetime in erasing counts. </li></ul></ul>
  6. 6. Example: Garbage Collection Flash Memory Characteristics A live page A dead page A free page This block is to be recycled. (3 live pages and 5 dead pages) L D D L D D L D L L D L L L F D L F L L L L D F F L L F L L F D
  7. 7. Example: Garbage Collection L L D L L L D L F L L L L D L L F L L F D L L D D D D A live page A dead page A free page Live data are copied to somewhere else. L D D D D Flash Memory Characteristics
  8. 8. Example: Garbage Collection A live page A dead page A free page <ul><li>The block is then erased. </li></ul><ul><li>Overheads: </li></ul><ul><li>live data copying </li></ul><ul><li>block eraseing. </li></ul>L L D L L L D L F L L L L D L L F L L F D L L F F F F F F F F L Flash Memory Characteristics
  9. 9. Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL </li></ul><ul><li>Performance Evaluation </li></ul><ul><li>Conclusion </li></ul>
  10. 10. System Architecture Garbage Collection Address Translation FTL/NFTL Layer File system (FAT, EXT2, NTFS......) Device Driver fwrite(file,data) Block write (LBA,size) Flash I/O Requests Control signals File Systems process process process Applications Flash-Memory Storage System Physical Devices (Flash Memory Banks) process
  11. 11. System Architecture – FTL Flash Translation Layer
  12. 12. Memory Space Requirements – FTL <ul><li>The problem is large memory space requirements. </li></ul><ul><ul><li>FTL adopts a page-level address translation mechanism . </li></ul></ul>For example, 256MB NAND flash with a page size of 512 bytes needs 524,288 (256*1024*1024/512) entries Assume that an entry needs 4 bytes, the address translation information of FTL requires 2,048KB memory space. FTL needs large memory space for the address translation table
  13. 13. System Architecture – NFTL <ul><li>A logical address is divided into </li></ul><ul><ul><li>a virtual block address (VBA) </li></ul></ul><ul><ul><li>a block offset. </li></ul></ul>. . . (9,23) . . . NFTL Address Translation Table (in main-memory) Free Free Free Used Free Free Free Free Used Used Free Free Free Free Free Free A Primary Block Address = 9 A Replacement Block Address = 23 If the page has been used Write to the first free page <ul><li>LBA=1011 </li></ul><ul><ul><li>VBA = 1011 / 8 = 126 </li></ul></ul><ul><ul><li>block offset = 1011 % 8 = 3 </li></ul></ul>Write data to LBA=1011 VBA=126 Block Offset=3
  14. 14. Memory Space Requirements - NFTL <ul><ul><li>NFTL does not need large memory space requirements, compared to FTL. </li></ul></ul><ul><ul><ul><li>NFTL adopts a block-level address translation. </li></ul></ul></ul><ul><ul><li>NFTL would need 64KB memory space to store 16,384 (256*1024/16) entries for 256MB NAND flash. </li></ul></ul><ul><ul><ul><li>Assume that a block consists of 32 pages. </li></ul></ul></ul>
  15. 15. Address Translation Time - NFTL <ul><li>The address translation performance of read and write requests can be deteriorated, due to linear searches of physical addresses. </li></ul><ul><li>Assume that each block contains 8 pages. </li></ul><ul><li>Let LBA A, B, C, D, and E be written for 5, 5, 1, 1, and 1 times, respectively. Their data distribution could be like to what in the left figure. </li></ul><ul><li>For example, it might need to scan 9 spare areas for LBA B. </li></ul>
  16. 16. Garbage Collection Overhead - NFTL 3. Overhead is 2 block erases and 5 page writes. <ul><li>Copy the most-recent content to the new primary block. </li></ul>2. Erase the old primary block and the replacement block.
  17. 17. Space Utilization - NFTL 3 free pages are wasted.
  18. 18. Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL </li></ul><ul><li>Performance Evaluation </li></ul><ul><li>Conclusion </li></ul>
  19. 19. Motivation <ul><li>An adaptive two-level management design of a flash translation layer , called AFTL . </li></ul><ul><ul><li>Exploit the advantages of the fine-grained address mechanism and the coarse-grained address mechanism . </li></ul></ul>Low More Long Small NFTL Much Better than NFTL High Space Utilization Much Better than NFTL Less Garbage Collection Overhead Much Better than NFTL Short Address Translation Time A little larger than NFTL Large Memory Space Requirements AFTL FTL
  20. 20. AFTL – Coarse-to-Fine Switching <ul><li>AFTL doesn’t erase the two blocks immediately. </li></ul>2. AFTL moves the mapping information of the replacement block to the fine-grained hash table by adding fine-grained slots. 3. The RPBA field of the corresponding mapping information is nullified.
  21. 21. AFTL – Fine-to-Coarse Switching <ul><li>The number of the fine-grained slots is limited. </li></ul><ul><ul><li>Some least recently used mapping information of fine-grained slots should be moved to the coarse-grained hash table. </li></ul></ul>(F, PBAE) <ul><li>Assume that this fine-grained slot is to be replaced. </li></ul><ul><li>Data stored in the page with the given (physical) address are copied to the primary or replacement block of the corresponding coarse-grained slot, as defined by NFTL. </li></ul>3. If there dose not exist any corresponding coarse-grained slot, a new one is created.
  22. 22. AFTL – Fine-to-Coarse Switching <ul><li>Coarse-to-fine switches would introduce fine-to-coarse switches and overhead in valid page copying. </li></ul><ul><ul><li>It is because the number of the fine-grained slots is limited. </li></ul></ul><ul><li>Stop any coarse-to-fine switch when some frequency bound in coarse-to-fine switches is reached. </li></ul><ul><ul><li>We set a parameter in the experiments to control the frequency of switches to explore the behavior of the proposed mechanism. </li></ul></ul>
  23. 23. The Advantages of AFTL <ul><li>Improve the address translation performance. </li></ul><ul><ul><li>It is because the moving of their mapping information to the fine-grained hash table. </li></ul></ul><ul><li>Improve the garbage collection overhead. </li></ul><ul><ul><li>The delayed recycling of any replacement block reduces the potential number of valid data copyings and blocks erased. </li></ul></ul><ul><li>Improve the space utilization. </li></ul><ul><ul><li>The delayed recycling of any primary block lets free pages of a primary block be likely used in the future. </li></ul></ul>
  24. 24. Contents <ul><li>Characteristics of Flash Memory </li></ul><ul><li>FTL versus NFTL </li></ul><ul><li>Our Approach – AFTL </li></ul><ul><li>Performance Evaluation </li></ul><ul><li>Conclusion </li></ul>
  25. 25. Performance Evaluation <ul><li>Performance Setup </li></ul><ul><ul><li>The characteristics of the experiment trace was over a 20GB disk. </li></ul></ul>1,669,228 Different LBA’s 13,198,805 / 2,797,996 sectors Total Write / Read Requests One week Durations Web Applications, E-mail Clients, MP3 Player, MSN Messenger, Word, Excel, PowerPoint, Media, Player, Programming, and Virtual Memory Activities Applications NTFS File Systems Windows XP OS 320 MB RAM Intel Celeron 750MHz CPU
  26. 26. Performance Evaluation <ul><li>Performance Setup </li></ul><ul><ul><li>The maximum number of fine-grained slots is controlled by a parameter MFS . </li></ul></ul><ul><ul><li>A parameter ST controls the frequency of switches between the two address translation mechanisms – n/ ST . </li></ul></ul><ul><ul><ul><li>ST=0 => No constraint on the number of switches. </li></ul></ul></ul><ul><ul><ul><li>Smaller ST => More switches. </li></ul></ul></ul><ul><ul><ul><li>Larger ST => Less switches. </li></ul></ul></ul>
  27. 27. Memory Space Requirements <ul><li>1. MFS ranged from 2,500, 5,000, 7,500, 10,000, 12,500, to 15,000. </li></ul><ul><li>2. AFTL uses a little more memory space than NFTL. </li></ul>
  28. 28. Address Translation Performance <ul><ul><li>1 . Larger MFS => smaller address translation time - More address translations going through the fine-grained address translation mechanism. </li></ul></ul><ul><ul><li>2. Smaller ST => longer address translation time - More coarse-to-fine switches </li></ul></ul>
  29. 29. Garbage Collection Overhead <ul><li>AFTL outperforms NFTL. </li></ul><ul><ul><li>- Coarse-to-fine switches can avoid immediately recycling of their primary and replacement blocks and related valid data copyings. </li></ul></ul><ul><ul><li>- A smaller ST value can increase the number of coarse-to-fine switches. </li></ul></ul>
  30. 30. Space Utilization <ul><li>The Space utilization might be better under AFTL. </li></ul><ul><ul><li>- Coarse-to-fine switches can delay the recycling of replacement blocks. </li></ul></ul><ul><ul><li>- Free pages of primary blocks might be used in the future.. </li></ul></ul>
  31. 31. Conclusion <ul><li>AFTL is proposed to </li></ul><ul><ul><li>exploit the advantages of fine-grained/coarse-grained address translation mechanisms, and to </li></ul></ul><ul><ul><li>switch dynamically and adaptively the mapping information between the two address translation mechanisms. </li></ul></ul><ul><li>AFTL does provide good performance in address mapping and space utilization and have garbage collection overhead and memory space requirements under proper management. </li></ul>
  32. 32. Q & A <ul><li>Question </li></ul><ul><li>& Answer </li></ul>

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