Flash-Memory Storage Systems: Design Issues and Challenges

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Flash-Memory Storage Systems: Design Issues and Challenges

  1. 1. Flash-Memory Storage Systems: Design Issues and Challenges Tei-Wei Kuo Department of Computer Science & Information Engineering National Taiwan University
  2. 2. Agenda Introduction Management Issues Behavior Analysis Reliability – Wear Leveling Other Challenging Issues Conclusion 2008/7/14 Embedded Systems and Wireless Networking Lab. 2
  3. 3. Introduction – Why Flash Memory Diversified Application Domains Portable Storage Devices Consumer Electronics Industrial Applications Critical System Components 2008/7/14 Embedded Systems and Wireless Networking Lab. 3
  4. 4. Trends in VLSI Technology Source: www.icknowledge.com 2008/7/14 Embedded Systems and Wireless Networking Lab. 4 * This slide was from the ASP-DAC’06 talk delivered by Prof. SangLyul. Min from the Seoul National University.
  5. 5. Flash Makers – NAND Flash Memory [EE Times,11/30/2007] For years, NAND prices have dropped by an average of 40 percent or more per year. Source: iSuppli Corp (Unit: Million Dollars) http://hugoleijtens.spaces.live.com/blog/cns!4B94B7453D4BFD9E!988.entry 2008/7/14 Embedded Systems and Wireless Networking Lab. 5
  6. 6. Trends – Storage Media September 2006 Samsung 2GB USB 2.0 Flash Drive Price: $49.99 Less Rebate: - $25.00 Final Price: $24.99* T-One 2GB Microdrive/3600RPM $144.99 Source: Using multilevel cell NAND flash technology in consumer applications, Electronic Engineering Times, July ,2005 2008/7/14 Embedded Systems and Wireless Networking Lab. 6
  7. 7. Trends – Storage Media March 2007 Transcend 8GB CompactFlash Card Price: $84.85 SanDisk 4GB CompactFlash Card Price: $55.99 Microdrive 4GB Compact Flash Type II Source: Using multilevel cell NAND flash technology in consumer applications, Price: $116 Electronic Engineering Times, July ,2005. Amazon.com 2008/7/14 Embedded Systems and Wireless Networking Lab. 7
  8. 8. Trends – Storage Media July 2008 Transcend 8GB Seagate FreeAgent SDHC SD CARD Desktop 500 GB (USD23.77) 3.5" USB 2.0 External Hard Drive (USD104.99) HITACHI 6GB Microdrive MD6GBBP (USD169.95, Feb 2008 No Longer Carried in July) 20Gb IBM HDD Source: Using multilevel cell NAND flash technology in consumer applications, Electronic Engineering Times, July ,2005 Component Times, Nov 2007.; March/July 2008, www. amazon.com 2008/7/14 Embedded Systems and Wireless Networking Lab. 8
  9. 9. Flash Stories – Solid-State Disks < 50% Heat, Ultra Silence, Light Weight, MTTF – 200M hours (HDD – 30M hours), Energy Efficiency Transcend 32GB SSD, 2.5- Inch, SATA, MLC (USD343.30 (2008/03) USD202.79 (2008/07)) IDC, SanDisk - Component Times, Nov 2007 2008/7/14 Embedded Systems and Wireless Networking Lab. 9
  10. 10. Flash Stories – Flash Wars Fab 300mm Wafer Fab by Toshiba and SanDisk at Yokkaichi, Japan 80,000 Wafers per Month (2008) 210,000 Wafers per Month 300mm Wafer Fab by IM Flash Technologies (Intel & Micron) at Utah Joint Venture: Sony and Qimonda, Hynix and Sandisk Technology 32nm (Samsung, Intel), 43nm (Toshiba), 50nm (IM) 2008/7/14 Embedded Systems and Wireless Networking Lab. 10
  11. 11. Introduction – The Characteristics of Storage Media Access time Media Read Write Erase DRAM 5ns (1B) 5ns (1B) - 2.56us (512B) 2.56us (512B) NOR FLASH 13X 150ns (1B) 83X 211us (1B) 1.2s (16KB) 14.4us (512B) 3.52ms (512B) NAND FLASH 20us (1B) 200us (1B) 1.5ms (128KB) 32.8us (512B) 212us (512B) DISK 400X 12.4ms (512B) 50X 12.4 ms(512B) - (average) (average) *Flash Erase Time: NOR(10ms), NAND (1.5ms) [Reference] DRAM: DDR-400. NOR FLASH: Intel 28F128J3A-150. NAND FLASH: Samsung K9K8G08U0M. Disk: Segate Barracuda ATA II.1 1. Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, and Cheng-Chih Yang, "A NOR Emulation Strategy over NAND Flash Memory," the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Daegu, Korea , August 21-24, 2007.
  12. 12. Introduction – Single-Level Cell (SLC) Each Word Line is connected to control gates. Each Bit Line is connected to the drain. Control Gate Drain Source Cell IDS Selected cell 2008/7/14 Embedded Systems and Wireless Networking Lab. 12
  13. 13. Introduction – Multi-Level Cell (MLC) vs SLC NUMBER OF CELLS 2008/7/14 Embedded Systems and Wireless Networking Lab. 13
  14. 14. Introduction – Consumer Applications 2008/7/14 Electronic Engineering Wireless Networking Lab. Embedded Systems and Times, July 2005 14
  15. 15. Bandwidth Requirements – Video ˇ ˇ Electronic Engineering Times, July 2005 2008/7/14 Embedded Systems and Wireless Networking Lab. 15
  16. 16. Bandwidth Requirements – Audio ˇ ˇ Electronic Engineering Times, July 2005 2008/7/14 Embedded Systems and Wireless Networking Lab. 16
  17. 17. Introduction – Challenges in Flash- Memory Storage Designs Requirements in Good Performance Limited Cost per Unit Increasing in Access Frequencies Strong Demands in Reliability Tight Coupling with Other Components Low Compatibility among Vendors 2008/7/14 Embedded Systems and Wireless Networking Lab. 17
  18. 18. Agenda Introduction Management Issues Behavior Analysis Reliability – Wear Leveling Other Challenging Issues Conclusion 2008/7/14 Embedded Systems and Wireless Networking Lab. 18
  19. 19. Management Issues – System Architectures AP AP AP AP File-System Layer Block Device Layer (FTL emulation) MTD drivers Flash Memory 2008/7/14 Embedded Systems and Wireless Networking Lab. 19
  20. 20. Management Issues – Flash-Memory Characteristics Write one 1 Page = 512B page 1 Block = 32 pages(16KB) Block 0 Block 1 Block 2 Block 3 Erase …… …… one block 2008/7/14 Embedded Systems and Wireless Networking Lab. 20
  21. 21. Management Issues – Flash-Memory Characteristics Write-Once No writing on the same page unless its residing block is erased! Pages are classified into valid, invalid, and free pages. Bulk-Erasing Pages are erased in a block unit to recycle used but invalid pages. Wear-Leveling Each block has a limited lifetime in erasing counts. 2008/7/14 Embedded Systems and Wireless Networking Lab. 21
  22. 22. Management Issues – Flash-Memory Characteristics Example 1: Out-place Update A B C D Live pages Free pages Suppose that we want to update data A and B… 2008/7/14 Embedded Systems and Wireless Networking Lab. 22
  23. 23. Management Issues – Flash-Memory Characteristics Example 1: Out-place Update A B C D A B Dead pages 2008/7/14 Embedded Systems and Wireless Networking Lab. 23
  24. 24. Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection L D D L D D L D This block is to be recycled. L L D L L L F D (3 live pages and 5 dead pages) L F L L L L D F A live page F L L F L L F D A dead page A free page 2008/7/14 Embedded Systems and Wireless Networking Lab. 24
  25. 25. Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection D D D D D D D D Live data are copied to somewhere else. L L D L L L L D L F L L L L D L A live page L L L F L L F D A dead page A free page 2008/7/14 Embedded Systems and Wireless Networking Lab. 25
  26. 26. Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection F F F F F F F F The block is then erased. L L D L L L L D Overheads: •live data copying L F L L L L D L •block erasing. A live page L L L F L L F D A dead page A free page 2008/7/14 Embedded Systems and Wireless Networking Lab. 26
  27. 27. Management Issues – Flash-Memory Characteristics Example 3: Wear-Leveling Wear-leveling might 100 L D D L D D L D A interfere with the 10 decisions of the block- L L D L L L F D B recycling policy. 20 L F L L L L D F C A live page 15 A dead page F L L F L L F D D A free page Erase cycle counts 2008/7/14 Embedded Systems and Wireless Networking Lab. 27
  28. 28. Management Issues – Challenges The write throughput drops significantly after garbage collection starts! The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly. Reliability becomes more and more critical when the manufacturing capacity increases! The significant increment of flash-memory access rates seriously exaggerates the Read/Program Disturb Problems! 2008/7/14 Embedded Systems and Wireless Networking Lab. 28
  29. 29. Agenda Introduction Management Issues Behavior Analysis Performance vs Overheads – FTL vs NFTL Trace Study Reliability – Wear Leveling Other Challenging Issues Conclusion 2008/7/14 Embedded Systems and Wireless Networking Lab. 29
  30. 30. System Architecture fwrite(file,data) process process process process Applications File system (FAT, EXT2, NTFS......) File Systems Block write (LBA,size) FTL/NFTL Garbage Address Layer Collection Translation Flash I/O Requests Flash-Memory Storage System Device Driver Control signals Physical Devices (Flash Memory Banks) 2008/7/14 Embedded Systems and Wireless Networking Lab. 30
  31. 31. 31 System Architecture SD, xD, MemoryStick, SmartMedia CompactFlash *FTL: Flash Translation Layer, MTD: Memory Technology Device 2008/1/30 2008/7/14 31 Embedded Systems and Wireless Networking Lab. 31
  32. 32. Policies – FTL FTL adopts a page-level address translation mechanism. The main problem of FTL is on large memory space requirements for storing the address translation information. Embedded Systems and Wireless Networking Lab. 32 2008/7/14
  33. 33. Policies – NFTL (Type 1) A logical address under NFTL is divided into a virtual block address and a block offset. e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3 NFTL A Chain Block A Chain Block A Chain Block Address Translation Table Address = 9 Address = 23 Address = 50 Write data to (in main-memory) LBA=1011 Free Free Free Free Free Free . . Free Free Free . Used Used Free Free (9) Free Free Free . WriteIfto the Write to the the page has . Block Free with blockFree page been used with block page Free . Offset=3 VBA=126 Freeoffset=3 Free offset=3 Free 2008/7/14 Free Embedded Systems and Wireless Networking Lab. Free Free 33
  34. 34. Policies – NFTL (Type 2) A logical address under NFTL is divided into a virtual block address and a block offset. e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3 NFTL A Primary Block A Replacement Block Address Translation Table Address = 9 Address = 23 (in main-memory) Write data to Free Used LBA=1011 Free Used . . Free Used . Used Free (9,23) Free Free . If the page has been . Block Free to theused Free Write . Offset=3 first free page VBA=126 Free Free 2008/7/14 Free Embedded Systems and Wireless Networking Lab. Free 34
  35. 35. Policies – NFTL NFTL is proposed for the large-scale NAND flash storage systems because NFTL adopts a block-level address translation. However, the address translation performance of read and write requests might deteriorate, due to linear searches of address translation information in primary and replacement blocks. 2008/7/14 Embedded Systems and Wireless Networking Lab. 35
  36. 36. Policies – FTL or NFTL FTL NFTL Memory Space Requirements Large Small Address Translation Time Short Long Garbage Collection Overhead Less More Space Utilization High Low The Memory Space Requirements for one 1GB NAND (512B/Page, 4B/Table Entry, 32 Pages/Block) FTL: 8,192KB (= 4*(1024*1024*1024)/512) NFTL: 256KB (= 4*(1024*1024*1024)/(512*32)) Remark: Each page of small-block(/large-block) SLC NAND can store 512B(/2KB) data, and there are 32(/64) pages per block. Each page of MLCx2 NAND can store 2KB, and there are 128 pages per block. 2008/7/14 Embedded Systems and Wireless Networking Lab. 36
  37. 37. Address Translation Time - NFTL The address translation performance of read and write requests can be deteriorated, due to linear searches of physical addresses. 1. Assume that each block contains 8 pages. 2. Let LBA A, B, C, D, and E be written for 5, 5, 1, 1, and 1 times, respectively. Their data distribution could be like to what in the left figure. 3. For example, it might need to scan 9 spare areas for LBA B. 2008/7/14 Embedded Systems and Wireless Networking Lab. 37
  38. 38. Garbage Collection Overhead - NFTL 1. Copy the most-recent content to the new primary block. 2. Erase the old primary block and the replacement block. 3. Overhead is 2 block erases and 5 page writes. 2008/7/14 Embedded Systems and Wireless Networking Lab. 38
  39. 39. Space Utilization - NFTL 3 free pages are wasted. 2008/7/14 Embedded Systems and Wireless Networking Lab. 39
  40. 40. Agenda Introduction Management Issues Behavior Analysis Performance vs Overheads – FTL vs NFTL Trace Study Reliability – Wear Leveling Other Challenging Issues Conclusion P.-C. Huang, Y.-H. Chang, J.-W. Hsieh, and M. Lin, “The Behavior Analysis of Flash-Memory Storage Systems, IEEE ISORC’08. 2008/7/14 Embedded Systems and Wireless Networking Lab. 40
  41. 41. Flash Storage System Architecture 2008/7/14 Embedded Systems and Wireless Networking Lab. 41
  42. 42. Peak Read/Write Throughput The sequential access pattern LBA usually yields the best-case throughput Largest request of a flash-memory packet length storage system It is due to the address mapping and garbage collection ith access overheads 2008/7/14 Embedded Systems and Wireless Networking Lab. 42
  43. 43. Worst-Case Write Response Time Access patterns with small accesses to LB trigger garbage APass1 Pass2 collection activities The first pass fills the whole flash memory to force out-place updates The second pass actually triggers the updates and garbage collection ith access 2008/7/14 Embedded Systems and Wireless Networking Lab. 43
  44. 44. Reliability - First-Failure Time Access patterns that repetitively write to LBA some specific LBA’s to see whether the management facilities can evenly distribute the writes to PBA’s. Random accesses are inserted to avoid the caching ith access effects 2008/7/14 Embedded Systems and Wireless Networking Lab. 44
  45. 45. Agenda Introduction Management Issues Behavior Analysis Reliability – Wear Leveling Other Challenging Issues Conclusion Y.-H. Chang, J.-W. Hseuh, and T.-W. Kuo,, “Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design,” ACM/IEEE 44-th Design Automation Conference (DAC), San Diego, USA, June 2007. [Best Paper Nomination] 2008/7/14 Embedded Systems and Wireless Networking Lab. 45
  46. 46. Wear Leveling versus Product Lifetime Settings File system: FAT16 file system with 8KB cluster size Flash memory: 256MB small-block flash memory with 100K erase cycles Updating of a 16MB file repeatedly with the throughput: 0.1MBs The file requires 2K clusters = 16MB ÷ 8KB(cluster size) The FAT size of this file is 4KB (2K(clusters) x 2 bytes) The 20% of blocks in flash memory joins the dynamic wear leveling Data of a 16MB file is stored in 1K blocks (16MB ÷ 16KB(block size)) Suppose flash memory is managed in the block level File systems update the FAT in each cluster writing so that FAT is updated 2K times for a 16MB file Writing of a 16MB incurs 1K block erases because of the reclaiming of invalid space. 2008/7/14 Embedded Systems and Wireless Networking Lab. 46
  47. 47. Wear Leveling versus Product Lifetime Ways in Data Updates In-Place-Updates: Rewriting on the Same Page Dynamic Wear Leveling: Rewriting over Another Free Page with Erasing over Blocks with Dead Pages Static Wear Leveling: Rewriting over Another Free Page with Erasing over Any Blocks Expected Lifetime of 16(MB) 100 K NO Wear Leveling (in - place update) = × ≈ 0.09(days) 0.1(MB/second) 2 K × 24 × 60 × 60 16(MB) 16 K (blocks) × 20% ×100 K Dynamic Wear Leveling = × ≈ 197.5(days) 0.1(MB/second) (2 K + 1K ) × 24 × 60 × 60 16(MB) 16 K (blocks) ×100% ×100 K Static Wear Leveling = × ≈ 987.5(days) 0.1(MB/second) (2 K + 1K ) × 24 × 60 × 60 2008/7/14 Embedded Systems and Wireless Networking Lab. 47
  48. 48. Wear Leveling versus Product Lifetime Static Wear Leveling – Block-Level Mapping Use a counter for each block The garbage collector always finds the block with the least erase count. Some heuristic approach erases a block to maintain 2 free blocks when the garbage collector finds the erase count of the block is over a given threshold. Problems: High extra block erases and GC starts find a victim GC starts data to block block 15 Update data in block 3 4 Write new block live-page copyings High main-memory consumption 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 High computation cost Flash Memory : index in the selection of a victim block : index to the selected free block 5 5 5 5 4 5 5 4 5 5 4 5 4 5 5 5 4 5 4 4 5 Counter : block contains (some) valid data : free block : dead block 2008/7/14 Embedded Systems and Wireless Networking Lab. 48
  49. 49. Comparison of Different Technologies No Wear Leveling Dynamic Wear Leveling 5000 5000 4000 4000 Erase Cycles 3000 3000 2000 2000 1000 1000 0 0 0 20 40 60 80 100 0 20 40 60 80 100 Perfect SWL Intuitive SWL 5000 5000 Erase Cycles 4000 4000 3000 3000 2000 2000 1000 1000 0 0 0 20 40 60 80 100 0 20 40 60 80 100 49 Physical Block Addresses (PBA) Physical Block Addresses (PBA) 2008/7/14 Embedded Systems and Wireless Networking Lab.
  50. 50. An Efficient Static Wear Leveling Mechanism A modular design for compatibility considerations A SWL mechanism Block Erasing Table (BET) bit flags SW Leveler SWL-Procedure SWL-Update 2008/7/14 50 Embedded Systems and Wireless Networking Lab.
  51. 51. The Block Erasing Table (BET) A bit-array: Each bit is for 2k consecutive blocks. Small k – in favor of hot-cold data separation Large k – in favor of small RAM space ecnt=2 =3 =1 =0 ecnt=1 =4 =3 =2 =0 fcnt =2 =1 =0 fcnt =1 =2 =0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Flash BET 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 k=0 k=2 ecnt: the total number of block erases done since the BET is reset fcnt: the number of 1’s in the BET : an index to a block that the Cleaner wants to erase 51 : a block that has been erased in the current resetting interval 2008/7/14 Embedded Systems and Wireless Networking Lab.
  52. 52. Endurance Improvement - The First Failure Time When k=3 and T=100, the When k=0 and T=100, the endurance is improved by endurance is improved by 100.2%. 87.5%. 2008/7/14 52 Embedded Systems and Wireless Networking Lab.
  53. 53. Summary An Efficient Static Wear Leveling Mechanism Small Memory Space Requirement Less than 1KB for 8GB flash memory Efficient Implementation An adjustable house-keeping data structure An cyclic queue scanning algorithm Performance Evaluation Improvement Ratio of the Endurance: The ratio is more than 50% Extra Overhead: It is less than 3% of extra block erase There is limited overhead in live-page copyings 2008/7/14 53 Embedded Systems and Wireless Networking Lab.
  54. 54. Agenda Introduction Management Issues Behavior Analysis Reliability – Wear Leveling Other Challenging Issues Conclusion 2008/7/14 Embedded Systems and Wireless Networking Lab. 54
  55. 55. Challenging Issues – Reliability Each Word Line is connected to control gates. Each Bit Line is connected to the drain. Control Gate Drain Source Cell IDS Selected cell 2008/7/14 Embedded Systems and Wireless Networking Lab. 55
  56. 56. Challenging Issues – Reliability Read Operation Program Operation When the floating gate is Electrons are moved into not charged with electrons, the floating gate, and the there is current ID (100uA) threshold voltage is thus if a reading voltage is raised. applied. (“1” state) 5V 1V 2008/7/14 Embedded Systems and Wireless Networking Lab. 56
  57. 57. Challenging Issues – Reliability Over-Erasing Problems Fast Erasing Bits All of the cells connected to the same bit line of a depleted cell would be read as “1”, regardless of their values. Read/Program Disturb Problems DC erasing of a programmed cell, DC programming of a non-programmed cell, drain disturb, etc. Flash memory that has thin gate oxide makes disturb problems more serious! Data Retention Problems Electrons stored in a floating gate might be lost such that the lost of electrons will sooner or later affects the charging status of the gate! 2008/7/14 Embedded Systems and Wireless Networking Lab. 57
  58. 58. Challenging Issues – Observations The write throughput drops significantly after garbage collection starts! The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly. Reliability becomes more and more critical when the manufacturing capacity increases! The significant increment of flash-memory access rates seriously exaggerates the Read/Program Disturb Problems! Wear-leveling technology is even more critical when flash memory is adopted in many system components or might survive in products for a long life time! 2008/7/14 Embedded Systems and Wireless Networking Lab. 58
  59. 59. Conclusion What Is Happening? Solid-State Storage Devices New Designs in the Memory Hierarchy More Applications in System Components and Products Challenging Issues: Performance, Cost, and Reliability Scalability Technology Reliability Technology Interdisciplinary Work 2008/7/14 Embedded Systems and Wireless Networking Lab. 59
  60. 60. Contact Information • Professor Tei-Wei Kuo ktw@csie.ntu.edu.tw URL: http://csie.ntu.edu.tw/~ktw Flash Research: http://newslab.csie.ntu.edu.tw/~flash/ Office: +886-2-23625336-257 Fax: +886-2-23628167 Address: Dept. of Computer Science & Information Engr. National Taiwan University, Taipei, Taiwan 106 2008/7/14 Embedded Systems and Wireless Networking Lab. 60
  61. 61. Q&A
  62. 62. Comparison of SLC and MLC 1-bit/Cell SLC NAND Flash 100,000 Program/Erase cycles (with ECC)[1] 10 years Data Retention[1] 2-bits/Cell MLC NAND Flash 10,000 Program/Erase cycles (with ECC) [2] 10 years Data Retention[2] 4-bits/Cell MLC NAND FLASH Developers (2006) M-systems, Intel, Samsung, and Toshiba [1] ST Micro-electronics NAND SLC large page datasheet (NAND08GW3B2A) [2] ST Micro-electronics NAND MLC large page datasheet (NAND04GW3C2A) •USD34.65 per GB for NOR, •USD7.10 (SLC) and USD2.48 (MLCx2) per GB for NAND in 2008 Q1 2008/7/14 Embedded Systems and Wireless Networking Lab. 62
  63. 63. Introduction – Price and Read/Write Performance NOR NAND SLC NAND MLCx2 Price $34.55/GB $6.79/GB $2.48/GB Read 23.84 MB/sec 15.33 MB/sec 13.5 MB/sec Write 0.07 MB/sec 4.57 MB/sec 2.34 MB/sec Erase 0.22 MB/sec 85.33 MB/sec 170.66 MB/sec *NOR: Silicon Storage Technology (SST). NAND SLC: Samsung Electronics. K9F1G08Q0M. NAND MLCx2: ST STMicroelectronics[1,2] 1. Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, and Cheng-Chih Yang, "A NOR Emulation Strategy over NAND Flash Memory," the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Daegu, Korea , August 21-24, 2007. 2. Yuan-Hao Chang and Tei-Wei Kuo, “A Log-based Management Scheme for Low-cost Flash-memory Storage Systems of Embedded Systems”
  64. 64. Non-Volatile Memory Macronix International Co., Component Times, Nov. 2007 2008/7/14 Embedded Systems and Wireless Networking Lab. 64
  65. 65. Performance Comparison (Still Under Development) Lifetime / RAM Type R/W Speed Endurance Density Cost 25~100ns/1B3, Highly reliable, 1~4MB MRAM 2ns/1B in experiment5 20 yr data retention 1GB TBA2 4USD/1MB Highly reliable, PRAM 50ns/1B 1013 W/E cycles 4~64MB N/A Racetrack Higher than Lower than 20~32ns/1B4 Highly reliable1 Memory MRAM1 MRAM1 References 1. http://www.digitimes.com.tw/EDM/EDM_DTF970122END/H11.pdf 2. http://www.engadget.com/2008/06/02/toshiba-says-its-1gb-mram-chips-are-almost-ready-were-ready/ 3. http://203.66.161.5/document/mic_digi/Topology/report_topology/IA/2003/030806MRAM.pdf 4. http://en.wikipedia.org/wiki/Racetrack_memory 5. http://en.wikipedia.org/wiki/Magnetoresistive_Random_Access_Memory

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