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Japanese Journal of Applied Physics 48 (2009) 081203                                                                      ...
Jpn. J. Appl. Phys. 48 (2009) 081203                                                                                      ...
Jpn. J. Appl. Phys. 48 (2009) 081203                                                                                      ...
Jpn. J. Appl. Phys. 48 (2009) 081203                                                                                      ...
Jpn. J. Appl. Phys. 48 (2009) 081203                                                                                      ...
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Extended Word-Line NAND Flash Memory

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Extended Word-Line NAND Flash Memory

  1. 1. Japanese Journal of Applied Physics 48 (2009) 081203 REGULAR PAPER Extended Word-Line NAND Flash Memory Jang-Gn YunÃ, Il Han Park, Wandong Kim, Jong Duk Lee, and Byung-Gook Park Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea Received April 1, 2009; accepted May 26, 2009; published online August 20, 2009 A NAND flash memory array having extended word-lines is proposed. Without scarifying areal density, both physical gate length and charge storage node size are increased through the word-line extension process. Simple fabrication flow is delivered and device performances in a viewpoint of the short channel effect are simulated. The effect of gate length variation on the cell threshold voltage (VTH ) distribution is addressed. Programming characteristics in the inversion-type source/drain NAND flash memory are also described. Some side effects concerned with the program disturbance and cell-to-cell interference are investigated in comparison with the conventional NAND flash memory. # 2009 The Japan Society of Applied Physics DOI: 10.1143/JJAP.48.081203 1. Introduction pitch Lg Wgap The inversion-type source/drain NAND flash memory was introduced to suppress the short channel effect. The increase WL WL WL of effective channel length can be achieved by forming source/drain regions electrically through the word-line fringing field.1–4) However, another problem can be taken place in highly scaled devices. They are not free from the fluctuation issues. The gate line edge roughness5–7) and channel dopant fluctuation8–10) problems cause a threshold voltage (VTH ) variation. As a result, they lead to a large cell Conventional NAND VTH distribution in NAND flash memories. Si substrate On the other hand, the devices can suffer from charge (a) variability issues because of the reduced volume of a charge storage node.11) The number of programmed charges Wgap’ declines as the size of the charge storage node shrinks Lg’ pitch down. Hence, only small amount of charge loss can induce a large VTH shift, thereby causing the retention characteristic to deteriorate. In consequence, not only the short channel effect but also these variation issues limit the scaling of the WL WL WL NAND flash memory. In this paper, the extended word-line NAND flash memory is proposed as shown in Fig. 1 to make the device immune from the short channel effect and the variability issues. The idea comes from the fact that the gap between word-lines is not necessarily needed to have same width as Extended WL NAND the gate length (Lg 6¼ Wgap ). In case of the NOR-type flash Si substrate memory array, bit-line contacts are required on every drain (b) regions.12,13) Therefore, enough space should be ensured on drain sides for contact process and its margin. However, the Fig. 1. (Color online) (a) Array structure of the conventional and source/drain just acts as segregation regions among word- (b) the extended word-line NAND flash memories. The gap between lines in the NAND flash memory array and this space can be word-lines is used to extend the word-line physically. used to extend the word-line physically within a fixed pitch (L0g > Wgap , Lg þ Wgap ¼ one pitch). 0 0 0 to the conformal deposition characteristic of the chemical 2. Possible Fabrication Process Flow vapor deposition (CVD) system.15) Then, the etching process Simplified fabrication process flow of the extended word- of the remaining poly-Si and oxide–nitride–oxide (ONO) line NAND flash memory array is illustrated in Fig. 2. First, dielectrics is resumed. Finally, source/drain regions are polycrystalline silicon (poly-Si) and oxide are deposited and formed through the ion implantation and activation. In case they are patterned in order to form word-lines. During the of the inversion-type source/drain NAND flash memory, the poly-Si etching process, it is stopped on the way and oxide final process can be skipped. spacer is made by the oxide deposition and etch-back process.14) The spacer width determines the word-line length 3. Results and Discussion and it can be controlled by the deposited oxide thickness due 3.1 Effect of the extended word-line To characterize the device performance of the extended à E-mail address: jgyun7@snu.ac.kr word-line NAND flash memory, the array structure illus- 081203-1 # 2009 The Japan Society of Applied Physics
  2. 2. Jpn. J. Appl. Phys. 48 (2009) 081203 J.-G. Yun et al. -3 Oxide hardmask 10 Oxide hardmask -6 10 Conventional Poly Si Poly Si -9 10 ID (A/μm) 10 -12 Extended WL (Lg' = 50 nm) Si substrate Si substrate -15 10 1. Poly-Si and oxide dep. 2. Word-line patterning Half pitch = 30 nm & poly-Si etch -18 10 Oxide spacer -3 -2 -1 0 1 2 3 etch VWL (V) Fig. 4. (Color online) ID –VWL characteristics of the conventional and Poly Si Poly Si the extended word-line NAND flash memories. The short channel effect is suppressed substantially. Si substrate Si substrate 0.5 VTH variation (V) 0.266 V 3. Oxide spacer formation 4. Poly-Si and ONO etch 0.0 Fig. 2. (Color online) Process flow for the extended word-line -0.5 2.011 V NAND flash memory. -1.0 Conventional Extended WL -1.5 -10 -5 0 5 10 ΔLedge (nm) (a) -3 -3 10 10 -6 Conventional -6 Extended WL 10 10 -9 -9 ID (A/μm) ID (A/μm) 10 10 -10 nm Half pitch = 30 nm ΔLedge = -10 nm Lg’ = 50 nm -12 10 ΔLedge = 10 nm -12 10 10 nm Wgap’ = 10 nm -15 0 nm -15 10 10 VGSL = VSSL = VBL = 1.5 V -18 10 -6 -4 -2 0 2 4 -18 10 -6 -4 -2 0 2 4 VPASS = 6 V VWL (V) VWL (V) (b) (c) Fig. 3. (Color online) Simulated array structure of the extended word-line NAND flash memory. Fig. 5. (Color online) (a) VTH change as a result of the word-line length variation and ID –VWL curves with different ÁLedge from À10 to 10 nm in (b) the conventional and (c) the extended word-line NAND trated in Fig. 3 is used. With minimum feature size of 30 nm, flash memories. 0 the word-line is extended to have Lg of 50 nm. Hence, the 0 gap between word-lines (Wgap ) becomes 10 nm. Conven- tional NAND flash memory is also simulated for comparison in 3D devices. After all, 20- to 30-nm-wide ONO dielectrics (Lg ¼ Wgap ¼ 30 nm). Same biases of VGSL ¼ VSSL ¼ become comparable to the length for word-line. That is, the VBL ¼ 1:5 V and Vpass ¼ 6 V are applied for both arrays to device immune from the short channel effect with the 2D perform the read operation. array structure, which the ONO dielectrics are stacked up By increasing the physical gate length through the word- vertically, is highly necessary to increase the bit-density. line extension process, the short channel effect is consid- Therefore, the extended word-line NAND flash memory is a erably suppressed in a two-dimensional (2D) planar-type good option for the extremely scaled NAND flash memory device. Dramatic enhancement of the sub-threshold slope is application. observed in case of the extended word-line NAND flash Moreover, the extended word-line NAND flash memory memory as shown in Fig. 4. Of course, the short channel shows little cell VTH dependency on the gate line edge effect can also be suppressed by increasing the physical gate variation. To simulate this, it is assumed that the maximum length or the gate controllability using three-dimensional variation is Æ5 nm on both edges of the word-line. There- (3D) devices such as the recessed channel array transistor fore, Æ10 nm of the word-line length variation (ÁLedge ) can (RCAT) or FinFET.16,17) However, they need extra areas for be caused for the worst case. The VTH is extracted according ONO dielectrics which consequently result in the reduction to ÁLedge as shown in Fig. 5(a). In the conventional NAND of areal density. Indeed, the thickness of ONO layers is at flash memory, it denotes strong sensitivity on ÁLedge . VTH least 10 to 15 nm and the area consumed by them is doubled variation more than 2 V is observed while only 0.27 V of 081203-2 # 2009 The Japan Society of Applied Physics
  3. 3. Jpn. J. Appl. Phys. 48 (2009) 081203 J.-G. Yun et al. -3 10 Inversion-type S/D -6 10 WL WL WL fringing field -9 Extended WL 10 ID (A/μm) (Lg' = 90 nm) -12 10 Conventional -15 Extended WL NAND 10 with inversion S/D Half pitch = 50 nm -18 Si substrate 10 -1 0 1 2 3 VWL (V) Fig. 6. (Color online) The extended word-line NAND flash memory array with the inversion-type source/drain. The gap between word- lines is controllable through the word-line extension process. Fig. 8. (Color online) ID –VWL characteristics of the conventional and the extended word-line NAND flash memories with the inversion-type source/drain. The improvement of the device performance comes from the increase of the physical channel length as well as the Peak inversion charge (/cm ) 19 3 6x10 Half pitch = 30 nm effective channel length. Vpass = 6 V 19 5x10 Program bit charge (fC/μm) 0.0 -0.5 19 4x10 Conventional -1.0 19 3x10 -1.5 Half pitch = 30 nm 10 15 20 25 30 Vpgm = 15 V -2.0 Gap width (nm) Extended WL -2.5 (Lg' = 50 nm) Fig. 7. Inversion source/drain charge variation as a function of the -13 -10 -7 -4 -1 gap width in the extended word-line NAND flash memory array. 10 10 10 10 10 Programming time (sec) VTH variation is found in case of the extended word-line (a) NAND flash memory. It is because of the strong immunity 4 from the short channel effect which makes the devices have Half pitch = 30 nm tight cell VTH distributions as shown in Figs. 5(b) and 5(c). 3 Conventional VTH shift (V) 3.2 Application of the inversion-type source/drain In addition, the inversion-type source/drain can be applied 2 to the extended word-line NAND flash memory as depicted Extended WL in Fig. 6. Through the word-line extension process, the gap (Lg' = 50 nm) 1 width can be modulated to have high concentration of inversion charges. By decreasing the gap width between word-lines, electric source/drain is formed with more 0 0.2 0.4 0.6 0.8 inversion electrons as shown in Fig. 7. The short channel | Charge loss | (fC/μm) effect is remarkably reduced by increasing the effective (b) channel length in the inversion-type source/drain NAND flash memory. Together with the increased effective channel Fig. 9. (Color online) (a) Comparison of the programmed bit charg- length by forming the inversion-type source/drain, further es between the conventional and the extended word-line NAND flash enhancement of the device performance is achieved through memories having the inversion-type source/drain. About 53% in- the physical gate length extension using the extended word- crease of programmed charges is observed. (b) VTH shift through the charge loss. Great enhancement of the data retention characteristic line NAND flash memory as shown in Fig. 8. Also, larger on can be achieved because of the increased number of programmed current is achieved in the extended word-line type. As the charges. inversion charge increases on the gap, the on current is higher than the conventional one. Transient simulations are carried out to analyze the memory. About 53% increase of programmed charges is program operation characteristics. Program voltage of 15 V achieved in the 30 nm technology node with the extended is applied on the selected word-line. Figure 9(a) shows word-line of 50 nm. Therefore, elevated immunity over the accumulated charges as a function of the programming time. charge fluctuation is expected in the proposed memory By increasing the area of the charge storage node through during the retention mode. Indeed, great improvement of the word-line extension process, much more electrons are retention characteristic is forecasted when the same charge injected in case the extended word-line NAND flash loss with time is supposed for both devices as shown in 081203-3 # 2009 The Japan Society of Applied Physics
  4. 4. Jpn. J. Appl. Phys. 48 (2009) 081203 J.-G. Yun et al. Adjoining bit charge (fC/μm) 8 0.0 Extended WL Conventional 6 (Lg' = 50 nm) Extended WL -4 -1.0x10 VTH shift (V) Vpgm Vpass Conventional 4 -4 -2.0x10 Erased cell 2 Select WL WL Half pitch = 30 nm e 0 Vpgm = 15 V -3.0x10 -4 -11 -9 -7 -5 -3 -1 10 10 10 10 10 10 10 -14 10 -11 10 -8 -5 10 10 -2 Programming time (sec) Programming time (sec) (a) Fig. 10. (Color online) Program speed of the conventional and the extended word-line NAND flash memories having the inversion-type VTH shift by disturbance (V) source/drain. -4 Disturb by Vpass 6.0x10 + E-field from neighboring cell Conventional Extended WL -4 Fig. 9(b). This is especially beneficial for the multi-level cell 4.0x10 VTH shift by disturbance (V) -4 6.0x10 Disturb by V pass Disburb by V pass (MLC) operation.18) Because the level-to-level VTH margin -4 4.0x10 + Neighboring E-field is narrower in the MLC than that in the single-level cell 2.0x10 -4 -4 2.0x10 (SLC), only small charge loss can induce a read error, 0.0 -11 10 10 -9 10 -7 10 -5 10 -3 10 -1 especially for the highest level.19) Programming time (sec) 0.0 Although the difference is small, faster programming speed is observed in the extended word-line NAND flash 10 -11 10 -9 10 -7 -5 10 10 -3 10 -1 memory as shown in Fig. 10. Actually, to induce the VTH Programming time (sec) shift, more charges are required in case of the extended word-line NAND flash memory due to the increased volume (b) of the charge storage node. However, more charges are Fig. 11. (Color online) (a) Neighboring bit charge variation and (b) injected through the extended parts of the charge storage corresponding VTH shift as a function of the programming time. The node and they also contribute to the current flow. That is, the program disturbance is taken place due to the high electric field from channel potential under the extended regions is also changed the selected word-line. by the stored charges and VTH increases that much. VTH shift by interference (V) 3.3 Minor side effects 0.25 Half pitch = 30 nm The influence of the high electric field from the selected 0.20 word-line to adjoining cells is characterized during the program operation. Combined with the high pass voltage 0.15 Extended WL applied on the adjoining transistor, a new kind of program (Lg' = 50 nm) disturbance is observed as shown in Fig. 11. For the worst 0.10 case simulation, the adjoining transistor is assumed to be in 0.05 the erased state (no stored electrons). The disturbance by Conventional Vpass means the conventional program disturbance by the 0.00 pass voltage applied on un-selected transistors.20) In the 0 1 2 3 4 extended word-line NAND flash memory, the high electric VTH shift by programming (V) field from the adjoining selected word-line results in a new kind of disturbance in company with the conventional Fig. 12. (Color online) VTH shift by the cell-to-cell interference when disturbance by Vpass as indicated in the inset of Fig. 11(b). both neighboring cells are in the programmed state. The difference of Although more charges are injected on the neighboring cell VTH shift about 0.1 V is observed in the worst case. in case of the extended word-line NAND flash memory, it 0 still shows an extremely small VTH variation when Wgap is 10 nm. The VTH shift by programming (Fig. 10) and the VTH interference effect is observed in case of the extended word- shift by disturbance (Fig. 11) differs by four orders of line NAND flash memory. However, the difference between magnitude after the program operation for 10 ms. two devices is just around 0.1 V. This can be further reduced On the other hand, because of the reduced space between by adopting low-k spacers or air-gap, although the air-gap adjoining word-lines, the interference becomes higher than cannot be applicable in case of inversion-type source/drain the conventional one.21) The VTH shift by cell-to-cell NAND flash memories.22) As well as the charge trapping interference is calculated with respect to the VTH shift by layers like the nitride in SONOS devices, nano-crystals can programming. To simulate the worst case, it is assumed that also be used as a charge storage node to reduce the both neighboring cells are in the programmed state. As interference.23–25) shown in Fig. 12, the VTH shift by interference goes up as the In practical application, 10 nm of space between word- VTH shift by programming ascends for both devices. More lines can result in high leakage current or breakdown of gap- 081203-4 # 2009 The Japan Society of Applied Physics
  5. 5. Jpn. J. Appl. Phys. 48 (2009) 081203 J.-G. Yun et al. marginal degradation. The extended bit-line can also be used for further increase of the charge storage node and number Nitride hard mask Nitride hard mask of programmed charges. In consequence, high performance and high density NAND flash memory can be fabricated with improved reliability characteristics by increasing the physical word-line length in the extended word-line NAND Si substrate Si substrate flash memory. 1. Hardmask deposition 2. Bit-line patterning & hardmask etch Acknowledgment Oxide spacer etch This work was supported by the Tera-bit Level Nano Device Project. Nitride hard mask 1) K. T. Park, J. Choi, J. Sel, V. Kim, C. Kang, Y. Shin, U. Roh, J. Park, J. S. Lee, J. Sim, S. Jeon, C. Lee, and K. Kim: Tech. Dig. VLSI, 2006, Si substrate Si substrate p. 19. 3. Oxide spacer formation 4. Hardmask and Si etch 2) C. H. Lee, J. Choi, Y. Park, C. Kang, B. I. Choi, H. Kim, H. Oh, and W. S. Lee: Tech. Dig. VLSI, 2008, p. 118. Fig. 13. (Color online) Bit-line extension process for the formation 3) H. T. Lue, E. K. Lai, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, of large charge storage nodes. [ðL0 Wg Þ=ðLg Wg Þ] times increase of the 0 N. Z. Lien, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. g charge storage node area can be achieved by using both word-line Hsieh, R. Liu, and C. Y. Lu: Tech. Dig. VLSI, 2008, p. 140. and bit-line extension processes. 4) K.-T. Park, J.-S. Sel, J. Choi, Y. Song, C. Kim, and K. Kim: IEEE Tran. Electron Devices 55 (2008) 404. 5) A. Asenov, S. Kaya, and A. R. Brown: IEEE Trans. Electron Devices 50 (2003) 1254. fill materials, especially, during the program operation as the 6) S. Xiong, J. Boker, Q. Xiang, P. Fisher, I. Dudley, P. Rao, H. Wang, high program voltage is applied on the selected word-line. and B. En: IEEE Trans. Semicond. Manuf. 17 (2004) 357. To prevent these, optimum designs of the space between the 7) G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov: IEEE Trans. Electron Devices 53 (2006) 3063. word-lines, operating bias conditions, gap-fill materials and 8) J. B. Johnson, T. B. Hook, and Y. M. Lee: IEEE Electron Device Lett. effective thickness/materials of ONO dielectrics should be 29 (2008) 802. made. 9) M. H. Chiang, J. N. Lin, K. Kim, and C. T. Chuang: IEEE Trans. Electron Devices 54 (2007) 2055. 10) H. Furuhashi, T. Shino, T. Ohsawa, F. Matsuoka, T. Higashi, Y. 3.4 Extended bit-line scheme Minami, H. Nakajima, K. Fujita, R. Fukuda, T. Hamamoto, and A. For more increase of the charge storage node size, bit-line Nitayama: Proc. IEEE Int. SOI Conf., 2008, p. 33. extension process can also be done like the extended word- 11) K. Kim and D. Park: Proc. 37th European Solid State Device Research line case as shown in Fig. 13. Using both of the extended Conf., 2007, p. 47. word-line and bit-line processes, the charge storage node 12) J. G. Yun, Y. Kim, I. H. Park, J. H. Lee, S. Kang, D. H. Lee, S. Cho, 0 0 area increases by [ðLg Wg Þ=ðLg Wg Þ] times. For example, if we D. H. Kim, G. S. Lee, W. B. Sim, Y. Son, H. Shin, J. D. Lee, and B. G. Park: Solid-State Electron. 52 (2008) 1498. assume that the oxide spacer width is 10 nm, the area 13) J. G. Yun, I. H. Park, S. Cho, J. H. Lee, D. H. Kim, G. S. Lee, Y. Kim, becomes 2,500 nm2 which is more than 2.7 times increase in J. D. Lee, and B. G. Park: IEEE Trans. Nanotechnol. 8 (2009) 111. the 30 nm technology node. However, in this case, the 14) J. Y. Song, W. Y. Choi, J. P. Kim, S. W. Kim, J. D. Lee, and B. G. interference in the bit-line direction will become stronger. Park: Jpn. J. Appl. Phys. 46 (2007) 2046. 15) Y. K. Lee, J. D. Lee, B. G. Park, S. T. Kang, C. Chung, and D. Park: Hence, it is expected that a compromise needs to be made J. Vac. Sci. Technol. B 22 (2004) 2493. between the increase of charge storage node and the high 16) W. H. Kwon, Y. H. Song, Y. Cai, and S. P. Shim: Jpn. J. Appl. Phys. interference. 47 (2008) 8802. 17) J. D. Choe, S. H. Lee, J. J. Lee, E. S. Cho, Y. Ahn, B. Y. Choi, S. K. 4. Conclusions Sung, J. No, I. Chung, K. Park, and D. Park: Jpn. J. Appl. Phys. 46 (2007) 2197. The word-line extension technology is a simple but effective 18) J. H. Park, S. H. Hur, J. H. Lee, J. T. Park, J. S. Sel, J. W. Kim, S. B. method for highly scaled NAND flash memories in various Song, J. Y. Lee, J. H. Lee, S. J. Son, Y. S. Kim, M. C. Park, S. J. Chai, aspects. By increasing the physical gate length, improve- J. D. Choi, U. I. Chung, J. T. Moon, K. T. Kim, K. Kim, and B. I. Ryu: ment of the short channel effect is achieved in the extended IEDM Tech. Dig., 2004, p. 873. word-line NAND flash memory. High immunity from the 19) E. Kim, K. Kim, D. Son, J. Kim, K. Lee, S. Won, J. Sok, W. S. Hong, line edge variation is observed by increasing the word-line. and K. Park: J. Semicond. Technol. Sci. 8 (2008) 27. 20) I. H. Park, T. H. Kim, S. Cho, J. H. Lee, J. D. Lee, and B. G. Park: Even with the inversion-type source/drain, it shows en- IEEE Trans. Nanotechnol. 5 (2006) 201. hanced device performances by modulating the gap width. 21) M. Park, K. Kim, J. H. Park, and J. H. Choi: IEEE Electron Device Beside the increase of the physical gate length, the extended Lett. 30 (2009) 174. word-line NAND flash memory has an enlarged charge 22) D. W. Kang, S. Jang, K. Lee, J. Kim, H. Kwon, W. Lee, B. G. Park, J. D. Lee, and H. Shin: IEDM Tech. Dig., 2006, p. 11. storage node. Increase of programmed charges in the bit is 23) J. Jung and W. J. Cho: J. Semicond. Technol. Sci. 8 (2008) 32. observed which can improve the data retention character- 24) J. H. Lee: J. Semicond. Technol. Sci. 8 (2008) 11. istic. The program disturbance and the cell-to-cell interfer- 25) J. G. Yun, I. H. Park, S. Cho, J. H. Lee, D. H. Kim, G. S. Lee, Y. Kim, ence are considered as side effects but they just show J. D. Lee, and B. G. Park: J. Korean Phys. Soc. 51 (2007) S229. 081203-5 # 2009 The Japan Society of Applied Physics

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