ENGR / ECE 212 11 & 14 April, 2003 All slides except those with blue backgrounds  are taken from John Wakerly’s Stanford E...
Read-Only Memories <ul><li>Program storage </li></ul><ul><ul><li>Boot ROM for personal computers </li></ul></ul><ul><ul><l...
Two-dimensional decoding
Larger example, 32Kx8 ROM
ROM control and I/O signals
ROM timing
Programmable ROM’s <ul><li>PROM </li></ul><ul><ul><li>Programmable ROM </li></ul></ul><ul><li>EPROM </li></ul><ul><ul><li>...
Read/Write Memories <ul><li>a.k.a. “RAM” (Random Access Memory) </li></ul><ul><li>Volatility </li></ul><ul><ul><li>Most RA...
SRAM
SRAM operation <ul><li>Individual bits are D latches,  not   edge-triggered D flip-flops. </li></ul><ul><ul><li>Fewer tran...
SRAM control lines <ul><li>Chip select </li></ul><ul><li>Output enable </li></ul><ul><li>Write enable </li></ul>
SRAM read timing <ul><li>Similar to ROM read timing </li></ul>
SRAM write timing <ul><li>Address must be stable before and after  write-enable is asserted. </li></ul><ul><li>Data is lat...
Bidirectional data in and out pins <ul><li>Use the same data pins for reads and writes </li></ul><ul><ul><li>Especially co...
Synchronous SRAMs <ul><li>Use latch-type SRAM cells internally </li></ul><ul><li>Put registers in front of address and con...
Some real life examples <ul><li>64-bit (16  4) RAM </li></ul><ul><li>Intel’s specification for 133 Mhz SDRAM </li></ul><u...
Memory today <ul><li>Dell’s “Learn More” </li></ul><ul><li>DDR SDRAM </li></ul><ul><ul><li>Double Data Rate Synchronous DR...
With it in April 2003 <ul><li>Flash for consumer electronics </li></ul><ul><ul><li>Cameras, cell phones, sneaker-net </li>...
How Stuff Works <ul><li>ROM   </li></ul><ul><li>RAM </li></ul><ul><li>Flash memory </li></ul><ul><li>Computer memory </li>...
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ENGR / ECE 212 11

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ENGR / ECE 212 11

  1. 1. ENGR / ECE 212 11 & 14 April, 2003 All slides except those with blue backgrounds are taken from John Wakerly’s Stanford EE 121, Digital Design Laboratory
  2. 2. Read-Only Memories <ul><li>Program storage </li></ul><ul><ul><li>Boot ROM for personal computers </li></ul></ul><ul><ul><li>Complete application storage for embedded systems. </li></ul></ul>
  3. 3. Two-dimensional decoding
  4. 4. Larger example, 32Kx8 ROM
  5. 5. ROM control and I/O signals
  6. 6. ROM timing
  7. 7. Programmable ROM’s <ul><li>PROM </li></ul><ul><ul><li>Programmable ROM </li></ul></ul><ul><li>EPROM </li></ul><ul><ul><li>Erasable PROM </li></ul></ul><ul><ul><li>Erased by exposing to UV light </li></ul></ul><ul><li>EEPROM </li></ul><ul><ul><li>Electrically EPROM </li></ul></ul><ul><ul><li>Data “writes” are slow and limited </li></ul></ul>
  8. 8. Read/Write Memories <ul><li>a.k.a. “RAM” (Random Access Memory) </li></ul><ul><li>Volatility </li></ul><ul><ul><li>Most RAMs lose their memory when power is removed </li></ul></ul><ul><ul><li>NVRAM = RAM + battery </li></ul></ul><ul><ul><li>Or use EEPROM </li></ul></ul><ul><li>SRAM (Static RAM) </li></ul><ul><ul><li>Memory behaves like latches or flip-flops </li></ul></ul><ul><li>DRAM (Dynamic Memory) </li></ul><ul><ul><li>Memory lasts only for a few milliseconds </li></ul></ul><ul><ul><li>Must “refresh” locations by reading or writing </li></ul></ul>
  9. 9. SRAM
  10. 10. SRAM operation <ul><li>Individual bits are D latches, not edge-triggered D flip-flops. </li></ul><ul><ul><li>Fewer transistors per cell. </li></ul></ul><ul><li>Implications for write operations: </li></ul><ul><ul><li>Address must be stable before writing cell. </li></ul></ul><ul><ul><li>Data must be stable before ending a write. </li></ul></ul>
  11. 11. SRAM control lines <ul><li>Chip select </li></ul><ul><li>Output enable </li></ul><ul><li>Write enable </li></ul>
  12. 12. SRAM read timing <ul><li>Similar to ROM read timing </li></ul>
  13. 13. SRAM write timing <ul><li>Address must be stable before and after write-enable is asserted. </li></ul><ul><li>Data is latched on trailing edge of (WE & CS). </li></ul>
  14. 14. Bidirectional data in and out pins <ul><li>Use the same data pins for reads and writes </li></ul><ul><ul><li>Especially common on wide devices </li></ul></ul><ul><ul><li>Makes sense when used with microprocessor buses (also bidirectional) </li></ul></ul>
  15. 15. Synchronous SRAMs <ul><li>Use latch-type SRAM cells internally </li></ul><ul><li>Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds </li></ul><ul><li>E.g., Pentium cache RAMs </li></ul>
  16. 16. Some real life examples <ul><li>64-bit (16  4) RAM </li></ul><ul><li>Intel’s specification for 133 Mhz SDRAM </li></ul><ul><li>IBM SRAM </li></ul><ul><li>64k bit EEPROM </li></ul>
  17. 17. Memory today <ul><li>Dell’s “Learn More” </li></ul><ul><li>DDR SDRAM </li></ul><ul><ul><li>Double Data Rate Synchronous DRAM </li></ul></ul><ul><ul><li>Why PC2100? </li></ul></ul><ul><ul><ul><li>8 bytes x 266M/sec = 2,128MB/sec </li></ul></ul></ul><ul><ul><li>Registered, Buffered, ECC, … </li></ul></ul><ul><li>RDRAM </li></ul><ul><ul><li>Rambus DRAM </li></ul></ul><ul><ul><li>Why 1066 </li></ul></ul><ul><ul><ul><li>Runs at 1066 Mhz </li></ul></ul></ul><ul><ul><ul><li>With 16, 32, or 64 bits per clock cycle </li></ul></ul></ul>
  18. 18. With it in April 2003 <ul><li>Flash for consumer electronics </li></ul><ul><ul><li>Cameras, cell phones, sneaker-net </li></ul></ul><ul><li>Examples include </li></ul><ul><ul><li>Compact Flash </li></ul></ul><ul><ul><ul><li>PCMCIA card format </li></ul></ul></ul><ul><ul><li>SmartMedia </li></ul></ul><ul><ul><ul><li>Once SSFCD (Solid State Floppy Disk Card) </li></ul></ul></ul><ul><ul><li>Memory Stick </li></ul></ul><ul><ul><li>MultiMediaCard </li></ul></ul><ul><ul><li>Secure Digital Card </li></ul></ul><ul><ul><li>XD Picture Card </li></ul></ul><ul><ul><ul><li>Olympus and Fuji </li></ul></ul></ul>
  19. 19. How Stuff Works <ul><li>ROM </li></ul><ul><li>RAM </li></ul><ul><li>Flash memory </li></ul><ul><li>Computer memory </li></ul>

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