Data Sheet

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Data Sheet

  1. 1. W O O 0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 10 W O W O Y.C O W WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T W O W O 0Y .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW 0 O W.1 Y.COM W FINAL W O W WW .100Y.C M.TW 00 .T WW .100Y.C M.TW W.1 Y.COM W W O W O WW .100Y.C M.TW WW .100Y.C M.TW .10 0 WW 00Y.CO .TW Am28F010 M .T W WW .100Y.C M.TW O W WW .100Y.C M.TW O W.1 OM 1 Megabit (128 K x 8-Bit) 0Y.CO W W O WW .100Y.C M.TW WW .10 .TW WW .100Y.C M.TW W OM W O W CMOS 12.0 Volt, Bulk Erase0Flash Memory WW .100Y.C M.TW O WW .10 Y.C M.TW WW .100Y.C M.TW W O W O WW DISTINCTIVEW Y.C O WW .100Y.C M.TW WW .100Y.C M.TW W .100 OM .T CHARACTERISTICS W O W O W WW s00Y.Cperformance High TW s WW .100Y.C M.TW WW .100Y.C M.TW Flasherase™ Electrical Bulk Chip-Erase .1 M. W O W O W WW 00Y.COmaximum access time W — 70 ns W W 0 WW .1 0Y.C 0Y.C M.TW— One second typical0chip-eraseM.TW .1 M.T W.1 Y.CO WW 00Y O .TW Programming .C W WW CMOSCO power consumptionW s 0Y . Low .TW W 00 .s W T Flashrite™W 1 10 mA maximum active current W.1 W.— 30Y.COM W OM — 10 µs typical WW. OM WW — 00 µA maximum standby current W Y.C W W byte-program.C M.TW 0Y W.1 100 Y.COM W .T W .100 M.T— Two seconds typical.10 program W chip O WW 00Y.CO .TW WW .100Y.C M.TW WW — .100 retention power consumption .1 No data .T W M M W Os Command register architectureCO W for WW 00Y.CO JEDEC-standard byte-wide 00Y.C Ws Compatible withM.TW WW .1 .TW WW .100Y. microprocessor/microcontroller compatible M.T W W .1 O W OM write interface WW W Y.CO WW .1EPROM pinoutsW 32-Pin Y.C 00PDIP M.T WW .100Y.C M.TW 100 .TW W O On-chip address andWW.latches.COM W W 32-pin 0Y.CO —W W— 32-pin0PLCC M.TW WW .100Y.C M.TW s W data .100Y M.T W . 1 O W sO Advanced CMOS flashWW .CO .T WW .100Y.C — M.Tcost single transistor memory cell M memory technology W WW .1TSOPC M.TW — 32-pin 00Y . W W 00Y O Low W.1 Y.CO W O WW 00Y.C WW .TW WW .100Y.C M. minimum W s 10,000 write/erase cyclesTW W .1 s Automatic write/erase pulseW.10 timerCOM M.T stop 0 W O W s Write and eraseY.C WW .100 voltageM.TW ±5% O 12.0 V WW .100Y.C M.TW WW .100Y. M.T W s Latch-upW O W O W WW .100Y. CO WW protected.C 100 mAW Y to WW .100Y.C M.TW .TW 100 .V CC +1 V OM.T W O W OM WW .100Y.C M.TW from –1 V W to WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW .100Y.C M.TW O WW .100Y.C M.TW WW .100Y.C M.TW GENERAL DESCRIPTION W O W O W WWis a .100Y.C Flash W O Tmemory orga- WW .100Y.C M.TW WW .100Y.C M.TW The Am28F010 Megabit M. WAMD’s Flash O technology reliably stores W memory con-O WW 0 8 bitsO . AMD’s FlashWW tents1even .after 10,000 erase and program cycles.Y.C M.TW nized as 128 Kbytes of 0Y.C each.TW W 0 0Y C M.TW WW .100 The memories offer theW. 1 cost-effective and M W. CO W AMD cell is .designed to optimize the erase and 0Y.C O W W most 00Y.CO .TW reliable WW 00Y WW .10 pro- .TW addition, the combination of OM.TW .1 read/write non-volatile random access memory. The M W.1 M gramming mechanisms. In CO W WW 00Y.CO Am28F010 is packaged in 32-pin PDIP,.TW W PLCC, and WW advanced 0Y. 0 .TW WW .100Y.C M.TW tunnel oxide processing and low internal .1 TSOP versions. It is designed to COM W.1 for O M programmingWW O WW in 00Y. be reprogrammed WW fieldsY.Cerase .and The Am28F010 uses00Y.C M.T W or .1 standard EPROM .T W pro- electric 00 TW W operations .1 a and erased in-system M W.1 produces reliable OM cycling. WW 0 .CO WW 00Y.CO . shipped grammers. The Am28F010 is erased when TW 12.0 V ± 5% 00Y.C WW .1 V PP high M.TW input to W voltage perform the 0Y W .1 M W.1 OM from the factory. WW 00Y.CO .TW WW 00Y.CO .TW Flasherase and Flashrite algorithms. W WW .100Y.C W The standard Am28F010 offers 1 OM . access times as fast as The highest 1 W. degree ofOM W latch-up protection is achieved W WW 00Y.Cmicroproces- W WW .100Y.C M.TW WW 70 ns, allowing operation of high-speed .1 sors without wait states. To eliminate Y.CO M.T with AMD’s proprietary non-epi process. Latch-up pro- W O WW 00 bus contention, W chip enable (CE#).TW tection is provided0Y.C WW .10 for stresses.TW 100 milliamps on up to the Am28F010 has separate W.1 O M and address andW pins from M V to V CC +1 V. data O –1 output enable (OE#) controls. WW .100Y.C WW .100Y.C M.TW The Am28F010 is byte programmable using 10 ms pro- W O W AMD’s Flash memories augment EPROMY.C WW WW .100 functionality W gramming pulses in accordance with AMD’s Flashrite .T with in-circuit electrical erasure WW and programming.M O Am28F010 uses a command register.100 W Y.C The W programming algorithm. The typical room temperature to manage this.T programming time of the Am28F010 is two seconds. M W WW 00Y.CO functionality, while maintaining a JEDEC Flash Stan- The entire chip is bulk erased using 10 ms erase pulses W.1 dard 32-pin pinout. The command register allows for according to AMD’s Flasherase alrogithm. Typical era- WW 100% TTL level control inputs and fixed power supply sure at room temperature is accomplished in less than levels during erase and programming, while maintain- one second. The windowed package and the 15–20 ing maximum EPROM compatibility. Publication# 11559 Rev: I Amendment/0 Issue Date: May 12, 1999
  2. 2. W O O 0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 10 W O W O Y.C O W WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T . O W O 0Y .COminutes required forWWW erasureC .TW EPROM .100Y usingM.T W ultra-violet WW . 00Y.C M TW ing edge of1WE# or CE# .whichever occurs first. To 0 O W.1 Y.COM are eliminated. W O W WW .100Y.C M.TW 00 light .T W WW .100Y.C M.TW simplify the following discussion, the WE# pin is used W.1 Y.COM W written to WW O O as the WW cycle control pin throughout the rest of write Commands are W the command.C Musing register Y.C .TW .10 0 standardTmicroprocessor write timings. Register.TW M . .100Y con- W .100 this W All setup and hold times are with respect to text. OM W O .C .CO .T as WW 00Ytents serveW inputs to an internal0state-machine WW .10 Y.C M.TW the WE# signal.100Y WW . .TW W .1 O M W O which controls the erase and programming circuitry.W AMD’s WW technology W . OM CcombinesW WW .100Y.C write W WW Y.C Flash 00Y to produceyears of EPROM .T 100 During M.T cycles, the command .register internally M.T and EEPROM W.1 experience COM W CO Oaddress and data neededW the programming W of quality, W . cost effectiveness.levels W reliability,0and M.TW the highest WW .100Y.C M.TW latches WW for .100Y. M .T . 10 Y The WW 0 erases O W and erase operations. For systemW CO .CO W design0simplifica- .TWAm28F010 electrically 0Y.C all bits W simultaneously WW .1tion, .the Am28F010 is designed to support either WE# 00Y .TW W 0 Y W .1 OM .T W or CE#COM W W W.1 write.COM W Fowler-Nordheimatunneling. The bytes are pro- using . controlled writes. During a system 00Y cycle, .T grammed one byte .1 time WWat 00Y.Cusing theW pro- W Y W W .T EPROM W 100 .T .1 W.addressesOM latched on the falling edge of0WE#OM gramming mechanism of 00Y.CO injection. WW hot electron .TW M WW CE# 0Y .C are occurs last. Data isWW on Y.Cris- .TW or W 0 whichever .TW W latched10 the W. M W.1 OM W W.1 Y.COM W W Y .CO .TW WW .100Y.C M.TW W 00 W.1 Y.COM W .T W .100 M W O WBLOCK DIAGRAM W WW 00Y.CO .TW WW .100Y.C M.TW W .100 M.T W.1 OM W O W WW 00Y.CO .TW WW .100Y.C M.TW WW DQ0–DQ7C M.TW .100 Y. W.1 VCC OM W O W O WW .100Y.SS M.TW C WW .100Y.C M.TW WW .100Y.C M.TW V W O W O W WW 00Y.CO .TW WW .1Erase.C M.TW 0 0Y Voltage WW .100Y.C M.TW Input/Output .1 VPP M W O WW 00Y.CO .TW W WW 0SwitchO .TW 0 Y.C WWBuffers 00Y.C M.TW 1 W W. .1 M W.1 OM O W WW 00Y.CO .TW WW .100Y.C Array.TW To WW .100Y.C M.TW W.1 # OM State W OM W O WW .100Y.C Control WE TW WW .100Y.C M.TW WW .100Y.C M.TW M. W O W O W WW 00Y.CO .TW Command WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O Register Program W WW .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW Voltage Switch .100Y W OM Data W O WW 00Y.CO .TW WW .100Y.C M.TW Chip Enable W CE# 0Y.C M WW .10Output Enable.TW Latch .1 OM W O W O OE#W WW .100Y.C M.TW WW .100Y.C M.TW Logic WW .100Y.C M.TW W O W O W WW .100Y.C M.TW O WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.CO .TW WW .100Y.C M.TW Y-Gating Y-Decoder WW .100Y.C M.TW .1 M W O WW 00Y.CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW W .1 OM Program/Erase W.1 OM W O WW .100Y.C M.TW Address Latch Low V CC W W Y.C TimerW Pulse WW .100Y.C M.TW W Detector .100 M.T W O WW 00Y.CO .T W WW 00Y.CO .TW WW X-Decoder.C M.T1,048,576 Bit W 00Y W .1 M W.1 Y.COM W .1 Cell Matrix WW 00Y.CO WW 00Y.CO .TW W A0–A16 WW .100 .T W .1 M W.1 OM W OM WW 00Y.CO .TW WW .100Y.C W Y.C W W W .100 M.T W.1 OM W W WW 00Y.CO .TW WW .100Y.C M.TW WW W.1 OM W O 11559I-1 WW .100Y.C M.TW WW .100Y.C M.TW W O W O WW .100Y.C M.TW WW .100Y.C PRODUCT SELECTOR GUIDE W O W WW .100Y.C M.TW WW Family Part Number W O Am28F010 WW .100Y.C M.TW Speed Options (VCC = 5.0 V ± 10%) W O -70 -90 -120 -150 -200 WW .100Y.C Max Access Time (ns) W 70 90 120 150 200 WW CE# (E#) Access (ns) 70 90 120 150 200 OE# (G#) Access (ns) 35 35 50 55 55 2 Am28F010
  3. 3. W O O 0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 10 W O W O Y.C O W WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T W O W O 0Y .COCONNECTION DIAGRAMS0Y.C .TW WW .10 .TW WW .100Y.C M.TW 0 OM O W.1 Y.COM W W W WW .100Y.C M.TW 00 .T WW .100Y.C M.TW W.1 Y.COM W W O W O 0 .T WW .100Y.C M.TW PDIP WW .100Y.C M.TWPLCC .10 M W O W O WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW WE# (W#) W.1 OM VPP 1 W VCC O W O WW .100Y.C M.TW WW 32 .100Y.C M.TW WW .100Y.C M.TW A16 VCC A12 A15 VPP O NC W WE# (W#) O W W O WW .100Y.C M.TW 2 31 WW .100Y.C M.TW A16 WW .100Y.C M.TW 3 4 3 2 1 32O 30 W A15 30 W NC O WW .100Y.C M.TW 31 W WW 00Y.CO .A12 4 T W WW A14 0Y.C M.TW 10 .1 M 29 . A7 5 W O 29 A14 WW 00Y.CO A7 W 5 W WW 00Y.CO .TW A6 6WW 10 0Y.C M28 W .T A13 W .T W.1 Y.COM W A5 7 WW. 0Y.CO 28 A13 W .1 OMA6 6 WW .100Y.C M.TW 27 W A8 W 00 .T W 0 27.TWA8 W O A5 7 W.1 Y.COM W A4 8 W W.1 Y.COM A9 WW .100Y.C M.TW 26 W W A9 .100 M.T A3 9 W 00 26 .TW OA4 8 W O W.1 Y.COM A1125 W WW .100Y.C A3M.TW 25 WW .100Y.C M.TW A11 WW .100 .TW 9 24 OE#W O A2 10 W OM C24 OE# W (G#) WW .100Y. 23 M.T (G#) W WW 00Y.CO .TW WW .100Y.C M.TW 11 A1 A10 W.1 A2 M 10 23 A10 W W O O W .CO .TW 12 WW .100Y.C CE#TW WW .100Y.C M.TW 22 W (E#) .100Y A0 22 (E#) A1 11 CE# W OMDQ0 13 W M. 21 ODQ7 W W .CO WW .1 .C WW .100YA0 12 .TW 21 DQ7 WW .100Y.C M.TW 14 15 16 17 18 19 00Y .T W O13M W C O W W 20 Y.COM W WW .100Y.C M.TW 20 DQ6 DQ0 WW .100Y. .TW W 00 .T OM W.1 Y.COM W VSS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 O W W DQ1 14 WW .100Y.C M.TW 19 DQ5 WW .100Y.C M.TW WW .100 M.T W DQ2 O 15 18 DQ4 W W .CO WW 00Y.CO .TW WW .VSS Y.C M.TW DQ3 W 100 16 O 00Y .TW W .1 M W .C 17 W W.1 Y.COM W WW 00Y.CO .TW WW .100Y .TW W OM W .100 M.T W.1 OM W W Y .C W W WW 00Y.CO .TW WW .100Y.C M.TW W .100 M.T W.1 OM W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O 11559I-2W Y.C Y.C WW .10011559I-3 M.TW WW .100Y.C M.TW W 100 .TW W. OM W O W WW .100Y.C M.TW O Note: Pin 1 is marked for orientation. WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.T W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C W O W W WW 00Y.CO .TW WW .100Y.C M.TW WW W.1 OM W O WW .100Y.C M.TW WW .100Y.C M.TW W O W O WW .100Y.C M.TW WW .100Y.C W O W WW .100Y.C M.TW WW W O WW .100Y.C M.TW W O WW .100Y.C W WW Am28F010 3
  4. 4. W O O 0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 10 W O W O Y.C O W WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T W O W O 0Y .COCONNECTION DIAGRAMS0(continued) .TW WW .10 Y.C M.TW WW .100Y.C M.TW 0 W.1 Y.COM W W O WW 00Y.CO .TW WW .100Y.C M.TW TSOP W 00 W.1 Y.COM W A11 .T 1WW O W.1 OM OE W 0 0Y.C M.TW WW .100Y.C 32 M.TW# .100 M.T A9 2 W.1 Y.CO W O 31 A10 WW 00Y.CO .TW A8 WW 3 00 .TW WW .100Y.C30 M.CE# TW .1 M A13 4 W.1 Y.COM W W CO D7 W 29 W O WW .100Y.C M.TW A14 5WW WW .100Y. 28 M.T .100 M.T D6 W O NC 6 W W .CO WW 00Y.CO D5 .TW 27 WW .100Y.C M.TW # WE 7 W 00Y .TW W .1 26 M D4 W CO VCC 8 W W.1 Y.COM W WW 0025.COD3 .TW Y W Y. W W 0 .T W W .100 M.T A16 NC 9 0 W.1 Y.COM W W.1 24 OSS VM WW 00Y.CO .TW 10 WW WW .1023Y.C D2 M.TW 0 W W.1 Y.COM A12 A15 11 .100 M.T W 22 O D1 W W 12 W WW 00Y.CO .TW WW .100Y.C M.TW 21 D0 W .100 M.T A7 13 .1 WW 00Y.CO .TW M W 20 A0O C W WW 00Y.CO A6 W 14 .T 15 W WW 1900Y.A1 M.TW .1 .1 OMA5 W .1 O M W18 Y.CO A2 W WW .100Y.C M.TW16 A4 WW .100Y.C M.TW WW 17 100 A3 . M.T W W O W O W WW .100Y. CO WW .100Y.C M.TW W32-Pin .100Y.C M.TW W TSOP—Standard Pinout .TW W O W OM W WW .100Y.C M.TW O WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.OE# .1 WCO T WW .100Y.C M.TW WW .100Y.C M.TW 32 A11 .1 A10 M 2 W O 31 W A9 O W WW 00Y.CO 3.TW CE# WW .100Y.C M.TW WW A8 00Y.C M.TW 30 . 1 .1 M W O 29 W O WW 00Y.CO 4 .TW D7 WW .100Y.C M.TW WW A13 00Y.C M.TW W .1 D6 5 M 28 W.1 Y.CO A14 WW 00Y.CO6 .TW D5 W WW 00Y.CO .TW 27 W NC W 00 .TW W 1 D4 OM 7 .1 M 26 WE# 1 W. OM W. D3 W O 25 WW CC Y.C WW .1VSSY.C 8 M.TW 00 WW .100Y.C M.TW V .100 M.T W W D2 9 O W O 24 NCW W .CO WW .100Y.C M.TW 10 WW .100Y.C M.TW 23 WA16 00Y .TW W D1 11 O W O 22 A15W W.1 Y.COM W WW D000Y.12 M.TW C WW .100Y.C M.TW 21 W 00 .T W .1 13 O W O A12 A7 W W.1 Y.COM W WW .100Y.C M.TW 19 A0 20 WW A1100Y.C M.TW14 W A6 .100 M.T W . O W CO WW 00Y.CO .TW WW .100Y. A2 WW A3 .100Y.C M.TW 18 .TW 17 15 A5 W OM .1 M WW 00Y.CO .TW 16 A4 W CO W W .C W Y. W W 32-Pin TSOP—Reverse .10 0Y M. TW W 1 W .100 M.T Pinout WW 00Y.CO .TW W.11559I-4 OM W WW 00Y.CO .TW W WW .100Y.C M.TW W.1 Y.COM W W.1 OM W O W WW .100Y.C M.TW WW .100Y.C M.TW W .100 M.T W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.T LOGIC SYMBOL W.1 OM W O W O W Y.C W WW .100Y.C M.TW WW .100Y.C M W .100 M.T W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C .1 M W O W W WW 00Y.CO .TW 17 WW .100Y.C M.TW WW W.1 OM W O WW .100Y.C A0–A16 .TW WW 8100Y.C M.TW W OM W. O WW .100Y.C M.TW DQ0–DQ7 WW .100Y.C W O W WW .100Y.C CE# (E#)W .T WW W OM WW .100Y.C (G#)TW OE# M. W WW 00Y.CO (W#)WE# W.1 WW 11559I-5 4 Am28F010
  5. 5. W O O 0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 10 W O W O Y.C O W WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T W O W O 0Y .COORDERING INFORMATION Y.C .TW WW .100 .TW WW .100Y.C M.TW 0 OM O W.1 Y.COM W W W WW .100Y.C M.TW 00 .T Standard Products WW .100Y.C M.TW W.1 Y.COM W WW O WW W .CO .T and Y.C W .10 0 AMD standard products are available.in00Y packages W operating W W.100 numberM.T Combination) is formed M.T 1 several M ranges. The order O (Valid W O .CO .TW WW 00Yby a combination of: WW .100Y.C M.TW WW .100Y.C M.TW W.1 M JW O W O WW .100Y.C M.TW OAM28F010 -70 WW .100Y.C M.TW C B WW .100Y.C M.TW W O W O OPTIONAL W W PROCESSING.C O WW .100Y.C M.TW WW .100Y.C M.TW Blank = W 100 Y Standard Processing OM .TW O W O W. .C W WW .100Y.C M.TW WW .100Y.C M.TW B WW .100Y = Burn-In .TW W O W OM W WW .100Y.C M.TW O WW .100Y.C M.TW WW .100Y.C M TW Contact an AMD representative for more .information. W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW .1 M TEMPERATURE RANGE W O WW 00Y.CO .TW W WW 00Y.CO .TWCommercial (0°C to +70°C)Y.C C= WW .100 .TW W .1 M .1 M I = Industrial (–40°C toW OM W O WW .100 .C W O +85°C) WW .100Y.C M.TW WW .100Y.C METW . = Extended (–55°C to +125°C) Y OM.TW W O W O WW 00Y.C WW .100Y.C M.TW WW .100Y.C M.TW TYPE W .TW O W O PACKAGE W.1 Y.COM W W WW .100Y.C M.TW WW .100Y.C P =.TW Plastic DIP (PD 032)100 WW T M 32-Pin Rectangular Plastic .Leaded Chip M. 32-Pin W O W OJ = W W Y.CO WW .100Y.C M.TW WW .100Y.C M.TW (PL 032) W 100 .TW O W O= 32-Pin Thin Small Outline W. Carrier .C OM W WW .100Y.C M.TW WW .100Y.C M.TW Pinout (TS 032) .100Y E WW Package (TSOP) M.TW W O Standard W O WW 00Y.CO .TW WW .1 0Y.C WW .100Y.C = 32-Pin W Small Outline Package0(TSOP) M.TW F T Thin W .1 M M. Reverse Pinout (TSR032) W O WW 00Y.CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW W .1 M W.1 SPEEDM O W O W WW 00Y.CO .TW Y.C OPTION WW .100Y.C WW .100See Product.TW Guide and Valid Combinations M.TW .1 M M Selector W O WW 00Y.CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW W .1 M W.1 OM W O W WW 00Y.CO .NUMBER/DESCRIPTION 100Y.C DEVICE TW WW . .TW WW .100Y.C M.TW .1 M W OM W O W .CO .TW WW 00YAm28F010(128 K x 8-Bit) CMOS Flash 100Y.C 1 Megabit WW . Memory .TW WW .100Y.C M.TW W.1 OM W OM W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW WW 00Y.CO .TW W O WW 00Y.CO .TW WW .100Y.C Valid .Combinations W TW W Combinations M Valid W.1 M W.1 OM W .CO .TW WW 00Y.CO .TW WW . sup- .C M.T Valid Combinations list configurations planned to be 100Y W 00Y W portedW. 1 in volume for thisM O device. Consult the localWWsales .CO AM28F010-70 W.1 Y.COM W AMD W W 00 PC, PI, M.T WW .100Y.C M specific valid combinations and 0Y office to confirm availability of.T W W .10 M AM28F010-90 W W.1 Y.CO PE, W to checkW newly Y.CO combinations. W on 00 released .TW W WW 00Y.CO W W .100 EC, EI, EE, .T JC, JI, JE, M .1 M W.1 WW 00Y.CO .TW AM28F010-120 W WW 00Y.CO .TW W WW AM28F010-150 W.1 Y.COM W FC, FI, FE W.1 OM W WW .100Y.C M.TW AM28F010-200 W .100 M.T W O W WW 00Y.CO .TW WW .100Y.C W. 1 OM W WW .100Y.C M.TW WW W O WW .100Y.C M.TW W O WW .100Y.C W WW Am28F010 5
  6. 6. W O O 0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 10 W O W O Y.C O W WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T O W O 0Y .COPIN .DESCRIPTION W 00Y.C TW WW .1 .TW WW VCC W.10 0Y.C M.TW 0 OM O W.1 Y.COM W W Y.C WW . for device operation. (5.0 V ± 5% or 10%) WW .100Y.C M.TW Power supply100 M.T W W .100 O M.T A0–A16 W O W W .CO Y.C ddressTW for memory locations.Y.C M.TW A WW 0 Internal latches VPPW 00Y .TW .100 hold addresses during writeWW.10 M. Inputs O W.1 Y.COM W WW 00Y.CO .TW WW . 00 W cycles.100Y.C M.TW Program voltage1input. VPP must be at high voltage in M.T W .1 O M) W . O W .CO W the command register. The command WW .100Y.C M.TW registerW 00Y .TW CE# (E# order to write to WW .100Y.C M.TW W.1 Y.C requiredW alter the mem- controls all functionsOM to W CO W O W WW .1 high.C M. Chip Enable active low input activates the chip’s con- WW .100Y.logic and.TW buffers. Chip Enable 00Y will dese-TW ory arrayW W.Memory contents cannot be altered trol M input contents. 100 OM .T W O ≤ VCC WW lectY.CO .TWoperates the chip in stand-by mode. .TWwhen VPP WW +2 .V.00Y.C M.TW the device and WW .100Y.C M W .100 M W1 O WW DQ0–DQ7 .TW .CO WW 00Y.CO .TWSS V WW .100Y.C M.TW W 0Y W .10 M W.1 OM Ground W O W WW Data0Y.CO during memory write cycles. 0Y.C Inputs W WW .10 Internal M.TW WW .100Y.C M.TW .10 M.T latches hold data during write cycles. W O W O WW .100Y.C M.TW Data Outputs WE # (W#) WW 00Y.CO read cycles. W during memory M.TW WW .100Y.C M.TW W.1 W O O Write Enable active WW controls the write function WNC 00Y.CO .TW WW .100Y.C M.TWcommand W low input Y.C array. W register to100 memoryM.T The tar- W of the W. the W .1 O M W Y.C WW .100Y. CO O get address is latched on the falling edge of the Write Y.C WW Connect-corresponding pin isW connected W W W .TW No W .100 the die. .T O M not W .100 OM.T W OM Enable pulse and the appropriate data is latched on the W .C internally to WW .100Y.C M.TW WW .100Y.C rising edge of the W Write 0Y W highT M.T to the device. WW.10 EnableOM. inhibits pulse. W OE #W #) O W O .C (G WW .100Y.C M.TW .TW writing WW .100Y.C M.TW W 00Y W O W.1 Y.COM W W WW .100 the M.TW .CO WW .10 Y.C M.TW Output Enable active low input gates the outputs of the WW .100 M.T device throughY data buffers during memory read 0 cycles.W O is high during command Y.CO W W WW .100Y .CO .TW WW Output Y.C M.TW Enable WW .100 .TW 100 sequencing .and program/erase operations. OM W OM WW 00Y.CO .TW W WW 00Y.C W WW .100Y.C M.TW W W.1 Y.COM W .1 M.T W O W W WW 00Y.CO .TW WW .100Y.C M.TW W .100 M.T .1 WW 00Y.CO .TW M W O W WW 00Y.CO .TW W WW .100Y.C M.TW .1 M W.1 OM W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW .100Y.C M.TW O WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.T W O W O W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M W.1 OM W O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C W O W W WW 00Y.CO .TW WW .100Y.C M.TW WW W.1 OM W O WW .100Y.C M.TW WW .100Y.C M.TW W O W O WW .100Y.C M.TW WW .100Y.C W O W WW .100Y.C M.TW WW W O WW .100Y.C M.TW W O WW .100Y.C W WW 6 Am28F010

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