Virtual Memory Operating Systems  Fall 2002
Paging and Virtual Memory <ul><li>Paging makes virtual memory possible </li></ul><ul><ul><li>Logical to physical address m...
How does this work? <ul><li>CPU can execute a process as long as some portion of its address space is mapped onto the phys...
Benefits <ul><li>More processes may be maintained in the main memory </li></ul><ul><ul><li>Better system utilization </li>...
Why is this practical? <ul><li>Observation: Program branching and data access patterns are not random </li></ul><ul><li>Pr...
Virtual memory implementation <ul><li>Efficient run-time address translation </li></ul><ul><ul><li>Hardware support, contr...
Thrashing <ul><li>A condition when the system is engaged in moving pages back and forth between memory and disk most of th...
Address translation <ul><li>Virtual address is divided into page number and offset </li></ul><ul><li>Process page table ma...
Forward-mapped page tables (FMPT) <ul><li>Page table entry (PTE) structure </li></ul><ul><li>Page table is an array of the...
Address Translation using FMPT Program Paging Main Memory Virtual address Register Page Table Page Frame Offset P# Frame #...
Handling large address spaces <ul><li>One level FMPT is not suitable for large virtual address spaces </li></ul><ul><ul><l...
Multilevel FMPT <ul><li>Use bits of the virtual address to index a  hierarchy  of page tables </li></ul><ul><li>The leaf i...
Two-level FMPT page number page offset p i p 2 d 10 10 12
Two-level FMPT
Inverted page table (IPT) <ul><li>A single table with one entry per  physical page </li></ul><ul><li>Each entry contains t...
Address translation with IPT <ul><li>Virtual address is first indexed into the  hash anchor table  (HAT) </li></ul><ul><li...
Address translation with IPT Virtual address page number offset hash + HAT base register ASID register page number ASID Fr...
Translation Lookaside Buffer (TLB) <ul><li>With VM accessing a memory location involves at least two intermediate memory a...
TLB internals <ul><li>TLB is associative, high speed memory </li></ul><ul><ul><li>Each entry is a pair (tag,value) </li></...
Address translation with TLB
Bits in the PTE: Present (valid) <ul><li>Present (valid) bit </li></ul><ul><ul><li>Indicates whether the page is assigned ...
Bits in PTE: modified, used <ul><li>Modified (dirty) bit </li></ul><ul><ul><li>Indicates whether the page has been modifie...
Bits in PTE <ul><li>Access permissions bit </li></ul><ul><ul><li>indicates whether the page is read-only or read-write </l...
Protection with VM <ul><li>Preventing processes from accessing other process pages </li></ul><ul><li>Simple with FMPT </li...
Segmentation with paging <ul><li>Segmentation  </li></ul><ul><ul><li>simplifies protection and sharing, enforce modularity...
Address translation Main Memory Page Frame Offset Paging Page Table P# + Frame # Offset Seg Table Ptr + S # Segmentation P...
Page size considerations <ul><li>Small page size  </li></ul><ul><ul><li>better approximates locality </li></ul></ul><ul><u...
Next : Page replacement
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  1. 1. Virtual Memory Operating Systems Fall 2002
  2. 2. Paging and Virtual Memory <ul><li>Paging makes virtual memory possible </li></ul><ul><ul><li>Logical to physical address mapping is dynamic </li></ul></ul><ul><ul><li>Processes can be broken to a number of pages that need not be mapped into a contiguous region of the main memory </li></ul></ul><ul><li>=> It is not necessary that all of the process pages be in main memory during execution </li></ul>
  3. 3. How does this work? <ul><li>CPU can execute a process as long as some portion of its address space is mapped onto the physical memory </li></ul><ul><ul><li>E.g., next instruction and data addresses are mapped </li></ul></ul><ul><li>Once a reference to an unmapped page is generated ( page fault ): </li></ul><ul><ul><li>Put the process into blocking state </li></ul></ul><ul><ul><li>Read the page from disk into the memory </li></ul></ul><ul><ul><li>Resume the process </li></ul></ul>
  4. 4. Benefits <ul><li>More processes may be maintained in the main memory </li></ul><ul><ul><li>Better system utilization </li></ul></ul><ul><li>The process size is not restricted by the physical memory size: the process memory is virtual </li></ul><ul><ul><li>But what is the limit anyway? </li></ul></ul>
  5. 5. Why is this practical? <ul><li>Observation: Program branching and data access patterns are not random </li></ul><ul><li>Principle of locality: program and data references tend to cluster </li></ul><ul><li>=> Only a fraction of the process virtual address space need to be resident to allow the process to execute for sufficiently long </li></ul>
  6. 6. Virtual memory implementation <ul><li>Efficient run-time address translation </li></ul><ul><ul><li>Hardware support, control data structures </li></ul></ul><ul><li>Fetch policy </li></ul><ul><ul><li>Demand paging: page is brought into the memory only when page-fault occurs </li></ul></ul><ul><ul><li>Pre-paging: pages are brought in advance </li></ul></ul><ul><li>Page replacement policy </li></ul><ul><ul><li>Which page to evict when a page fault occurs? </li></ul></ul>
  7. 7. Thrashing <ul><li>A condition when the system is engaged in moving pages back and forth between memory and disk most of the time </li></ul><ul><li>Bad page replacement policy may result in thrashing </li></ul><ul><li>Programs with non-local behavior </li></ul>
  8. 8. Address translation <ul><li>Virtual address is divided into page number and offset </li></ul><ul><li>Process page table maintains mappings of virtual pages onto physical frames </li></ul><ul><ul><li>Each process has its own unique page table </li></ul></ul>Virtual Address Page Number Offset
  9. 9. Forward-mapped page tables (FMPT) <ul><li>Page table entry (PTE) structure </li></ul><ul><li>Page table is an array of the above </li></ul><ul><ul><li>Index is the virtual page number </li></ul></ul>P M Frame Number Other Control Bits Page Table Frame # Page # P: present bit M: modified bit
  10. 10. Address Translation using FMPT Program Paging Main Memory Virtual address Register Page Table Page Frame Offset P# Frame # Page Table Ptr Page # Offset Frame # Offset +
  11. 11. Handling large address spaces <ul><li>One level FMPT is not suitable for large virtual address spaces </li></ul><ul><ul><li>32 bit addresses, 4K (2 12 ) page size, 2 32 / 2 12 = 2 20 entries ~4 bytes each => </li></ul></ul><ul><ul><li>4Mbytes resident page table per process! </li></ul></ul><ul><ul><li>What about 64 bit architectures?? </li></ul></ul><ul><li>Solutions: </li></ul><ul><ul><li>multi-level FMPT </li></ul></ul><ul><ul><li>Inverted page tables (IPT) </li></ul></ul>
  12. 12. Multilevel FMPT <ul><li>Use bits of the virtual address to index a hierarchy of page tables </li></ul><ul><li>The leaf is a regular PTE </li></ul><ul><li>Only the root is required to stay resident in main memory </li></ul><ul><ul><li>Other portions of the hierarchy are subject to paging as regular process pages </li></ul></ul>
  13. 13. Two-level FMPT page number page offset p i p 2 d 10 10 12
  14. 14. Two-level FMPT
  15. 15. Inverted page table (IPT) <ul><li>A single table with one entry per physical page </li></ul><ul><li>Each entry contains the virtual address currently mapped to a physical page (plus control bits) </li></ul><ul><li>Different processes may reference the same virtual address values </li></ul><ul><ul><li>Address space identifier (ASID) uniquely identifies the process address space </li></ul></ul>
  16. 16. Address translation with IPT <ul><li>Virtual address is first indexed into the hash anchor table (HAT) </li></ul><ul><li>The HAT provides a pointer to a linked list of potential page table entries </li></ul><ul><li>The list is searched sequentially for the virtual address (and ASID) match </li></ul><ul><li>If no match is found -> page fault </li></ul>
  17. 17. Address translation with IPT Virtual address page number offset hash + HAT base register ASID register page number ASID Frame# IPT + IPT base register frame number HAT
  18. 18. Translation Lookaside Buffer (TLB) <ul><li>With VM accessing a memory location involves at least two intermediate memory accesses </li></ul><ul><ul><li>Page table access + memory access </li></ul></ul><ul><li>TLB caches recent virtual to physical address mappings </li></ul><ul><ul><li>ASID or TLB flash is used to enforce protection </li></ul></ul>
  19. 19. TLB internals <ul><li>TLB is associative, high speed memory </li></ul><ul><ul><li>Each entry is a pair (tag,value) </li></ul></ul><ul><ul><li>When presented with an item it is compared to all keys simultaneously </li></ul></ul><ul><ul><li>If found, the value is returned; otherwise, it is a TLB miss </li></ul></ul><ul><ul><li>Expensive: number of typical TLB entries: 64-1024 </li></ul></ul><ul><ul><li>Do not confuse with memory cache! </li></ul></ul>
  20. 20. Address translation with TLB
  21. 21. Bits in the PTE: Present (valid) <ul><li>Present (valid) bit </li></ul><ul><ul><li>Indicates whether the page is assigned to frame or not </li></ul></ul><ul><ul><li>Invalid page can be not a part of any memory segment </li></ul></ul><ul><ul><li>A reference to an invalid page generates page fault which is handled by the operating system </li></ul></ul>
  22. 22. Bits in PTE: modified, used <ul><li>Modified (dirty) bit </li></ul><ul><ul><li>Indicates whether the page has been modified </li></ul></ul><ul><ul><li>Unmodified pages need not be written back to the disk when evicted </li></ul></ul><ul><li>Used bit </li></ul><ul><ul><li>Indicates whether the page has been accessed recently </li></ul></ul><ul><ul><li>Used by the page replacement algorithm </li></ul></ul>
  23. 23. Bits in PTE <ul><li>Access permissions bit </li></ul><ul><ul><li>indicates whether the page is read-only or read-write </li></ul></ul><ul><li>UNIX copy-on-write bit </li></ul><ul><ul><li>Set whether more than one process shares a page </li></ul></ul><ul><ul><li>If one of the processes writes into the page, a separate copy must first be made for all other processes sharing the page </li></ul></ul><ul><ul><li>Useful for optimizing fork() </li></ul></ul>
  24. 24. Protection with VM <ul><li>Preventing processes from accessing other process pages </li></ul><ul><li>Simple with FMPT </li></ul><ul><ul><li>Load the process page table base address into a register upon context switch </li></ul></ul><ul><li>ASID with IPT </li></ul>
  25. 25. Segmentation with paging <ul><li>Segmentation </li></ul><ul><ul><li>simplifies protection and sharing, enforce modularity, but prone to external fragmentation </li></ul></ul><ul><li>Paging </li></ul><ul><ul><li>transparent, eliminates ext. fragmentation, allows for sophisticated memory management </li></ul></ul><ul><li>Segmentation and paging can be combined </li></ul>
  26. 26. Address translation Main Memory Page Frame Offset Paging Page Table P# + Frame # Offset Seg Table Ptr + S # Segmentation Program Segment Table Seg # Page # Offset
  27. 27. Page size considerations <ul><li>Small page size </li></ul><ul><ul><li>better approximates locality </li></ul></ul><ul><ul><li>large page tables </li></ul></ul><ul><ul><li>inefficient disk transfer </li></ul></ul><ul><li>Large page size </li></ul><ul><ul><li>internal fragmentation </li></ul></ul><ul><li>Most modern architectures support a number of different page sizes </li></ul><ul><ul><ul><li>a configurable system parameter </li></ul></ul></ul>
  28. 28. Next : Page replacement

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