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Class Notes WW10


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Class Notes WW10

  1. 1. The Applications of Nano Materials Department of Chemical and Materials Engineering San Jose State University Zhen Guo, Ph. D.
  2. 2. How to study Nanomaterials Microstructure Properties Materials Applications Processing Basic Materials Science Principles Part I -- Done Part II – Done Part III – This one
  3. 3. The Applications of Nano Materials Nano Materials Applications Electronics Magnetic Device Optics MEMS Bio Device Structure Daily Life consumable Renewable Energy
  4. 4. Applications of Nano Materials Dr. Danielle Chamberlin, Agilent Corp (Term paper due) Application ( VI I) – Nano Materials and Optical Device Week 15 05/11 Dr. Sun Lei Digital Health, Intel Corp. Applications (V I ) -- Biochemical Properties of Nano Materials Week 14 05/04 Dr. Geetha Dholakia NASA AMES Research Center Application (V) – Nano materials applications on Aerospace Week 13 04/27 Prof. Jiangyu Li University of Washington Application ( I V) – Nano Magnetic Materials Week 12 04/20 Prof. David Mitlin University of Alberta Application ( III ) – Nano Materials and Renewable Energy source Week 11 04/13 Blue Sheet #4 Peer review comment Due Application (I I ) – Nano Electric Materials: Quantum Computing Logic Device and memory Week 10 04/06 Quiz #4 1st Draft Due (3 copies) Application (I) – Nano grained structural materials and Nano Composite Week 9 03/22
  5. 5. Session X – Nano Electric Materials -- Single Electron Transistor -- Other Novel Transistor -- Nano Crystal Memory -- Phase Change Memory
  6. 6. MOSFET Principles <ul><li>Review MOSFET principles – accumulations, depletion, and inversion. Vt, Vg, Ids, Idsat, etc. </li></ul><ul><li>Just remember that Electrons are like water, source / drain like two bottles, channel is a pipe in between and gate is like a valve to open / close the pipe... </li></ul>
  7. 7. Single Electron Box <ul><li>Single Electron Box </li></ul><ul><ul><li>One Quantum Dot </li></ul></ul><ul><ul><li>Two Electrodes </li></ul></ul><ul><ul><li>Tunneling Junction </li></ul></ul><ul><ul><li>Control Gate Capacitor </li></ul></ul><ul><li>Electrons are injected/ejected into / from quantum dots thru tunneling junctions. </li></ul><ul><li>Extra electrons injected into quantum dots will lead to excessive charging energy </li></ul>Courtesy from Rainer Waser: Nano-electronics and Information technology PP427-445
  8. 8. Coulomb Blockade <ul><li>Coulomb Blockade is caused by excessive charging energy Wc which increase as the size of quantum dot decrease </li></ul>With adding extra electron into QD W c =e 2 /2C sp r  => C sp  => W c  When Wc >> kT, thermal energy is no longer sufficient to overcome excessive charging energy => Coulomb Blockade <ul><li>Quantum Effect of Coulomb Blockade – Quantum confinement cause energy level split => next electrons may need to occupy higher energy level </li></ul>W c = e 2 /2C sp +  E (n)
  9. 9. Bias Condition for Coulomb Blockade <ul><li>When gate voltage is zero, the charge at quantum dot is zero. </li></ul><ul><li>As gate voltage increases to a certain value, electrons are attracted to quantum dot, making 1e net charge of dot </li></ul><ul><li>Further increase gate voltage will increase electron number. </li></ul>
  10. 10. Bias Condition for Coulomb Blockade <ul><li>To maintain the electron number in quantum dots, we have </li></ul>Courtesy from Rainer Waser: Nano-electronics and Information technology <ul><li>To substitute the equations in previous slide, we obtained </li></ul>When Consider both sides, we have or
  11. 11. Single Electron Transistor (SET) <ul><li>SET – three terminal switching device that can transfer electron one by one from source to drain </li></ul>Courtesy from Rainer Waser: Nano-electronics and Information technology -- can be considered as two independent tunneling junctions -- Each will have to satisfy Coulomb Blockade conditions
  12. 12. Single Electron Transistor (SET) Con’d: Two Equations can be reduced to Source Blue Line Drain Red Line <ul><li>In grey area, both source and drain satisfy coulomb blockade condition for same n value=>Fixed # electrons. </li></ul><ul><li>In green area, source and drain satisfy different value. </li></ul><ul><ul><li>-- In Area A, for source junction, it satisfy n=1 so one electron will tunnel from source to QD </li></ul></ul><ul><ul><li>-- Once electron at QD, it found that drain junction is favor n=0 so this electron will further tunnel to drain </li></ul></ul><ul><ul><li>-- Current Flow from source to drain </li></ul></ul><ul><ul><li>-- Giving a small Vds, Ids will vary with Vg periodically </li></ul></ul><ul><ul><li>-- Vg can behave as a switch. Vg=0, need Vds greater than threshold, Vg=e/2Cg, linear Ids verse Vds </li></ul></ul>
  13. 13. Fabrication of SET (I) <ul><li>PADOX – Pattern Dependent Oxidization </li></ul><ul><ul><li>-- 1-D Si Nano Wire connected with 2-D Si layers at both ends </li></ul></ul><ul><ul><li>-- Oxidization process forms tunneling barriers at both ends. </li></ul></ul><ul><ul><li>-- Can be either width or thickness modulated. </li></ul></ul><ul><ul><li>-- For Vertical PADOX, it is possible to form 2 tiny islands </li></ul></ul>
  14. 14. Fabrication of SET (II) <ul><li>Surface-Treated SOI Channel </li></ul><ul><ul><li>-- 1-D SOI channel intentionally undulated with alkaline based solutions </li></ul></ul><ul><ul><li>-- The nano scaled undulation results in potential fluctuation due to the difference of quantum confinement effect from one part to another. </li></ul></ul><ul><ul><li>-- The channel effectively splits into several quantum dots. </li></ul></ul><ul><ul><li>-- Process is completely compatible with current CMOS fabrications </li></ul></ul>
  15. 15. Advantage and Disadvantages <ul><li>Advantages: </li></ul><ul><ul><li>Lower power assumption </li></ul></ul><ul><ul><li>Good scalability </li></ul></ul><ul><li>Disadvantages </li></ul><ul><ul><li>Operated usually at low temperature </li></ul></ul><ul><ul><li>High output impedance due to tunneling </li></ul></ul><ul><ul><li>Vds has to be less than Vg to have gate fully control the switch. </li></ul></ul>
  16. 16. Other Novel Logic Transistor <ul><li>Ferro-Electric Field Effect Transistor (FeFET) </li></ul>Courtesy from Rainer Waser: Nano-electronics and Information technology -- On state: for positive gate voltage, the polarization vector P is directed towards Channel. -- Cohesive voltage Vc keep remanent polarization Pr large enough to invert channel and keep current flow even when Vg=0 (non-volatile operation) -- Off State: negative gate voltage will bring Pr direct opposite to channel and + charge are accumulated in the channel region. Channel resistance is high and no current flow
  17. 17. Other Novel Logic Transistor <ul><li>Spintronic transistor – based on the effect of spin orientation on electron’s transportation properties </li></ul>-- Source and drain are both ferro-magnetic materials with identical magnetization direction -- Channel is a hetero-junction of semiconductor compound with a highly mobile 2-D electron gas. -- Source will inject a spin-polarized current into channel. Without gate voltage, spin will remain unchanged so electron travel to drain on a very high velocity (1% of speed of light) -- When applied gate voltage, spin direction will be rotated by magnetic field so the spin is no longer aligned with drain side => More scattering, higher resistance, lower velocity.
  18. 18. Other Novel Logic Transistor <ul><li>Molecular transistor – Single Molecular acting as electronic switch and storage elements </li></ul>
  19. 19. Nano Crystal Memory <ul><li>Introduction </li></ul><ul><li>Why Nano Crystal Memory </li></ul><ul><li>New Development on Nano Crystal Memory </li></ul>Nano Crystal Flash Memory Traditional Floating Gate Memory Floating Gate Usually Poly Si
  20. 21. Recent Trend in Non-volatile Memory <ul><li>Current flash memory is continuing to follow Moore’s Law at 90 / 65 / 45nm Nodes </li></ul><ul><ul><ul><li>-- 18 years for 9 generations </li></ul></ul></ul><ul><li>ETOX and NAND will still be the mainstream flash memory in next 5 years. </li></ul><ul><li>There is no clear roadmap to continuously scale flash memory beyond 32nm node. </li></ul>
  21. 22. ITRS Roadmap for Emerging Memory Device (2003) 63
  22. 23. Nano-crystal Memory for Technology Gap S. J. Baik et al, IDEM, 2003
  23. 24. Principle of Nano Crystal Memory Improvement of Data Retention and SILT. Nano Crystal Flash Memory Traditional Floating Gate Memory Floating Gate Usually Poly Si
  24. 25. Nano Crystal as Storing Bit <ul><li>Nano Crystal Technology has been studied extensively to replace traditional floating gate as charge storage media . </li></ul><ul><li>Advantages: </li></ul><ul><ul><li>Scalability with Channel Tunneling and Erase </li></ul></ul><ul><ul><li>Compatible with Traditional CMOS Platform </li></ul></ul><ul><ul><li>Improved Charge Retention and Endurance </li></ul></ul><ul><ul><li>Potential Multi Bit usage </li></ul></ul><ul><li>Challenges: </li></ul><ul><ul><li>Strictly control the size and distribution of nano crystals </li></ul></ul><ul><ul><li>Still Litho node limited </li></ul></ul><ul><ul><li>Much work to be done for a integrated reliable and high yield process </li></ul></ul>
  25. 26. Silicon Nano Crystal as Storing Media R. Muralidhar et al. IDEM, 2003 <ul><li>Reduce SILC and thus improve data retention and endurance </li></ul><ul><li>Decrease gate coupling and thus improve leakage and erase saturation </li></ul><ul><li>Possible multi-bit storage as particle size goes down to discrete energy state of electrons </li></ul>
  26. 27. Metal Dots as Storage Media <ul><li>Metal dots can be Co, W or Au </li></ul><ul><li>Suppose to be better than Si as work function is higher (more attractive to electrons) </li></ul><ul><li>Multilayer can improve retention and endurance </li></ul>C. Lee, et al, IDEM, 2003 M. Takata, et al, IDEM, 2003
  27. 28. Silicon Nano Crystals Produced by CVD Methods (I) <ul><li>A Si-rich SiOx thin film is deposited on Si surface by PECVD method. The non-stoichemetry are controlled by gas flow ratios. </li></ul><ul><li>An furnace annealing were performed on this film at 1000C in N2 atmosphere to precipitate Si Nano crystals out of supersaturated film. </li></ul>-- U.S. Pattern Pending
  28. 29. Si – SiO 2 Binary Phase Diagram -- Si has no solubility in SiO2 at equilibrium state
  29. 30. Silicon Nano Crystals Produced by CVD Methods (II) -- U.S. Pattern Pending <ul><li>Thermal Decomposition of SiH 4 precursor on Silicon surface for Si Nano crystals . </li></ul><ul><li>No Anneal Step is required. </li></ul><ul><li>Most compatible with current CMOS technology. </li></ul><ul><li>Challenge is how to control location and size distribution. </li></ul>
  30. 31. Other Ideas of Synthesis Nano Crystals <ul><li>Controllable Nucleation and Growth </li></ul><ul><li>Volmer -Weber Growth (3-D Island Growth) on Thin Film </li></ul><ul><li>In-Situ Phase Segregation ( Spinodal Decomposition ) </li></ul><ul><li>Pre-patterned Growth ( Polymer Precursor Self-assembly ) </li></ul>
  31. 32. Summary <ul><li>Nano storing bit can and must meet Si technology in 5 years. </li></ul><ul><li>Nano crystal memory is the most promising one to be compatible with CMOS platform </li></ul><ul><li>Many challenges still exist ranging from manufacturing nano particles to integration into traditional process flow </li></ul><ul><li>Materials scientist can definitely help! </li></ul>
  32. 33. Phase Transformation Memory <ul><li>Same principle as DVD </li></ul><ul><li>Using transformation between amorphous and crystalline phase based on cooling speed. </li></ul><ul><li>Different phases has different optical and electrical properties. </li></ul><ul><li>Easy to be integrated and scalable. </li></ul>Phase Transformation Memory
  33. 34. Stephen Lai, Intel, December 2003.
  34. 35. Basic Architecture of Nano Crystal Memory Floating nano crystals can be -- Silicon nano crystals (multiple or single) -- Silicon nano wires -- Metal nano dots (single or Multi layers) S. Tiwari et al. Appl, Phy lett, 1996 R. Muralidhar et al. IDEM, 2003
  35. 36. Nucleation and Growth Control <ul><li>Nano particles need strong nucleation and slow growth </li></ul><ul><li>Low temperature (high  T) promote nucleation and slow down growth </li></ul><ul><li>The distance among nucleation sites has to be bigger than diffusion length </li></ul><ul><li>Nucleus size should be controlled around critical radius </li></ul>
  36. 37. Volmer-Weber Growth <ul><li>3-D island growth </li></ul><ul><li>Neither complete wetting nor complete non-wetting surface </li></ul><ul><li>Island size and distribution controlled by heterogeneous nucleation sites </li></ul>
  37. 38. Spinodal Decomposition <ul><li>Spontaneous transformation due to instability </li></ul><ul><li>No nucleation barriers-only require local compositional fluctuations </li></ul><ul><li>Wave length (or particle size) is a function of undercooling </li></ul><ul><li>Misfit strain will also play a key role in particle size (barriers for growth) </li></ul>
  38. 39. Self-Assembly Patterning K. W. Guarini et. al. IDEM, 2003