Chapter 5

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Chapter 5

  1. 1. Chapter 5 Memory
  2. 2. Outline <ul><li>Memory Write Ability and Storage Permanence </li></ul><ul><li>Common Memory Types </li></ul><ul><li>Composing Memory </li></ul><ul><li>Memory Hierarchy and Cache </li></ul><ul><li>Advanced RAM </li></ul>
  3. 3. Introduction <ul><li>Embedded system’s functionality aspects </li></ul><ul><ul><li>Processing </li></ul></ul><ul><ul><ul><li>processors </li></ul></ul></ul><ul><ul><ul><li>transformation of data </li></ul></ul></ul><ul><ul><li>Storage </li></ul></ul><ul><ul><ul><li>memory </li></ul></ul></ul><ul><ul><ul><li>retention of data </li></ul></ul></ul><ul><ul><li>Communication </li></ul></ul><ul><ul><ul><li>buses </li></ul></ul></ul><ul><ul><ul><li>transfer of data </li></ul></ul></ul>
  4. 4. Memory: basic concepts <ul><li>Stores large number of bits </li></ul><ul><ul><li>m x n : m words of n bits each </li></ul></ul><ul><ul><li>k = Log 2 ( m ) address input signals </li></ul></ul><ul><ul><li>or m = 2^k words </li></ul></ul><ul><ul><li>e.g., 4,096 x 8 memory: </li></ul></ul><ul><ul><ul><li>32,768 bits </li></ul></ul></ul><ul><ul><ul><li>12 address input signals </li></ul></ul></ul><ul><ul><ul><li>8 input/output data signals </li></ul></ul></ul><ul><li>Memory access </li></ul><ul><ul><li>r/w: selects read or write </li></ul></ul><ul><ul><li>enable: read or write only when asserted </li></ul></ul><ul><ul><li>multiport: multiple accesses to different locations simultaneously </li></ul></ul>m × n memory … … n bits per word m words enable 2 k × n read and write memory A 0 … r/w … Q 0 Q n-1 A k-1 memory external view
  5. 5. Write ability/ storage permanence <ul><li>Traditional ROM/RAM distinctions </li></ul><ul><ul><li>ROM </li></ul></ul><ul><ul><ul><li>read only, bits stored without power </li></ul></ul></ul><ul><ul><li>RAM </li></ul></ul><ul><ul><ul><li>read and write, lose stored bits without power </li></ul></ul></ul><ul><li>Traditional distinctions blurred </li></ul><ul><ul><li>Advanced ROMs can be written to </li></ul></ul><ul><ul><ul><li>e.g., EEPROM </li></ul></ul></ul><ul><ul><li>Advanced RAMs can hold bits without power </li></ul></ul><ul><ul><ul><li>e.g., NVRAM </li></ul></ul></ul><ul><li>Write ability </li></ul><ul><ul><li>Manner and speed a memory can be written </li></ul></ul><ul><li>Storage permanence </li></ul><ul><ul><li>ability of memory to hold stored bits after they are written </li></ul></ul>Write ability and storage permanence of memories, showing relative degrees along each axis (not to scale). External programmer OR in-system, block-oriented writes, 1,000s of cycles Battery life (10 years) Write ability EPROM Mask-programmed ROM EEPROM FLASH NVRAM SRAM/DRAM Storage permanence Nonvolatile In-system programmable Ideal memory OTP ROM During fabrication only External programmer, 1,000s of cycles External programmer, one time only External programmer OR in-system, 1,000s of cycles In-system, fast writes, unlimited cycles Near zero Tens of years Life of product
  6. 6. Write ability <ul><li>Ranges of write ability </li></ul><ul><ul><li>High end </li></ul></ul><ul><ul><ul><li>processor writes to memory simply and quickly </li></ul></ul></ul><ul><ul><ul><li>e.g., RAM </li></ul></ul></ul><ul><ul><li>Middle range </li></ul></ul><ul><ul><ul><li>processor writes to memory, but slower </li></ul></ul></ul><ul><ul><ul><li>e.g., FLASH, EEPROM </li></ul></ul></ul><ul><ul><li>Lower range </li></ul></ul><ul><ul><ul><li>special equipment, “programmer”, must be used to write to memory </li></ul></ul></ul><ul><ul><ul><li>e.g., EPROM, OTP ROM </li></ul></ul></ul><ul><ul><li>Low end </li></ul></ul><ul><ul><ul><li>bits stored only during fabrication </li></ul></ul></ul><ul><ul><ul><li>e.g., Mask-programmed ROM </li></ul></ul></ul><ul><li>In-system programmable memory </li></ul><ul><ul><li>Can be written to by a processor in the embedded system using the memory </li></ul></ul><ul><ul><li>Memories in high end and middle range of write ability </li></ul></ul>
  7. 7. Storage permanence <ul><li>Range of storage permanence </li></ul><ul><ul><li>High end </li></ul></ul><ul><ul><ul><li>essentially never loses bits </li></ul></ul></ul><ul><ul><ul><li>e.g., mask-programmed ROM </li></ul></ul></ul><ul><ul><li>Middle range </li></ul></ul><ul><ul><ul><li>holds bits days, months, or years after memory’s power source turned off </li></ul></ul></ul><ul><ul><ul><li>e.g., NVRAM </li></ul></ul></ul><ul><ul><li>Lower range </li></ul></ul><ul><ul><ul><li>holds bits as long as power supplied to memory </li></ul></ul></ul><ul><ul><ul><li>e.g., SRAM </li></ul></ul></ul><ul><ul><li>Low end </li></ul></ul><ul><ul><ul><li>begins to lose bits almost immediately after written </li></ul></ul></ul><ul><ul><ul><li>e.g., DRAM </li></ul></ul></ul><ul><li>Nonvolatile memory </li></ul><ul><ul><li>Holds bits after power is no longer supplied </li></ul></ul><ul><ul><li>High end and middle range of storage permanence </li></ul></ul>
  8. 8. ROM: “Read-Only” Memory <ul><li>Nonvolatile memory </li></ul><ul><li>Can be read from but not written to, by a processor in an embedded system </li></ul><ul><li>Traditionally written to, “programmed”, before inserting to embedded system </li></ul><ul><li>Uses </li></ul><ul><ul><li>Store software program for general-purpose processor </li></ul></ul><ul><ul><ul><li>program instructions can be one or more ROM words </li></ul></ul></ul><ul><ul><li>Store constant data needed by system </li></ul></ul><ul><ul><li>Implement combinational circuit </li></ul></ul>2 k × n ROM … Q 0 Q n-1 A 0 … enable A k-1 External view
  9. 9. Example: 8 x 4 ROM <ul><li>Horizontal lines = words </li></ul><ul><li>Vertical lines = data </li></ul><ul><li>Lines connected only at circles </li></ul><ul><li>Decoder sets word 2’s line to 1 if address input is 010 </li></ul><ul><li>Data lines Q 3 and Q 1 are set to 1 because there is a “programmed” connection with word 2’s line </li></ul><ul><li>Word 2 is not connected with data lines Q 2 and Q 0 </li></ul><ul><li>Output is 1010 </li></ul>8 × 4 ROM 3×8 decoder Q 0 Q 3 A 0 enable A 2 word 0 word 1 A 1 Q 2 Q 1 programmable connection wired-OR word line data line word 2 Internal view
  10. 10. Implementing combinational function <ul><li>Any combinational circuit of n functions of same k variables can be done with 2^ k x n ROM </li></ul>Truth table Inputs (address) Outputs a b c y z 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 z y c enable a b 8×2 ROM word 0 word 1 word 7
  11. 11. Mask-programmed ROM <ul><li>Connections “programmed” at fabrication </li></ul><ul><ul><li>set of masks </li></ul></ul><ul><li>Lowest write ability </li></ul><ul><ul><li>only once </li></ul></ul><ul><li>Highest storage permanence </li></ul><ul><ul><li>bits never change unless damaged </li></ul></ul><ul><li>Typically used for final design of high-volume systems </li></ul><ul><ul><li>spread out NRE cost for a low unit cost </li></ul></ul>
  12. 12. OTP ROM: One-time programmable ROM <ul><li>Connections “programmed” after manufacture by user </li></ul><ul><ul><li>user provides file of desired contents of ROM </li></ul></ul><ul><ul><li>file input to machine called ROM programmer </li></ul></ul><ul><ul><li>each programmable connection is a fuse </li></ul></ul><ul><ul><li>ROM programmer blows fuses where connections should not exist </li></ul></ul><ul><li>Very low write ability </li></ul><ul><ul><li>typically written only once and requires ROM programmer device </li></ul></ul><ul><li>Very high storage permanence </li></ul><ul><ul><li>bits don’t change unless reconnected to programmer and more fuses blown </li></ul></ul><ul><li>Commonly used in final products </li></ul><ul><ul><li>cheaper, harder to inadvertently modify </li></ul></ul>
  13. 13. EPROM: Erasable programmable ROM <ul><li>Programmable component is a MOS transistor </li></ul><ul><ul><li>Transistor has “floating” gate surrounded by an insulator </li></ul></ul><ul><ul><li>(a) Negative charges form a channel between source and drain storing a logic 1 </li></ul></ul><ul><ul><li>(b) Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0 </li></ul></ul><ul><ul><li>(c) (Erase) Shining UV rays on surface of floating-gate causes negative charges to return to channel from floating gate restoring the logic 1 </li></ul></ul><ul><ul><li>(d) An EPROM package showing quartz window through which UV light can pass </li></ul></ul><ul><li>Better write ability </li></ul><ul><ul><li>can be erased and reprogrammed thousands of times </li></ul></ul><ul><li>Reduced storage permanence </li></ul><ul><ul><li>program lasts about 10 years but is susceptible to radiation and electric noise </li></ul></ul><ul><li>Typically used during design development </li></ul>. (d) (a) (b) source drain +15V source drain 0V (c) source drain floating gate 5-30 min
  14. 14. EEPROM: Electrically erasable programmable ROM <ul><li>Programmed and erased electronically </li></ul><ul><ul><li>typically by using higher than normal voltage </li></ul></ul><ul><ul><li>can program and erase individual words </li></ul></ul><ul><li>Better write ability </li></ul><ul><ul><li>can be in-system programmable with built-in circuit to provide higher than normal voltage </li></ul></ul><ul><ul><ul><li>built-in memory controller commonly used to hide details from memory user </li></ul></ul></ul><ul><ul><li>writes very slow due to erasing and programming </li></ul></ul><ul><ul><ul><li>“ busy” pin indicates to processor EEPROM still writing </li></ul></ul></ul><ul><ul><li>can be erased and programmed tens of thousands of times </li></ul></ul><ul><li>Similar storage permanence to EPROM (about 10 years) </li></ul><ul><li>Far more convenient than EPROMs, but more expensive </li></ul>
  15. 15. Flash Memory <ul><li>Extension of EEPROM </li></ul><ul><ul><li>Same floating gate principle </li></ul></ul><ul><ul><li>Same write ability and storage permanence </li></ul></ul><ul><li>Fast erase </li></ul><ul><ul><li>Large blocks of memory erased at once, rather than one word at a time </li></ul></ul><ul><ul><li>Blocks typically several thousand bytes large </li></ul></ul><ul><li>Writes to single words may be slower </li></ul><ul><ul><li>Entire block must be read, word updated, then entire block written back </li></ul></ul><ul><li>Used with embedded systems storing large data items in nonvolatile memory </li></ul><ul><ul><li>e.g., digital cameras, TV set-top boxes, cell phones </li></ul></ul>
  16. 16. RAM: “Random-access” memory <ul><li>Typically volatile memory </li></ul><ul><ul><li>bits are not held without power supply </li></ul></ul><ul><li>R ead and written to easily by embedded system during execution </li></ul><ul><li>Internal structure more complex than ROM </li></ul><ul><ul><li>a word consists of several memory cells, each storing 1 bit </li></ul></ul><ul><ul><li>ea ch input and output data line connects to each cell in its column </li></ul></ul><ul><ul><li>rd/wr connected to every cell </li></ul></ul><ul><ul><li>when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read </li></ul></ul>enable 2 k × n read and write memory A 0 … r/w … Q 0 Q n-1 A k-1 external view 4×4 RAM 2×4 decoder Q 0 Q 3 A 0 enable A 1 Q 2 Q 1 Memory cell I 0 I 3 I 2 I 1 rd/wr To every cell internal view
  17. 17. Basic types of RAM <ul><li>SRAM: Static RAM </li></ul><ul><ul><li>Memory cell uses flip-flop to store bit </li></ul></ul><ul><ul><li>Requires 6 transistors </li></ul></ul><ul><ul><li>Holds data as long as power supplied </li></ul></ul><ul><li>DRAM: Dynamic RAM </li></ul><ul><ul><li>Memory cell uses MOS transistor and capacitor to store bit </li></ul></ul><ul><ul><li>More compact than SRAM </li></ul></ul><ul><ul><li>“ Refresh” required due to capacitor leak </li></ul></ul><ul><ul><ul><li>word’s cells refreshed when read </li></ul></ul></ul><ul><ul><li>Typical refresh rate 15.625 microsec. </li></ul></ul><ul><ul><li>Slower to access than SRAM </li></ul></ul>memory cell internals Data W Data' SRAM Data W DRAM
  18. 18. Ram variations <ul><li>PSRAM: Pseudo-static RAM </li></ul><ul><ul><li>DRAM with built-in memory refresh controller </li></ul></ul><ul><ul><li>Popular low-cost high-density alternative to SRAM </li></ul></ul><ul><li>NVRAM: Nonvolatile RAM </li></ul><ul><ul><li>Holds data after external power removed </li></ul></ul><ul><ul><li>Battery-backed RAM </li></ul></ul><ul><ul><ul><li>SRAM with own permanently connected battery </li></ul></ul></ul><ul><ul><ul><li>writes as fast as reads </li></ul></ul></ul><ul><ul><ul><li>no limit on number of writes unlike nonvolatile ROM-based memory </li></ul></ul></ul><ul><ul><li>SRAM with EEPROM or flash </li></ul></ul><ul><ul><ul><li>stores complete RAM contents on EEPROM or flash before power turned off </li></ul></ul></ul>
  19. 19. Example: HM6264 & 27C256 RAM/ROM devices <ul><li>Low-cost low-capacity memory devices </li></ul><ul><li>Commonly used in 8-bit microcontroller-based embedded systems </li></ul><ul><li>First two numeric digits indicate device type </li></ul><ul><ul><li>RAM: 62 </li></ul></ul><ul><ul><li>ROM: 27 </li></ul></ul><ul><li>Subsequent digits indicate capacity in kilobits </li></ul>Device Access Time (ns) Standby Pwr. (mW) Active Pwr. (mW) Vcc Voltage (V) HM6264 85-100 .01 15 5 27C256 90 .5 100 5 22 20 data<7…0> addr<15...0> /OE /WE /CS1 CS2 HM6264 11-13, 15-19 2,23,21,24, 25, 3-10 22 27 20 26 data<7…0> addr<15...0> /OE /CS 27C256 11-13, 15-19 27,26,2, 2 3,21, 24,25, 3-10 block diagrams device characteristics timing diagrams data addr OE /CS1 CS2 Read operation data addr WE /CS1 CS2 Write operation
  20. 20. Example: TC55V2325FF-100 memory device <ul><li>2-megabit synchronous pipelined burst SRAM memory device </li></ul><ul><li>Designed to be interfaced with 32-bit processors </li></ul><ul><li>Capable of fast sequential reads and writes as well as single byte I/O </li></ul>timing diagram block diagram device characteristics data<31…0> addr<15…0> addr<10...0> /CS1 /CS2 CS3 /WE /OE MODE /ADSP /ADSC /ADV CLK TC55V2325FF-100 Device Access Time (ns) Standby Pwr. (mW) Active Pwr. (mW) Vcc Voltage (V) TC55V23 10 na 1200 3.3 25FF-100 A single read operation CLK /ADSP /ADSC /ADV addr <15…0> /WE /OE /CS1 and /CS2 CS3 data<31…0>
  21. 21. Composing memory <ul><li>Memory size needed often differs from size of readily available memories </li></ul><ul><li>When available memory is larger, simply ignore unneeded high-order address bits and higher data lines </li></ul><ul><li>When available memory is smaller, compose several smaller memories into one larger memory </li></ul><ul><ul><li>Connect side-by-side to increase width of words </li></ul></ul><ul><ul><li>Connect top to bottom to increase number of words </li></ul></ul><ul><ul><ul><li>added high-order address line selects smaller memory containing desired word using a decoder </li></ul></ul></ul><ul><ul><li>Combine techniques to increase number and width of words </li></ul></ul>… 2 m × 3n ROM 2 m × n ROM A 0 … enable 2 m × n ROM … 2 m × n ROM … Q 3n-1 Q 2n-1 … Q 0 … A m Increase width of words 2 m+1 × n ROM 2 m × n ROM A 0 … enable … 2 m × n ROM A m-1 A m 1 × 2 decoder … … … Q n-1 Q 0 … Increase number of words A enable outputs Increase number and width of words
  22. 22. Memory hierarchy <ul><li>Want inexpensive, fast memory </li></ul><ul><li>Main memory </li></ul><ul><ul><li>Large, inexpensive, slow memory stores entire program and data </li></ul></ul><ul><li>Cache </li></ul><ul><ul><li>Small, expensive, fast memory stores copy of likely accessed parts of larger memory </li></ul></ul><ul><ul><li>Can be multiple levels of cache </li></ul></ul>Processor Cache Main memory Disk Tape Registers
  23. 23. Cache <ul><li>Usually designed with SRAM </li></ul><ul><ul><li>faster but more expensive than DRAM </li></ul></ul><ul><li>Usually on same chip as processor </li></ul><ul><ul><li>space limited, so much smaller than off-chip main memory </li></ul></ul><ul><ul><li>faster access ( 1 cycle vs. several cycles for main memory) </li></ul></ul><ul><li>Cache operation: </li></ul><ul><ul><li>Request for main memory access (read or write) </li></ul></ul><ul><ul><li>First, check cache for copy </li></ul></ul><ul><ul><ul><li>cache hit </li></ul></ul></ul><ul><ul><ul><ul><li>copy is in cache, quick access </li></ul></ul></ul></ul><ul><ul><ul><li>cache miss </li></ul></ul></ul><ul><ul><ul><ul><li>copy not in cache, read address and possibly its neighbors into cache </li></ul></ul></ul></ul><ul><li>Several cache design choices </li></ul><ul><ul><li>cache mapping, replacement policies, and write techniques </li></ul></ul>
  24. 24. Cache mapping <ul><li>Far fewer number of available cache addresses </li></ul><ul><li>Are address’ contents in cache? </li></ul><ul><li>Cache mapping used to assign main memory address to cache address and determine hit or miss </li></ul><ul><li>Three basic techniques: </li></ul><ul><ul><li>Direct mapping </li></ul></ul><ul><ul><li>Fully associative mapping </li></ul></ul><ul><ul><li>Set-associative mapping </li></ul></ul><ul><li>Caches partitioned into indivisible blocks or lines of adjacent memory addresses </li></ul><ul><ul><li>usually 4 or 8 addresses per line </li></ul></ul>
  25. 25. Direct mapping <ul><li>Main memory address divided into 2 fields </li></ul><ul><ul><li>Index </li></ul></ul><ul><ul><ul><li>cache address </li></ul></ul></ul><ul><ul><ul><li>number of bits determined by cache size </li></ul></ul></ul><ul><ul><li>Tag </li></ul></ul><ul><ul><ul><li>compared with tag stored in cache at address indicated by index </li></ul></ul></ul><ul><ul><ul><li>if tags match, check valid bit </li></ul></ul></ul><ul><li>Valid bit </li></ul><ul><ul><li>indicates whether data in slot has been loaded from memory </li></ul></ul><ul><li>Offset </li></ul><ul><ul><li>used to find particular word in cache line </li></ul></ul>Data Valid Tag Index Offset = V T D
  26. 26. Fully associative mapping <ul><li>Complete main memory address stored in each cache address </li></ul><ul><li>All addresses stored in cache simultaneously compared with desired address </li></ul><ul><li>Valid bit and offset same as direct mapping </li></ul>Tag Offset = V T D Valid V T D … V T D = = Data
  27. 27. Set-associative mapping <ul><li>Compromise between direct mapping and fully associative mapping </li></ul><ul><li>Index same as in direct mapping </li></ul><ul><li>But, each cache address contains content and tags of 2 or more memory address locations </li></ul><ul><li>Tags of that set simultaneously compared as in fully associative mapping </li></ul><ul><li>Cache with set size N called N-way set-associative </li></ul><ul><ul><li>2-way, 4-way, 8-way are common </li></ul></ul>Tag Index Offset = V T D Data Valid V T D =
  28. 28. Cache-replacement policy <ul><li>Technique for choosing which block to replace </li></ul><ul><ul><li>when fully associative cache is full </li></ul></ul><ul><ul><li>when set-associative cache’s line is full </li></ul></ul><ul><li>Direct mapped cache has no choice </li></ul><ul><li>Random </li></ul><ul><ul><li>replace block chosen at random </li></ul></ul><ul><li>LRU: least-recently used </li></ul><ul><ul><li>replace block not accessed for longest time </li></ul></ul><ul><li>FIFO: first-in-first-out </li></ul><ul><ul><li>push block onto queue when accessed </li></ul></ul><ul><ul><li>choose block to replace by popping queue </li></ul></ul>
  29. 29. Cache write techniques <ul><li>When written, data cache must update main memory </li></ul><ul><li>Write-through </li></ul><ul><ul><li>write to main memory whenever cache is written to </li></ul></ul><ul><ul><li>easiest to implement </li></ul></ul><ul><ul><li>processor must wait for slower main memory write </li></ul></ul><ul><ul><li>potential for unnecessary writes </li></ul></ul><ul><li>Write-back </li></ul><ul><ul><li>main memory only written when “dirty” block replaced </li></ul></ul><ul><ul><li>extra dirty bit for each block set when cache block written to </li></ul></ul><ul><ul><li>reduces number of slow main memory writes </li></ul></ul>
  30. 30. Cache impact on system performance <ul><li>Most important parameters in terms of performance: </li></ul><ul><ul><li>Total size of cache </li></ul></ul><ul><ul><ul><li>total number of data bytes cache can hold </li></ul></ul></ul><ul><ul><ul><li>tag, valid and other house keeping bits not included in total </li></ul></ul></ul><ul><ul><li>Degree of associativity </li></ul></ul><ul><ul><li>Data block size </li></ul></ul><ul><li>Larger caches achieve lower miss rates but higher access cost </li></ul><ul><ul><li>e.g., </li></ul></ul><ul><ul><ul><li>2 Kbyte cache: miss rate = 15%, hit cost = 2 cycles, miss cost = 20 cycles </li></ul></ul></ul><ul><ul><ul><ul><li>avg. cost of memory access = (0.85 * 2) + (0.15 * 20) = 4.7 cycles </li></ul></ul></ul></ul><ul><ul><ul><li>4 Kbyte cache: miss rate = 6.5%, hit cost = 3 cycles, miss cost will not change </li></ul></ul></ul><ul><ul><ul><ul><li>avg. cost of memory access = (0.935 * 3) + (0.065 * 20) = 4.105 cycles (improvement) </li></ul></ul></ul></ul><ul><ul><ul><li>8 Kbyte cache: miss rate = 5.565%, hit cost = 4 cycles, miss cost will not change </li></ul></ul></ul><ul><ul><ul><ul><li>avg. cost of memory access = (0.94435 * 4) + (0.05565 * 20) = 4.8904 cycles (worse) </li></ul></ul></ul></ul>
  31. 31. Cache performance trade-offs <ul><li>Improving cache hit rate without increasing size </li></ul><ul><ul><li>Increase line size </li></ul></ul><ul><ul><li>Change set-associativity </li></ul></ul>0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 1 Kb 2 Kb 4 Kb 8 Kb 16 Kb 32 Kb 64 Kb 128 Kb 1 way 2 way 4 way 8 way % cache miss cache size
  32. 32. Advanced RAM <ul><li>DRAMs commonly used as main memory in processor based embedded systems </li></ul><ul><ul><li>high capacity, low cost </li></ul></ul><ul><li>Many variations of DRAMs proposed </li></ul><ul><ul><li>need to keep pace with processor speeds </li></ul></ul><ul><ul><li>FPM DRAM: fast page mode DRAM </li></ul></ul><ul><ul><li>EDO DRAM: extended data out DRAM </li></ul></ul><ul><ul><li>SDRAM/ESDRAM: synchronous and enhanced synchronous DRAM </li></ul></ul><ul><ul><li>RDRAM: rambus DRAM </li></ul></ul>
  33. 33. Basic DRAM <ul><li>Address bus multiplexed between row and column components </li></ul><ul><li>Row and column addresses are latched in, sequentially, by strobing ras and cas signals, respectively </li></ul><ul><li>Refresh circuitry can be external or internal to DRAM device </li></ul><ul><ul><li>strobes consecutive memory address periodically causing memory content to be refreshed </li></ul></ul><ul><ul><li>Refresh circuitry disabled during read or write operation </li></ul></ul>Data In Buffer Data Out Buffer rd/ wr data Row Addr. Buffer Col Addr . Buffer address ras cas Bit storage array Row Decoder Col Decoder Refresh Circuit cas, ras, clock Sense Amplifiers
  34. 34. Fast Page Mode DRAM (FPM DRAM) <ul><li>Each row of memory bit array is viewed as a page </li></ul><ul><li>Page contains multiple words </li></ul><ul><li>Individual words addressed by column address </li></ul><ul><li>Timing diagram: </li></ul><ul><ul><li>row (page) address sent </li></ul></ul><ul><ul><li>3 words read consecutively by sending column address for each </li></ul></ul><ul><li>Extra cycle eliminated on each read/write of words from same page </li></ul>row col data col col data data ras cas address data
  35. 35. Extended data out DRAM (EDO DRAM) <ul><li>Improvement of FPM DRAM </li></ul><ul><li>Extra latch before output buffer </li></ul><ul><ul><li>allows strobing of cas before data read operation completed </li></ul></ul><ul><li>Reduces read/write latency by additional cycle </li></ul>row col col col data data data Speedup through overlap ras cas address data
  36. 36. (S)ynchronous and Enhanced Synchronous (ES) DRAM <ul><li>SDRAM latches data on active edge of clock </li></ul><ul><li>Eliminates time to detect ras/cas and rd/wr signals </li></ul><ul><li>A counter is initialized to column address then incremented on active edge of clock to access consecutive memory locations </li></ul><ul><li>ESDRAM improves SDRAM </li></ul><ul><ul><li>added buffers enable overlapping of column addressing </li></ul></ul><ul><ul><li>faster clocking and lower read/write latency possible </li></ul></ul>clock ras cas address data row col data data data
  37. 37. Rambus DRAM (RDRAM) <ul><li>More of a bus interface architecture than DRAM architecture </li></ul><ul><li>Data is latched on both rising and falling edge of clock </li></ul><ul><li>Broken into 4 banks each with own row decoder </li></ul><ul><ul><li>can have 4 pages open at a time </li></ul></ul><ul><li>Capable of very high throughput </li></ul>
  38. 38. DRAM integration problem <ul><li>SRAM easily integrated on same chip as processor </li></ul><ul><li>DRAM more difficult </li></ul><ul><ul><li>Different chip making process between DRAM and conventional logic </li></ul></ul><ul><ul><li>Goal of conventional logic (IC) designers: </li></ul></ul><ul><ul><ul><li>minimize parasitic capacitance to reduce signal propagation delays and power consumption </li></ul></ul></ul><ul><ul><li>Goal of DRAM designers: </li></ul></ul><ul><ul><ul><li>create capacitor cells to retain stored information </li></ul></ul></ul><ul><ul><li>Integration processes beginning to appear </li></ul></ul>
  39. 39. Memory Management Unit (MMU) <ul><li>Duties of MMU </li></ul><ul><ul><li>Handles DRAM refresh, bus interface and arbitration </li></ul></ul><ul><ul><li>Takes care of memory sharing among multiple processors </li></ul></ul><ul><ul><li>Translates logic memory addresses from processor to physical memory addresses of DRAM </li></ul></ul><ul><li>Modern CPUs often come with MMU built-in </li></ul><ul><li>Single-purpose processors can be used </li></ul>

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