ch4-2(memory).ppt

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ch4-2(memory).ppt

  1. 1. Memory Static RAM Dynamic RAM
  2. 2. Memory technology types <ul><li>Read-Only Memory (ROM) </li></ul><ul><ul><li>Non-volatile storage </li></ul></ul><ul><ul><li>ROM, PROM, EPROM, EEPROM </li></ul></ul><ul><li>Random Access Memory (RAM) </li></ul><ul><ul><li>Static RAM (SRAM) </li></ul></ul><ul><ul><li>Dynamic RAM (DRAM) </li></ul></ul>
  3. 3. ROM types <ul><li>OT-PROM (one time programmable) </li></ul><ul><ul><li>Mask ROM </li></ul></ul><ul><ul><li>Fuse ROM </li></ul></ul><ul><li>PROM </li></ul><ul><ul><li>EPROM </li></ul></ul><ul><ul><li>EEPROM </li></ul></ul>Word Line Bit Line Mask ROM Fuse ROM Word Line Bit Line Word Line Bit Line EPROM EEPROM Flash Memory Floating gate
  4. 4. SRAM <ul><li>Hold data without external refresh </li></ul><ul><ul><li>Simplicity : don’t require external refresh circuitry </li></ul></ul><ul><ul><li>Speed: SRAM is faster than DRAM </li></ul></ul><ul><ul><li>Cost: several times more expensive than DRAMs </li></ul></ul><ul><ul><li>Size: take up much more space than DRAMs </li></ul></ul><ul><ul><li>Power: consume more power than DRAMs </li></ul></ul><ul><ul><li>Usage: level 1 or level 2 cache </li></ul></ul>Word Line Bit Line Bit Line Word Line Bit Line
  5. 5. SRAM example: Samsung 1Mx4 High-speed CMOS SRAM <ul><li>Fast access time: 8, 10ns (Max) </li></ul><ul><li>Low power dissipation </li></ul><ul><ul><li>Stanby: 5mA (max) </li></ul></ul><ul><ul><li>Operating: 80 mA (8 ns), 65mA (10ns) </li></ul></ul>
  6. 6. Timing Diagram
  7. 7. DRAM <ul><li>Refresh circuit : storage decay in ms </li></ul><ul><li>DRAMs take up much less space, typically ¼ the silicon area of SRAMs or less (one transistor and a capacitor) </li></ul>Word Line Bit Line
  8. 8. DRAM Organization Long rows to simplify refresh Two new signals: RAS, CAS Row Address Strobe Column Address Strobe replace Chip Select
  9. 9. RAS, CAS Addressing Even to read 1 bit, an entire 64-bit row is read! Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits! Read Cycle Read Row Row Address Latched Read Bit Within Row Column Address Latched Tri-state Outputs
  10. 10. Write cycle timing (1) Latch Row Address Read Row (2) WE low (3) CAS low: replace data bit (4) RAS high: write back the modified row (5) CAS high to complete the memory cycle
  11. 11. RAM Refresh <ul><li>Refresh Frequency:(4ms – 64ms) </li></ul><ul><ul><li>4096 word RAM -- refresh each word once every 4 ms </li></ul></ul><ul><ul><li>Assume 120ns memory access cycle </li></ul></ul><ul><ul><li>This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)! </li></ul></ul><ul><ul><li>But RAM is really organized into 64 rows </li></ul></ul><ul><ul><li>This is one refresh cycle every 62.5  s (1 in 500 DRAM accesses) </li></ul></ul><ul><ul><li>Large capacity DRAMs have 256 rows, refresh once every 16  s </li></ul></ul><ul><li>RAS-only Refresh (RAS cycling, no CAS cycling) </li></ul><ul><ul><li>External controller remembers last refreshed row </li></ul></ul><ul><li>Some memory chips maintain refresh row pointer </li></ul><ul><ul><li>CAS before RAS refresh: if CAS goes low before RAS, then refresh </li></ul></ul>
  12. 12. DRAM Technologies <ul><li>Conventional DRAM </li></ul><ul><li>Fast Page Mode (FPM) DRAM </li></ul><ul><li>Extended Data Out (EDO) DRAM </li></ul><ul><li>Synchronous DRAM (SDRAM) </li></ul><ul><li>Double Data Rate SDRAM (DDR SDRAM) </li></ul><ul><li>Direct Rambus DRAM (DRDRAM) </li></ul><ul><li>Synchronous-Link DRAM (SLDRAM) </li></ul>
  13. 13. Fast Page Mode (FPM) DRAM <ul><li>Sending the row address just once for many accesses to memory in locations near each other, improving access time </li></ul><ul><ul><li>Page mode </li></ul></ul><ul><li>Burst mode access </li></ul><ul><ul><li>Memory is not read one byte at a time (32 or 64 bits at a time) </li></ul></ul><ul><ul><li>Several consecutive chunks of memory </li></ul></ul><ul><ul><li>“ x-y-y-y” for four consecutive accesses </li></ul></ul>
  14. 14. Example: Samsung 1Mx16 FPM DRAM <ul><li>Power : 5V or 3.3 V, 450-500 mW </li></ul><ul><li>Access time : 50ns, 60ns </li></ul>
  15. 17. EDO DRAM: Samsung 1Mx16bit
  16. 19. Synchronous DRAM <ul><li>Tied to the system clock </li></ul><ul><li>Burst mode </li></ul><ul><ul><li>System timing : 5-1-1-1 </li></ul></ul><ul><ul><li>Internal interleaving </li></ul></ul><ul><li>New memory standard for modern PCs </li></ul><ul><li>Speed </li></ul><ul><ul><li>Access time: 10ns, 12ns,… </li></ul></ul><ul><ul><li>MHz rating: 100 MHz, 133MHz </li></ul></ul>
  17. 20. Synchronous DRAM, cont’d <ul><li>Latency </li></ul><ul><ul><li>SDRAMs are still DRAMs </li></ul></ul><ul><ul><li>5-1-1-1 (10ns means the second, third and fourth access times) </li></ul></ul><ul><li>2-clock and 4-clock Circuitry </li></ul><ul><ul><li>2-clock: 2 different DRAM chips on the module </li></ul></ul><ul><ul><li>4-clock: 4 different DRAM chips </li></ul></ul><ul><li>Packaging </li></ul><ul><ul><li>Usually comes in DIMM packaging </li></ul></ul><ul><ul><li>Buffered and unbuffered, 3.3 V and 5.0V </li></ul></ul>
  18. 21. Samsung 8Mx8bitx4 banks synchronous DRAM
  19. 24. SDRAM DIMM <ul><li>64Mx64 SDRAM DIMM based on 32Mx8, 4 banks 3.3v SDRAMs with SPD </li></ul><ul><ul><li>SPD: serial presence detect chip: speed and design information about the module </li></ul></ul>
  20. 26. Direct Rambus DRAM (DRDRAM) <ul><li>Direct Rambus channel </li></ul><ul><ul><li>High speed 16-bit bus, 400MHz </li></ul></ul><ul><ul><li>Transfers at rising and falling edges, 1.6Gbytes/second </li></ul></ul><ul><ul><li>Rambus Inline Memory module (RIMM) </li></ul></ul>
  21. 27. Samsung 256/288Mbit RDRAM <ul><li>512K x 16/18 x 32s banks </li></ul><ul><li>Mobile, graphics, and large memory systems </li></ul><ul><li>Low latency </li></ul><ul><li>Advanced power management </li></ul>
  22. 29. Synchronous-Link DRAM (SLDRAM) <ul><li>SLDRAM Consortium </li></ul><ul><ul><li>Evolutionary design </li></ul></ul><ul><ul><li>64bit bus running at a 200 MHz clock speed (effective speed of 400 MHz) </li></ul></ul><ul><ul><li>3.2 Gbytes/second </li></ul></ul><ul><ul><li>Open standard </li></ul></ul>
  23. 30. Comparison of semiconductor memories * 0.4 mm design rule 30/0.1 (mA) 10 4 ~10 5 0.8s 6.4 (  s) 50/100 (ns) 0.42 257 1.7 4Mx16b 64M Flash 70/ (mA) - 14 (ns) 14/33 (ns) 0.59 226 8.4 2Mx8b 16M SRAM 85/ (mA) - 100 (ns) 38/100 (ns) 0.52 211 1.7 8Mx8b 8k ref 64M DRAM Power consumption (Act./Stdby) Write 횟수 Erase time Write cycle Real Access/ cycle Cell 효율 (%) Chip size (mm 2 ) Cell size (mm 2 ) Bit org.

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