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Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device ...


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Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device ...

  1. 1. Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 83∼86 Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device Built on a Bulk Si Wafer Il Hwan Cho,∗ Byung Gook Park and Jong Duk Lee School of Electrical Engineering & Computer Science, Seoul National University, Seoul 151-742 Tai-su Park School of Materials Science and Engineering, Seoul National University, Seoul 151-742 Si Young Choi Semiconductor R&D Center, Samsung Electronics Co., Ltd., Yongin 449-711 Jong Ho Lee School of Electrical Engineering, Kyungpook National University, Daegu 702-701 (Received 7 August 2003) A new SONOS memory structure was proposed to solve the scaling-down problems of conventional flash memories. The proposed SONOS flash memory devices which has a body-tied fin MOSFET structure, was fabricated using a bulk Si wafer and was characterized. The proposed devices show a reduced short-channel effect than conventional devices. The Fowler-Nordheim programming char- acteristics, the channel hot-electron injection programming characteristics, and the leakage-current characteristics of the body-tied double-gate flash memory device are shown. PACS numbers: 85.30.De Keywords: Semiconductor-device characterization, Design and modeling (Nano-Science & Technology) I. INTRODUCTION In this paper, for the first time, a body-tied double- gate SONOS flash memory device using a bulk Si wafer is proposed. Brief fabrication steps and measured charac- A SONOS (silicon-oxide-nitride-oxide-silicon) flash teristics are presented. Since the body shape resembles memory device is considered as a promising candidate the Greek letter Omega (Ω), we call the memory device to implement a low-voltage and high-density nonvolatile an Ω flash memory. semiconductor memory (NVSM). The SONOS memory device has better scaling-down characteristics than a conventional flash memory device having a poly-Si stor- II. EXPERIMENT age node, because the total equivalent gate oxide thick- ness of the SONOS devices is much thinner than that of a conventional memory [1]. Recently, double-gate MOS- The schematic cross-section of the fabricated Ω flash FETs (for example, FinFETs) have been considered as memory device is shown in Fig. 1(a). The body of the the most promising candidates for nano-scale CMOS de- device is directly connected to the Si substrate. The gate vices [2]. Among them, the FinFET is one of the promis- dielectric stack is consisted of oxide-nitride-oxide (ONO) ing candidates due to its simple structure and process as shown in the magnified view, and the thicknesses for compatibility with conventional CMOS technology. All the ONO are 1 nm, 4 nm, and 2 nm in the fabricated FinFETs ever reported have been implemented on SOI samples, respectively. wafers, which have demerits in terms of wafer cost and Processes to fabricate the device can be explained defect density. Moreover, memory devices fabricated on briefly as follows: On p-type (100) wafers, a 0.12-µm SOI wafers suffer from possible floating-body effects and design-rule KrF photo lithography step was performed heat-accumulation problems. to define the active regions. After the silicon has been etched to a reasonable depth to form trenches, a layer of ∗; oxide was grown and completely etched in a diluted HF Tel: +82-2-880-7282; Fax: +82-2-882-4658 solution, leaving thin fins standing vertically in which the -83-
  2. 2. -84- Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004 Fig. 3. ID -VDS characteristics of the Ω SONOS flash mem- Fig. 1. Bird’s eye view of the body-tied fin double-gate ory. SONOS flash memory (Ω SONOS flash memory device). The structure inside the circle stands for the ONO stack. Fig. 2. SEM view showing the fin and the body structures after CMP and the SiN etch-back. channel and the source/drain were formed. Formation of the thin oxide was following by a SiN-layer deposition, and the unfilled trenches were filled with SiO2 deposited by HDP CVD. CMP process was performed until the SiN layer was opened. As shown in Fig. 2, the top portion of the SiN layer was etched in a phosphoric acid solu- tion, and ion implantation steps for well fabrication and channel doping were performed. The SiN layer was additionally recessed to a depth of 90 nm and fin sidewalls were opened. After the thin Fig. 4. ID -VGS characteristics of the Ω and the conven- SiO2 has been removed, 2-nm tunneling-gate SiO2 and tional SONOS flash memory devices. (a) ID -VGS character- 4-nm SiN were grown in sequence, followed by the forma- istics of an Ω SONOS flash memory and (b) ID -VGS charac- tion of an oxide layer about 1-nm thick, then, an in-situ teristics of a planar SONOS flash memory. phosphorous doped poly-Si and a SiN mask layer were deposited. Gate electrodes were patterned by using the 0.12-µm design-rule KrF photo lithography and etching. After P+ ison, conventional planar-channel SONOS memory de- (or B+ for PMOS) ions for (LDD) had been implanted, vices were fabricated with the same ONO stack. The an SiN spacer was formed, and ion implantations were rest of the process steps were the same as those in the performed to dope the source/drain regions. For compar- conventional CMOS fabrication process.
  3. 3. Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device· · · – Il Hwan Cho et al. -85- Fig. 5. Fowler-Nordheim (FN) program characteristics of Fig. 6. Channel hot electron (CHE) program characteris- an Ω SONOS flash memory device: (a) FN program char- tics of an Ω SONOS flash memory: (a) CHE program charac- acteristics as a parameter of the program time when pro- teristics of an Ω SONOS flash memory device as a parameter grammed with 10 V and (b) VT H characteristics of an Ω of the program time when programmed with VGS = 3 V and SONOS flash memory device by FN programming with VGS VDS = 5 V and (b) VT H characteristics of an Ω SONOS flash = 8 V and VGS = 10 V. memory device and a conventional one by CHE programming with VGS = 3 V and VDS = 5 V. III. RESULTS AND DISCUSSION programming voltages are relatively long because the top Fig. 3 shows the reasonable ID -VDS characteristics oxide in the ONO structure is so thin that during the pro- of the fabricated 120-nm Ω flash memory devices. Fig. gramming part of the electrons from the channel, go to 4 shows ID -VGS curves of the proposed device and of the gate electrode by tunneling the top oxide. Thus, the the conventional planar-channel device. In Fig. 4(a), top oxide should be at least thicker than that of the bot- the drain-induced barrier lowering (DIBL) is about 12 tom (tunneling) oxide to make the program/erase times mV/V, and the subthreshold swing (SS) is about 84 faster. If the FN program voltage is to be lowered, the mV/dec for the Ω SONOS with an LG of 120 nm. In Fig. thickness of the ONO layer should be optimized [4]. 3(b), the conventional device with an LG of 280 nm shows Fig. 6(a) shows Ω flash memory program characteris- a DIBL of 54 mV/V and SS of 96 mV/dec. The 120-nm tics due to CHE injection as a parameter of the program Ω flash memory device shows a better short-channel ef- time at a given VGS = 3 V and VDS = 5 V. In the CHE fect than the 280-nm planar-channel flash device. These program mode, the subthreshold slope of programmed results show same trend as device simulation results [3]. cell deteriorates as in the case of FN programming. In Therefore, the proposed Ω structure MOSFET has great Fig. 6(b), the programming characteristics of 180-nm potential for device scaling-down in high-density non- Ω and 280-nm conventional SONOS memory devices at volatile memories. VGS = 3 V and VDS = 5 V are shown. The character- Fig. 5 shows the Fowler-Nordheim (FN) program char- istics of both devices need to be compared at the same acteristics of 120-nm Ω flash memory devices. In Fig. gate length. If a ∆VT H of 2 V for the Ω flash device 5(a), the ID -VGS characteristics as a parameter of the when programmed with VGS = 3 V and VDS = 5 V program time are shown. VT H versus the program time is to be obtained , a 1 ms program time is needed. To is shown in Fig. 5(b) for various program voltages. For improve the CHE program characteristics, we need to a ∆VT H of 2 V, a program time of 200 ms when pro- improve the ONO stack and to modify the CHE pro- grammed with a VGS of 8 V is estimated. With a VGS gram method. We think a 1-nm top-oxide thickness in of 10 V, 0.2 ms is needed. These program times for both the ONO stack is too thin and needs to be increased.
  4. 4. -86- Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004 We have proposed, for the first time, double-gate SONOS flash memory MOS devices (so-called Ω flash devices) based on a body-tied fin MOS structure, and the characterized them. The proposed Ω flash memory device was implemented on a bulk Si wafer instead of a SOI wafer and shows better scalability. The Ω flash memory MOSFET is expected to be a very promising candidate for a future high-density flash devices. ACKNOWLEDGMENTS Fig. 7. Iof f characteristics of an Ω SONOS flash memory This work was supported by the Tera-level Nanode- (LG of 120 nm) and a planar SONOS flash memory (LG of vices Project of the Korea Ministry of Science and Tech- 280 nm) with initial state. nology in 2002. Fig. 7 shows Iof f (ID @ VGS = 0 V) versus VDS as a parameter of the device structure at the initial state. The REFERENCES Ω flash device shows a lower Iof f than the conventional planar-memory device with a longer gate length. The leakage current for the Ω flash memory device is about [1] Byungcheul Kim, Sang-Bae Yi and Kwang-Yell Seo, J. 1 pA even at a supply voltage of about 5 V. Hence, for Korean Phys. Soc. 41, 945 (2002). a bit line having 1 k memory cells, the combined leak- [2] D. Hisamoto, Wen-Chin, Jakub Kedzierski, Hideki age current is at most 1 nA. The conventional planar Takeuchi, Kazuya Asamo, Charles Kuo, Erik Anderson, channel-device shows a significant Iof f increase when the Tsu-Jae King, Jeffrey Bokor and Chenming Hu, IEEE VDS is larger than 3.5 V. Electron Dev. 47, 2320 (2000). [3] I. H. Cho, B. G. Park, J. D. Lee and J. H. Lee, J. Korean Phys. Soc. 40, 233 (2002). [4] Byungcheul Kim, Sang-Eun Lee and Kwang-Well Seo, J. IV. CONCLUSIONS Korean Phys. Soc. 40, 644 (2002).