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AVR Microcontroller Family Assembly Language Programming


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AVR Microcontroller Family Assembly Language Programming

  1. 1. AVR Microcontroller Family Assembly Language Programming University of Akron Dr. Tim Margush
  2. 2. AVR <ul><li>Atmel AVR 8-Bit Processors come in a variety of configurations and packages </li></ul><ul><ul><li>They all share a common core – registers, instructions, basic I/O capabilities </li></ul></ul><ul><li>Our focus is the ATMega16 </li></ul>
  3. 3. ATMega16 Specs <ul><li>131 Instructions </li></ul><ul><li>32 8-bit GP registers </li></ul><ul><li>Throughput up to 16 MIPS </li></ul><ul><li>16K programmable flash (instructions) </li></ul><ul><li>512Bytes EEPROM </li></ul><ul><li>1K internal SRAM </li></ul><ul><li>Timers, serial and parallel I/O, ADC </li></ul>
  4. 4. AVR CPU <ul><li>PC: address of next instruction </li></ul><ul><li>IR: prefetched instruction </li></ul><ul><li>ID: current instruction </li></ul><ul><li>GPR: R0-R31 </li></ul><ul><li>ALU: Note internal data path </li></ul>
  5. 5. AVR Memory <ul><li>Flash: Machine instructions go here </li></ul><ul><li>SRAM: For runtime data </li></ul><ul><ul><li>Note bus independence for data and instructions </li></ul></ul><ul><li>EEPROM: Secondary storage </li></ul><ul><ul><li>EEPROM and Flash memories have a limited lifetime of erase/write cycles </li></ul></ul>
  6. 6. Flash Memory <ul><li>Programs reside in word addressable flash storage </li></ul><ul><ul><li>Word addresses range from 0000-1FFF (PC is 13 bits) </li></ul></ul><ul><ul><li>Byte addresses range 0000-3FFF (0x4000=16K) </li></ul></ul><ul><li>Harvard Architecture </li></ul><ul><ul><li>It is possible to use this storage area for constant data as well as instructions, violating the true spirit of this architecture </li></ul></ul><ul><li>Instructions are 16 or 32-bits </li></ul><ul><ul><li>Most are 16-bits and are executed in a single clock cycle </li></ul></ul>
  7. 7. SRAM <ul><li>The ATMega16 has 1K (1024 bytes) of byte addressable static RAM </li></ul><ul><ul><li>This is used for variable storage and stack space during execution </li></ul></ul><ul><ul><li>SRAM addresses start at $0060 and go through $045F </li></ul></ul><ul><ul><ul><li>The reason for not starting at zero will be covered later </li></ul></ul></ul>
  8. 8. EEPROM <ul><li>Electrically Erasable Programmable Read Only Memory </li></ul><ul><ul><li>Programs can read or write individual bytes </li></ul></ul><ul><ul><li>This memory is preserved when power is removed </li></ul></ul><ul><ul><li>Access is somewhat slow; it serves as a form of secondary storage </li></ul></ul>
  9. 9. Clock <ul><li>All processors are pushed through their fetch execute cycle by an alternating 0-1 signal, called a clock </li></ul><ul><li>The ATMega16 can use an internal or external clock signal </li></ul><ul><ul><li>Clock signals are usually generated by an RC oscillator or a crystal </li></ul></ul><ul><ul><ul><li>The internal clock is an RC oscillator programmable to 1, 2, 4, or 8 MHz </li></ul></ul></ul><ul><ul><ul><li>An external clock signal (crystal controlled) can be more precise for time critical applications </li></ul></ul></ul>
  10. 10. AVR Machine Language <ul><li>AVR instructions are 16 or 32-bits </li></ul><ul><li>Each instruction contains an opcode </li></ul><ul><ul><li>Opcodes generally are located in the initial bits of an instruction </li></ul></ul><ul><li>Some instructions have operands encoded in the remaining bits </li></ul><ul><ul><li>Opcode and operands are numbers, but their containers are simply some of the bits in the instruction </li></ul></ul>
  11. 11. Load Immediate <ul><li>LDI Rd, K </li></ul><ul><ul><li>Load a constant into a register (Rd = K) </li></ul></ul><ul><ul><li>1110 bbbb rrrr bbbb </li></ul></ul><ul><ul><ul><li>Limitations: 16 <= d <= 31; 0x00 <= K <= 0xFF </li></ul></ul></ul><ul><ul><li>Opcode is 1110 </li></ul></ul><ul><ul><li>The register number is coded in bits 7-4 </li></ul></ul><ul><ul><ul><li>Only the last 4 bits of the register number are present; a leading 1 is assumed (1rrrr) </li></ul></ul></ul><ul><ul><li>The constant is split into two nybbles </li></ul></ul>
  12. 12. LDI Examples <ul><li>LDI R16, $2C </li></ul><ul><ul><li>1110 0010 0000 1100 or 0xE20C </li></ul></ul><ul><li>LDI R27, $0F </li></ul><ul><ul><li>27 is 11011 </li></ul></ul><ul><ul><li>1110 0000 1011 1111 or 0xE0BF </li></ul></ul><ul><li>Note that this instruction always </li></ul><ul><ul><li>starts with E, </li></ul></ul><ul><ul><li>has the two nybbles of K at positions 2 and 0, </li></ul></ul><ul><ul><li>and encodes the register in nybble 1 </li></ul></ul>
  13. 13. Add Registers <ul><li>ADD Rd, Rr </li></ul><ul><ul><li>Add the contents of two registers, store result in Rd (Rd = Rd + Rr) </li></ul></ul><ul><ul><li>0000 11rd dddd rrrr </li></ul></ul><ul><ul><ul><li>Any registers: 0 <= r <= 31; 0 <= d <= 31 </li></ul></ul></ul><ul><ul><li>The opcode is 000011 </li></ul></ul><ul><ul><li>The register numbers are coded in binary </li></ul></ul><ul><ul><ul><li>Rr has its high bit split off from the others </li></ul></ul></ul>
  14. 14. ADD Examples <ul><li>ADD R16, R3 </li></ul><ul><ul><li>ddddd is 10000 and rrrrr is 00011 </li></ul></ul><ul><ul><li>0000 1101 0000 0011 or 0x0D03 </li></ul></ul><ul><li>ADD R27, R17 </li></ul><ul><ul><li>ddddd is 11011, rrrrr is 10001 </li></ul></ul><ul><ul><li>0000 1111 1011 0001 or 0x0FB1 </li></ul></ul><ul><li>Note that this instruction always </li></ul><ul><ul><li>starts with 0, </li></ul></ul><ul><ul><li>followed by C, D, E, or F </li></ul></ul><ul><ul><li>and can have any values in the second byte </li></ul></ul>
  15. 15. Expanding Opcodes <ul><li>The following are not legal opcodes </li></ul><ul><ul><li>1, 11, 111 </li></ul></ul><ul><li>No opcode longer than 4 bits starts 1110 </li></ul><ul><ul><li>Except ser Rd </li></ul></ul><ul><ul><li>1110 1111 dddd 1111 </li></ul></ul><ul><li>Similarly, no prefix of 000011 is an opcode and no opcode longer than 6 begins with this sequence </li></ul><ul><ul><li>Except lsl Rd </li></ul></ul><ul><ul><li>0000 11dd dddd dddd </li></ul></ul>LDI: 1110 011110110011 ADD: 000011 1100101101 How does the processor &quot;know&quot; where the opcode portion stops?
  16. 16. A Machine Language Program <ul><li>Load program into memory </li></ul><ul><ul><li>At address 0 we place the word $E20C </li></ul></ul><ul><ul><li>At address 1 we place the word $E01F </li></ul></ul><ul><ul><li>At address 2 we place the word $0F01 </li></ul></ul><ul><li>Execute the three instructions in sequence </li></ul><ul><ul><li>Set PC to 0 and perform 3 fetch-execute cycles </li></ul></ul><ul><li>Observe result </li></ul><ul><ul><li>R16 has the sum of $2C and $0F, $3B </li></ul></ul>
  17. 17. A Machine Language Program <ul><li>0000: $E20C LDI R16, $2C </li></ul><ul><li>0001: $E01F LDI R17, $0F </li></ul><ul><li>0002: $0F01 ADD R16, R17 </li></ul><ul><li>R16 = R16 + R17 </li></ul><ul><li>= $2C + $0F </li></ul><ul><li>= $3B </li></ul>
  18. 18. AVR Studio <ul><li>An integrated development environment </li></ul><ul><ul><li>Provides a text editor </li></ul></ul><ul><ul><li>Supports the AVR assembler </li></ul></ul><ul><ul><li>Supports the gnu C compiler </li></ul></ul><ul><ul><li>Provides an AVR simulator and debugger </li></ul></ul><ul><ul><li>Provides programming support for the AVR processors via serial interface </li></ul></ul>
  19. 19. AVR Studio: New Project <ul><li>Start AVR Studio </li></ul><ul><li>Click New Project </li></ul><ul><li>Select type: Assembler </li></ul><ul><li>Choose a project name </li></ul><ul><li>Select create options and pick a location </li></ul><ul><li>Location should be a folder to hold all project folders </li></ul><ul><li>Each project should be in its own folder </li></ul>
  20. 20. AVR Studio: New Project <ul><li>On the next dialog, select the Debug platform: AVR Simulator </li></ul><ul><li>Pick the device type: ATMega16 </li></ul><ul><li>Finish </li></ul>
  21. 21. AVR Studio: Interface <ul><li>Enter the program in the assembly source file that is opened for you. </li></ul><ul><li>Click the Assemble button (F7) </li></ul>Assemble Workspace Output Editor
  22. 22. AVR Studio: Assembler Report <ul><li>Assembler summary indicates success </li></ul><ul><ul><li>6 bytes of code, no data, no errors </li></ul></ul>
  23. 23. AVR Studio: Debugger <ul><li>Start the debugging session </li></ul><ul><ul><li>Click Start Debugging </li></ul></ul><ul><ul><li>Next instruction is shown with yellow arrow </li></ul></ul><ul><li>Choose I/O View </li></ul><ul><ul><li>View registers 16-17 </li></ul></ul><ul><li>Step through program </li></ul><ul><ul><li>F10 is Step Over </li></ul></ul>Start Debugging
  24. 24. AVR Studio: Debugger <ul><li>The first 2 instructions are completed </li></ul><ul><ul><li>R16 and R17 have the expected values from the LDI instructions </li></ul></ul><ul><li>The sum is placed in R16 </li></ul><ul><ul><li>$3B is the sum </li></ul></ul>
  25. 25. AVR Studio: Memory <ul><li>Memory contents may be viewed (and edited) during debugging </li></ul><ul><ul><li>You can view program (flash), data (SRAM), or EEPROM memory </li></ul></ul><ul><ul><li>You can also view the general purpose and I/O registers using this tool </li></ul></ul>The Program
  26. 26. Using Mnemonics <ul><li>Rather than code the machine language program as a sequence of numeric word values expressed in hexadecimal, assembly language programmers usually use instruction mnemonics </li></ul><ul><li>This program will assemble and run identically to the first </li></ul><ul><ul><li>ldi R16, $2C </li></ul></ul><ul><ul><li>ldi R17, $0F </li></ul></ul><ul><ul><li>add R16, R17 </li></ul></ul>
  27. 27. What's Next? <ul><li>In our sample program, we executed three instructions, what comes next? </li></ul><ul><ul><li>Undefined! Depends on what is in flash </li></ul></ul><ul><li>How do we terminate a program? </li></ul><ul><ul><li>Use a loop! </li></ul></ul><ul><li>0000: $E20C LDI R16, $2C </li></ul><ul><li>0001: $E01F LDI R17, $0F </li></ul><ul><li>0002: $0F01 ADD R16, R17 </li></ul><ul><li>0003: $???? ??? </li></ul><ul><li>If a program is to simply stop, add an instruction that jumps to its own address </li></ul>
  28. 28. Relative Jump <ul><li>RJMP K 1100 kkkk kkkk kkkk </li></ul><ul><ul><li>-2048 <= K < 2048 </li></ul></ul><ul><li>According to the manufacturer specifications, this instruction causes this action: </li></ul><ul><ul><li>PC = PC + 1 + K </li></ul></ul><ul><li>We want K = -1 </li></ul><ul><ul><li>This will cause a jump to the address from which the instruction was fetched </li></ul></ul>
  29. 29. Relative Jump <ul><li>Here: RJMP Here 1100 kkkk kkkk kkkk </li></ul><ul><ul><li>K = -1 ($FFF) </li></ul></ul><ul><ul><li>1100 1111 1111 1111 or $CFFF </li></ul></ul><ul><li>0000: $E20C LDI R16, $2C </li></ul><ul><li>0001: $E01F LDI R17, $0F </li></ul><ul><li>0002: $0F01 ADD R16, R17 </li></ul><ul><li>0003: $CFFF RJMP -1 </li></ul><ul><li>0004: $???? ??? </li></ul>This distance is -1 word Remember that the program counter is incremented before the instruction is executed