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Intel core i3, i5, i7 , core2 duo and atom processors


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Intel core i3, i5, i7 , core2 duo and atom processors

  1. 1. Introduction to recent IntelProcessor Microarchitecture andBrand Processor FamiliesBy : Fady Morris MiladMay 25, 2013
  2. 2. What aspects will we compareprocessors according to ?• Instruction Set Architecture(ISA) :is the part of the computer architecture related to programming,including the native data types, instructions, registers, addressingmodes, memory architecture, interrupt and exception handling,and external I/O. An ISA includes a specification of the set ofopcodes (machine language), and the native commandsimplemented by a particular processor.Example : x86, x86-64, MMX• Microarchitecture :the way a given instruction set architecture (ISA) is implemented on aprocessorexamples : P6, NetBurst, Core, Nehalem, Sandy Bridge
  3. 3. What aspects will we compareprocessors according to ?• Marketing Names :Example : Pentium, Core2Duo, Core i3, i5, i7• Fabrication Process :65nm, 45nm, 32nm, 22nm
  4. 4. Roadmap of Intel Microarchitecture :
  5. 5. Roadmap of Intel Microarchitecture• "Tick-Tock" is a model adopted by chip manufacturer IntelCorporation since 2007 to follow every microarchitecturalchange with a die shrink of the process technology.• Every "tick" is a shrinking of process technology of theprevious microarchitecture• Every "tock" is a new microarchitecture.• Every year, there is expected to be one tick or tock.
  6. 6. Architectural change Fabrication process Microarchitecture Codename Release dateProcessorsMarketing namesTick Die shrink65 nmP6, NetBurstPresler, CedarMill, YonahJanuary 5, 2006 Core Pentium 4 Pentium D Pentium M Pentium Dual-Core CeleronTockNewmicroarchitectureCoreConroe July 27, 2006[2]  Core 2 Pentium Dual-Core Pentium Celeron Dual-Core Celeron Celeron MTick Die shrink45 nmPenryn November 11, 2007[3]TockNewmicroarchitecture NehalemNehalem November 17, 2008[4] Core i3 Core i5 Core i7 Pentium Celeron XeonTick Die shrink32 nmWestmere January 4, 2010[5][6]TockNewmicroarchitectureSandy BridgeSandy Bridge January 9, 2011[7]Tick Die shrink22 nmIvy Bridge April 29, 2012TockNewmicroarchitectureHaswell Haswell June 2nd 2013
  7. 7. The Core Microarchitecture• Example Processors : Core 2 Duo• First Released : July 27, 2006• designed from ground up, but is similar to the Pentium Mmicroarchitecture in design philosophy.• The power consumption of these new processors is extremelylow• new technology included in the design is Macro-Ops Fusion,which combines two x86 instructions into a single micro-operation• This architecture is a dual core design with linked L1 cacheand shared L2 cache• No Hyperthreading
  8. 8. Nehalem Microarchitecture• Used in Core i3, i5, i7 Processors(1st Generation)• released : November 17, 2008• Some Features :– An important change is the enlargement of the L2-cache by 50% compared with Meromprocessors. This means a L2-cache of 3 respectively 6 megabytes. Since this increases theamount of data available for quick processing by the CPU, it is probably the most importantadvantage of the Penryn architecture for most users and mainly responsible for the measuredperformance improvement.– Hyperthreading reintroduced– reduction in L2 cache size, as well as an enlarged L3 cache that is shared by all cores.– Intel QuickPath Interconnect in high-end models replacing the legacy front side bus– Integration of PCI Express and DMI into the processor in mid-range models, replacing thenorthbridge– Integrated memory controller supporting two or three memory channels of DDR3 SDRAM orfour FB-DIMM2 channels• Improvements over Core :– 10-25% more single-threaded performance / 20-100% more multithreaded performance atthe same power level– 30% lower power usage for the same performance– Nehalem provides a 15–20% clock-for-clock increase in performance per core(average)
  9. 9. Sandy Bridge Microarchitecture• Used in Core i3, i5, i7 Processors(Second Generation)• released : January 9, 2011• Upgraded features from Nehalem include:– 32 kB data + 32 kB instruction L1 cache and 256 kB L2 cache per core– Shared L3 cache includes the processor graphics (LGA 1155)– 64-byte cache line size– Decoded micro-operation cache and enlarged, optimized branch predictor– Improved performance for transcendental mathematics, AES encryption (AES instruction set), and SHA-1hashing– Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and richfunctionality– Intel Quick Sync Video, hardware support for video encoding and decoding– Up to 8 physical cores or 16 logical cores through Hyper-threading– Integration of the GMCH (integrated graphics and memory controller) and processor into a single die insidethe processor package. In contrast, Sandy Bridges predecessor, Clarkdale, has two separate dies (one forGMCH, one for processor) within the processor package. This further integration reduces memory latencyeven more.• Developed primarily by the Israel branch of Intel, the codename was originally "Gesher" (meaning"bridge" in Hebrew). The name was changed to avoid being associated with the defunct Gesherpolitical party
  10. 10. Ivy Bridge Microarchitecture• Used in Core i3, i5, i7 Processors(ThirdGeneration)• released : April 29, 2012• Features :– The Ivy Bridge CPU microarchitecture is a shrink fromSandy Bridge and remains largely unchanged.– die shrinking improvement(tick) – 22nmmanufacturing process– backward compatible with Sandy Bridge– Trigate Transistors (3D Transistors)
  11. 11. Ivy Bridge Microarchitecture(Continued)• Trigate Transistors(3D Transistors) :– allowing for essentially three times the surfacearea forelectrons to travel.– reduce leakage and consume far less power thancurrent transistors.– This allows up to 37% higher speed, or a powerconsumption at under 50% of the previous type oftransistors used by Intel– faster switching speed
  12. 12. Haswell Microarchitecture• Currently Under Development• Will be Used in Core i3, i5, i7Processors(Fourth Generation)• Will be released on June 4, 2013• Micoarchitecutre Improvement over “IvyBridge”
  13. 13. • Next we will discuss some of Intel BrandNames currently in the market such as :– Core 2 Duo– Core i Series(i3, i5, i7)– Intel Atom
  14. 14. Core 2 Duo• Core Microarchitecture family (codename penryn)• 2 cores on single die• 45nm Technology• An important change introduced is the enlargement ofthe L2-cache by 50% compared with previousprocessors. This means a L2-cache of 3 respectively 6megabytes. Since this increases the amount of dataavailable for quick processing by the CPU, it is probablythe most important advantage of the Penrynarchitecture for most users and mainly responsible forthe measured performance improvement.
  15. 15. Core i series• Core i3, i5, i7• Nehalem or Sandy Bridge MicroarchitectureBased• Different types of new Intel processors brands tosuit various user needs.– Core i3 : This processor is considered to be the lowend, budget processor– Core i5 processor : This is considered the mid-rangeand mainstream– Core i7 processors :are considered high endProcessors
  16. 16. Core i Seriesstar rating :• Their relative levels of processing power are alsosignified by their Intel Processor Star Ratings,which are based on a collection of criteriainvolving their number of cores, clockspeed (inGHz), size of cache, as well as some new Inteltechnologies like Turbo Boost and Hyper-Threading.• Core i3s are rated with three stars, i5s have fourstars, and i7s have five.
  17. 17. Core i seriesComparison between i3, i5, i7• We will compare i3, i5, i7 according to :– Number of Cores– Cache Sizes– Hyper Threading– Intel Turbo Boost Technology
  18. 18. Core i seriesComparison between i3, i5, i7• Number of Cores :– Core i3 : all of them are 2 cores– Core i5 : either 2 cores or 4 cores– Core i7 : All of them are 4 cores• Cache Size :– Core i3 : All of them have 3 MB Cache– Core i5 : All of them have 6 MB Cache(Except forsome)– Core i7 : All of them have 8 MB Cache
  19. 19. Core i seriesComparison between i3, i5, i7Hyper-Threading• Intel has introduced a technology called Hyper-Threading. This enables a singlecore to serve multiple threads.• The main function of hyper-threading is to decrease the number of dependentinstructions on the pipeline.• Hyper-threading works by duplicating certain sections of the processor—thosethat store the architectural state—but not duplicating the main executionresources. This allows a hyper-threading processor to appear as the usual"physical" processor and an extra "logical" processor to the host operating system• core i3, i5 , and i7 all of them have hyper threading• The number of threads is double the number of cores :– Core i3 : 2 Cores  4 Threads– Core i5 :• Either 2 Cores That support Hyper Threading  4 Threads• or 4 Cores( True 4 Cores models don’t support Hyper Threading)  The Total number of Threads is 4too– Core i7 : 4 cores  8 Threads
  20. 20. Core i seriesComparison between i3, i5, i7Intel Turbo Boost Technlogy• The Intel Turbo Boost Technology allows a processor todynamically increase its clockspeed whenever the needarises. The maximum amount that Turbo Boost canraise clockspeed at any given time is dependent on thenumber of active cores, the estimated currentconsumption, the estimated power consumption, andthe processor temperature.• none of the Core i3 CPUs have Turbo Boost• All Core i5 and Core i7 are equipped with Turbo BoostTechnology
  21. 21. Intel Atom• ultra-low-voltage IA-32 and Intel 64 (x86-64) CPUs• originally designed in 45 nm CMOS with subsequent models, codenamedCedar, using a 32 nm process• Atom is mainly used in netbooks, nettops, embedded applications rangingfrom health care to advanced robotics, and mobile Internet devices(MIDs).• All Atom processors implement the x86 (IA-32) instruction set• Atom processors are based on the Bonnell microarchitecture• Bonnell Microarcitecture : is a CPU microarchitecture used byIntel Atom processors which can execute up to two instructions per cycle• Feature 16 pipleline stages• The Bonnell microarchitecture represents a partial revival of the principlesused in earlier Intel designs such as P5 and the i486, with the sole purposeof enhancing the performance per watt ratio