6 Switch Fabric

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6 Switch Fabric

  1. 1. Switching - Fabric An Engineering Approach to Computer Networking
  2. 2. Switching Number of connections: from few (4 or 8) to huge (100K)
  3. 3. Switching - Basic Assumptions <ul><li>continuous streams </li></ul><ul><li>telephone connections </li></ul><ul><ul><li>no bursts </li></ul></ul><ul><ul><li>no buffers </li></ul></ul><ul><li>connections change </li></ul><ul><li>multicast </li></ul><ul><li>Blocking </li></ul><ul><ul><li>external </li></ul></ul><ul><ul><li>internal </li></ul></ul><ul><ul><ul><li>re-arrangeable </li></ul></ul></ul><ul><ul><ul><li>strict sense non-blocking </li></ul></ul></ul><ul><ul><ul><li>wide sense non-blocking </li></ul></ul></ul>
  4. 4. Multiplexors and demultiplexors <ul><li>Multiplexor: aggregates sessions </li></ul><ul><ul><li>N input lines </li></ul></ul><ul><ul><li>Output runs N times as fast as input </li></ul></ul><ul><li>Demultiplexor: distributes sessions </li></ul><ul><ul><li>one input line and N outputs that run N times slower </li></ul></ul><ul><li>Can cascade multiplexors </li></ul>
  5. 5. Time division switching <ul><li>Key idea: when demultiplexing, position in frame determines output limk </li></ul><ul><li>Time division switching interchanges sample position within a frame: time slot interchange (TSI) </li></ul>
  6. 6. Example - TSI sessions: (1,2) (2,4) (3,1) (4,3) 4 3 2 1 2 4 1 3 TSI
  7. 7. TSI <ul><li>Simple to build. </li></ul><ul><li>Multicast </li></ul><ul><li>Limit is the time taken to read and write to memory </li></ul><ul><li>For 120,000 circuits </li></ul><ul><ul><li>need to read and write memory once every 125 microseconds </li></ul></ul><ul><ul><li>each operation takes around 0.5 ns => impossible with current technology </li></ul></ul><ul><li>Need to look to other techniques </li></ul>
  8. 8. Space division switching <ul><li>Each sample takes a different path through the switch, depending on its destination </li></ul>
  9. 9. Crossbar <ul><li>Simplest possible space-division switch </li></ul><ul><li>Crosspoints can be turned on or off </li></ul>
  10. 10. Crossbar - example 1 2 3 4 1 2 3 4 sessions: (1,2) (2,4) (3,1) (4,3)
  11. 11. Crossbar <ul><li>Advantages: </li></ul><ul><ul><li>simple to implement </li></ul></ul><ul><ul><li>simple control </li></ul></ul><ul><ul><li>strict sense non-blocking </li></ul></ul><ul><li>Drawbacks </li></ul><ul><ul><li>number of crosspoints, N 2 </li></ul></ul><ul><ul><li>large VLSI space </li></ul></ul><ul><ul><li>vulnerable to single faults </li></ul></ul>
  12. 12. Time-space switching <ul><li>Precede each input trunk in a crossbar with a TSI </li></ul><ul><li>Delay samples so that they arrive at the right time for the space division switch’s schedule </li></ul>2 1 4 3 MUX MUX 1 2 3 4
  13. 13. Time-Space: Example 2 1 3 4 2 1 4 3 TSI 3 1 2 4 Internal speed = double link speed time 1 time 2
  14. 14. Finding the schedule <ul><li>Build a graph </li></ul><ul><ul><li>nodes - input links </li></ul></ul><ul><ul><li>session connects an input and output nodes. </li></ul></ul><ul><li>Feasible schedule </li></ul><ul><li>Computing a schedule </li></ul><ul><ul><li>compute perfect matching. </li></ul></ul>
  15. 15. Time-space-time (TST) switching <ul><li>Allowed to flip samples both on input and output trunk </li></ul><ul><li>Gives more flexibility => lowers call blocking probability </li></ul>
  16. 16. Circuit switching - Space division <ul><li>graph representation </li></ul><ul><ul><li>transmitter nodes </li></ul></ul><ul><ul><li>receiver nodes </li></ul></ul><ul><ul><li>internal nodes </li></ul></ul><ul><li>Feasible schedule </li></ul><ul><ul><li>edge disjoint paths. </li></ul></ul><ul><li>cost function </li></ul><ul><ul><li>number of crosspoints </li></ul></ul><ul><ul><li>internal nodes </li></ul></ul>
  17. 17. Example sessions: (1,3) (2,6) (3,1) (4,4) (5,2) (6,5)
  18. 18. Clos Network Clos(N, n , k) N - inputs/outputs; nxk ( N/n)x(N/n) kxn N=6 n=2 k=2 3 x3 3 x3 2 x2 2 x2 2 x2 2 x2 2 x2 2 x2
  19. 19. Clos Network - strict sense non-blocking <ul><li>Holds for k >= 2n-1 </li></ul><ul><li>Proof: </li></ul><ul><ul><li>Consider and idle input and output </li></ul></ul><ul><ul><li>Input box connected to at most n-1 middle layer switches </li></ul></ul><ul><ul><li>output box connected to at most n-1 middle layer switches </li></ul></ul><ul><ul><li>There exists a &quot;free&quot; middle switch. </li></ul></ul>
  20. 20. Proof
  21. 21. Example Clos(8,2,3) N=8 n=2 k=3 4 x4 4 x4 3 x2 3 x2 3 x2 2 x3 2 x3 2 x3 2 x3 4 x4 3 x2
  22. 22. Clos Network - rearrangable <ul><li>Holds for k >= n </li></ul><ul><li>Proof: </li></ul><ul><ul><li>Consider all input and output </li></ul></ul><ul><ul><li>find a perfect matching. </li></ul></ul><ul><ul><li>route the perfect matching </li></ul></ul><ul><ul><li>remaining network is Clos(N-n,n-1,k-1) </li></ul></ul><ul><li>summary: </li></ul><ul><ul><li>smaller circuit </li></ul></ul><ul><ul><li>weaker guarantee </li></ul></ul><ul><li>Mulicast ? </li></ul>
  23. 23. Recursive constructions - Benes Network N/2 x N/2 N/2 x N/2 1 n 1 n . . . . . .
  24. 24. Benes Networks <ul><li>Size: </li></ul><ul><ul><li>F(N) = 4N + 2F(N/2) = 4N log N </li></ul></ul><ul><li>Rearrangable </li></ul><ul><ul><li>Clos network with k=2 n=2 </li></ul></ul><ul><li>Symmetry </li></ul><ul><li>Example. </li></ul><ul><li>proof </li></ul>
  25. 25. Example 16x16
  26. 26. Strict Sense non-Blocking N/2 x N/2 N/2 x N/2 . . . . . . N/2 x N/2
  27. 27. Properties <ul><li>Size: </li></ul><ul><ul><li>F(N) = 4N + 3F(N/2) = 4N 1.58 </li></ul></ul><ul><ul><li>strict sense non-blocking </li></ul></ul><ul><ul><li>Clos network with k=3 n=2 </li></ul></ul><ul><li>Better parameters: </li></ul><ul><ul><li>k=sqrt{N} and n=sqrt{N} </li></ul></ul><ul><ul><li>recursive size sqrt{N} x sqrt{N} </li></ul></ul><ul><ul><li>Circuit size N log 2.58 N </li></ul></ul>
  28. 28. Cantor Networks <ul><li>m copies of Benes network. </li></ul><ul><li>For m >= log N its strict sense non-blocking </li></ul><ul><li>Network size N log 2 N </li></ul><ul><li>Example </li></ul><ul><li>Proof. </li></ul>
  29. 29. Advanced constructions <ul><li>There are networks of size N log N. </li></ul><ul><ul><li>the constants are huge! </li></ul></ul><ul><li>Basic paradigm also applies to large packet switches. </li></ul>

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