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Introduction of testing and verification of vlsi design

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Usha Mehta
Usha Mehta

This slides are introductory slides for the course testing and verification of VLSI Design which cover the basics of Why, Where, When and How of VLSI design testing

Engineering
1 of 47
Introduction to Testing and Verification of VLSI Design 04-08-2021 Dr Usha Mehta 1
Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 04-08-2021 Dr Usha Mehta 2
Agenda • Philosophy of Testing • Why to test • Do you love to be tested? • Where do bugs come from?. • When to test • When should be your test scheduled? • How to test • Verification and Testing in context of VLSI Design 04-08-2021 Dr Usha Mehta 3
Murphy’s Law……. - Edward Murphy, An American aerospace engineer who worked on safety-critical systems 04-08-2021 Dr Usha Mehta 4
Nothing is perfect……. 04-08-2021 Dr Usha Mehta 5
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System Development … Project Starts here…. 04-08-2021 Dr Usha Mehta 7 Courtesy: https://asiketltestanalyst.wordpress.com/tag/tom-and-jerry/
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Tom has forgotten that “Nothing is perfect…….” 04-08-2021 Dr Usha Mehta 10
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• Intel, producer of the affected chip, claims that the common user would experience it once every 27,000 years while IBM, manufacturer of a chip competing with Intel's Pentium, claims that the common user would experience it once every 24 days • Loss of $475 million 04-08-2021 Dr Usha Mehta 25
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Defective Parts Per Million (DPPM) • key metrics used to measure quality in many semiconductor segments • For mission-critical segments such as automotive and medical • Defective Parts Per Billion (DPPB) • For a premium vehicle • more than 7,000 semiconductor devices • If you assume a DPPM rate of 1 for all the semiconductor devices • it equates to seven failures for every 1,000 cars 04-08-2021 Dr Usha Mehta 29
• For Digital • 100 to 1000 DPM • For Analog and Mission Critical • Zero DPM • For 10nm Technology, 20% yield for many years for Intel 04-08-2021 Dr Usha Mehta 30
If testing is so important, why do people not test it thoroughly? • To save money • To save time • To hide the inefficiencies • …. 04-08-2021 Dr Usha Mehta 31
Tester…from Designer point of view….. • The relationship between the tester and everyone else in the project team has been like …. 04-08-2021 Dr Usha Mehta 32
Why so love-hate relationship? Can you prove the lion exists ? Can you prove the ghost does exits ? Or does not exist? Testing can only show the presence of errors, never their absence. -Edsger Djikstra 04-08-2021 Dr Usha Mehta 33
Tester….. From Production House point of view….. “Bugfree Design” does not give any extra revenue but bugs in design are very costly!!!! 04-08-2021 Dr Usha Mehta 34
• Costly re-spin(s) • Companies may miss out market window • Large companies can have reputation at stake – e.g. Pentium Bug • Smaller companies can have hard to recover financial implications • For start-ups, their existence itself can be at stake! 04-08-2021 Dr Usha Mehta 35 Respin…. 65 % of chips fail at first silicon Tester….. From Production House point of view…..
04-08-2021 Dr Usha Mehta 36 Tester….. From User Point of View….. Does user really value testing?
Tester Designer Does not love Consumer does not care Production house Does not want 04-08-2021 Dr Usha Mehta 37
Even though….. testing is important….. •Does testing directly generate any revenue? •Does designer like testing? •Does it generate “trust” ? •Does trust generate “reusability”? •Does reusability generate “revenue”? 04-08-2021 Dr Usha Mehta 38
Why testing is of too much importance in today’s semiconductor world….. • In Earlier days, design had all the glamour and testing was considered to be a dirty job, but now… 04-08-2021 Dr Usha Mehta 39 [Courtesy: ITRS]
Testing and Verification in Current Scenario • While the silicon capacity continues to increase along the Moore’s law, the efforts required to verify these designs have increased even a greater rate : doubling roughly every six to nine months. • In the era of multimillion gate Asics, reusable IPs, and SoC designs, 70% of the total efforts consumed by verification and testing. • Number of verification, validation, testing engineer is three the number of RTL design engineer • When design projects are completed, test benches makes up 80% of the total code volume. • Most of the job openings in India is in this field. • Design Hubs in Ahmedabad/Gujarat??? • Verification Hubs in Ahmedabad/Gujarat??? 04-08-2021 Dr Usha Mehta 40
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Once they grow…… 04-08-2021 Dr Usha Mehta 42 Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process
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•Design Errors • Misinterpretation of specification •Fabrication Errors • Wrong component • Incorrect Wiring •Fabrication Defects • Imperfect Process Variations •Physical Failure • During life time of a system 04-08-2021 Dr Usha Mehta 44
ASIC Design Flow 04-08-2021 Dr Usha Mehta 45
Architectural Behavioural RTL Gate Transistor Physical Unpacked Chip 04-08-2021 Dr Usha Mehta 46 Circuit Chip, Components, Interconnects… System System on Chip Network on Chip Prototype Testing Mass Production Testing System @ Field
Thanks……

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Introduction of testing and verification of vlsi design

  • 1. Introduction to Testing and Verification of VLSI Design 04-08-2021 Dr Usha Mehta 1
  • 2. Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 04-08-2021 Dr Usha Mehta 2
  • 3. Agenda • Philosophy of Testing • Why to test • Do you love to be tested? • Where do bugs come from?. • When to test • When should be your test scheduled? • How to test • Verification and Testing in context of VLSI Design 04-08-2021 Dr Usha Mehta 3
  • 4. Murphy’s Law……. - Edward Murphy, An American aerospace engineer who worked on safety-critical systems 04-08-2021 Dr Usha Mehta 4
  • 7. System Development … Project Starts here…. 04-08-2021 Dr Usha Mehta 7 Courtesy: https://asiketltestanalyst.wordpress.com/tag/tom-and-jerry/
  • 10. Tom has forgotten that “Nothing is perfect…….” 04-08-2021 Dr Usha Mehta 10
  • 11. 04-08-2021 Dr Usha Mehta 11
  • 12. 04-08-2021 Dr Usha Mehta 12
  • 13. 04-08-2021 Dr Usha Mehta 13
  • 14. 04-08-2021 Dr Usha Mehta 14
  • 15. 04-08-2021 Dr Usha Mehta 15
  • 16. 04-08-2021 Dr Usha Mehta 16
  • 17. 04-08-2021 Dr Usha Mehta 17
  • 18. 04-08-2021 Dr Usha Mehta 18
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  • 21. 04-08-2021 Dr Usha Mehta 21
  • 22. 04-08-2021 Dr Usha Mehta 22
  • 23. 04-08-2021 Dr Usha Mehta 23
  • 24. 04-08-2021 Dr Usha Mehta 24
  • 25. • Intel, producer of the affected chip, claims that the common user would experience it once every 27,000 years while IBM, manufacturer of a chip competing with Intel's Pentium, claims that the common user would experience it once every 24 days • Loss of $475 million 04-08-2021 Dr Usha Mehta 25
  • 26. 04-08-2021 Dr Usha Mehta 26
  • 27. 04-08-2021 Dr Usha Mehta 27
  • 28. 04-08-2021 Dr Usha Mehta 28
  • 29. Defective Parts Per Million (DPPM) • key metrics used to measure quality in many semiconductor segments • For mission-critical segments such as automotive and medical • Defective Parts Per Billion (DPPB) • For a premium vehicle • more than 7,000 semiconductor devices • If you assume a DPPM rate of 1 for all the semiconductor devices • it equates to seven failures for every 1,000 cars 04-08-2021 Dr Usha Mehta 29
  • 30. • For Digital • 100 to 1000 DPM • For Analog and Mission Critical • Zero DPM • For 10nm Technology, 20% yield for many years for Intel 04-08-2021 Dr Usha Mehta 30
  • 31. If testing is so important, why do people not test it thoroughly? • To save money • To save time • To hide the inefficiencies • …. 04-08-2021 Dr Usha Mehta 31
  • 32. Tester…from Designer point of view….. • The relationship between the tester and everyone else in the project team has been like …. 04-08-2021 Dr Usha Mehta 32
  • 33. Why so love-hate relationship? Can you prove the lion exists ? Can you prove the ghost does exits ? Or does not exist? Testing can only show the presence of errors, never their absence. -Edsger Djikstra 04-08-2021 Dr Usha Mehta 33
  • 34. Tester….. From Production House point of view….. “Bugfree Design” does not give any extra revenue but bugs in design are very costly!!!! 04-08-2021 Dr Usha Mehta 34
  • 35. • Costly re-spin(s) • Companies may miss out market window • Large companies can have reputation at stake – e.g. Pentium Bug • Smaller companies can have hard to recover financial implications • For start-ups, their existence itself can be at stake! 04-08-2021 Dr Usha Mehta 35 Respin…. 65 % of chips fail at first silicon Tester….. From Production House point of view…..
  • 36. 04-08-2021 Dr Usha Mehta 36 Tester….. From User Point of View….. Does user really value testing?
  • 37. Tester Designer Does not love Consumer does not care Production house Does not want 04-08-2021 Dr Usha Mehta 37
  • 38. Even though….. testing is important….. •Does testing directly generate any revenue? •Does designer like testing? •Does it generate “trust” ? •Does trust generate “reusability”? •Does reusability generate “revenue”? 04-08-2021 Dr Usha Mehta 38
  • 39. Why testing is of too much importance in today’s semiconductor world….. • In Earlier days, design had all the glamour and testing was considered to be a dirty job, but now… 04-08-2021 Dr Usha Mehta 39 [Courtesy: ITRS]
  • 40. Testing and Verification in Current Scenario • While the silicon capacity continues to increase along the Moore’s law, the efforts required to verify these designs have increased even a greater rate : doubling roughly every six to nine months. • In the era of multimillion gate Asics, reusable IPs, and SoC designs, 70% of the total efforts consumed by verification and testing. • Number of verification, validation, testing engineer is three the number of RTL design engineer • When design projects are completed, test benches makes up 80% of the total code volume. • Most of the job openings in India is in this field. • Design Hubs in Ahmedabad/Gujarat??? • Verification Hubs in Ahmedabad/Gujarat??? 04-08-2021 Dr Usha Mehta 40
  • 41. 04-08-2021 Dr Usha Mehta 41
  • 42. Once they grow…… 04-08-2021 Dr Usha Mehta 42 Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process
  • 43. 04-08-2021 Dr Usha Mehta 43
  • 44. •Design Errors • Misinterpretation of specification •Fabrication Errors • Wrong component • Incorrect Wiring •Fabrication Defects • Imperfect Process Variations •Physical Failure • During life time of a system 04-08-2021 Dr Usha Mehta 44
  • 45. ASIC Design Flow 04-08-2021 Dr Usha Mehta 45
  • 46. Architectural Behavioural RTL Gate Transistor Physical Unpacked Chip 04-08-2021 Dr Usha Mehta 46 Circuit Chip, Components, Interconnects… System System on Chip Network on Chip Prototype Testing Mass Production Testing System @ Field