Sunil KumarIntel, BangaloreTrends in Mixed Signal Validation
AgendaMixed Signal SystemEvolution of MSVVerilog-AMS OverviewMixed Signal ToolsSteps in MSVConclusion
Mixed Signal SystemA system having some parts in analog domain andsome in digital domainA typical chip has these mixed sig...
Mixed Signal System: An ExampleSerializerDe-serializerClock andDataRecoveryPLL PLLBIASGenerationBIASGeneration
Evolution of MSVGeneration IAnalog Digital interactions were quite lessAnalog was verified in CKT simulator while digital ...
Evolution of MSVGeneration IIIShare of Mixed signal circuits has grown rapidlyPLLs, DDR3/4, PCI Express, 10/40GbE, HyperTr...
SPICEVerilog-AVerilog-AMS OverviewExtension of Verilog HDLAdds analog and mixed signal capabilitiesAlignment of Verilog-AM...
Verilog-AMS: Examples`include “disciplines.vams”module res10ohm (res_in,res_out);inout res_in, res_out;electrical res_in, ...
On ModelingValidation is as good as the modelsThe models need to be accurate enoughAnd for speed, they need to have enough...
Mixed Signal ToolsCombine two different methods of simulationEvent-driven simulation as found in logic simulatorsContinuou...
Steps in MSVStep 1: ModelingIdentify the CKT blocks which needs to be modeled in AMSCreate AMS models with inputs from CKT...
Example: Charge Pump PLLRef: August, N., “A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circu...
Analog Driver (Verilog-AMS Module)Test (SV Program)Harness (SV Class)MSV Testbench in SVBFM1 (SV Class)BFMN (SV Class)Chec...
ConclusionsMixed Signal Validation has become an important component ofthe validation spaceThe MSV tools have maturedMany ...
ReferencesVerilog-AMS Language Reference Manualhttp://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.3/VAMS-LRM-2...
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Trends in Mixed Signal Validation

  1. 1. Sunil KumarIntel, BangaloreTrends in Mixed Signal Validation
  2. 2. AgendaMixed Signal SystemEvolution of MSVVerilog-AMS OverviewMixed Signal ToolsSteps in MSVConclusion
  3. 3. Mixed Signal SystemA system having some parts in analog domain andsome in digital domainA typical chip has these mixed signal blocks:PLLs andCLK dist.PowerDistributionThermalSensorsResetsHigh Speed InterconnectBIASGen/CompSideband IOs
  4. 4. Mixed Signal System: An ExampleSerializerDe-serializerClock andDataRecoveryPLL PLLBIASGenerationBIASGeneration
  5. 5. Evolution of MSVGeneration IAnalog Digital interactions were quite lessAnalog was verified in CKT simulator while digital wasverified in digital simulatorA D were verified by manually reviewGeneration IIAnalog blocks were modeled in Verilog/VHDLThese models were calibrated with CKT to some extentAnalog blocks were still verified in CKT simulatorsA D were covered using the created modelsThe models were incapable of modeling analog behavior, e.g.,voltage levels, ramp, termination effect etc
  6. 6. Evolution of MSVGeneration IIIShare of Mixed signal circuits has grown rapidlyPLLs, DDR3/4, PCI Express, 10/40GbE, HyperTransport, FBD,QPIDigital models are not sufficient enoughHDLs have been created for analog and mixed signalVerilog-AMS, VHDL-AMSAnalog and mixed signal blocks are modeled in AMS HDLNew tools came up to support these languagesMentor’s ADMS, Cadence’s AMS, Synopsys’s Discovery-AMSMost of these tools have started supporting Fast SPICE
  7. 7. SPICEVerilog-AVerilog-AMS OverviewExtension of Verilog HDLAdds analog and mixed signal capabilitiesAlignment of Verilog-AMS with the SystemVerilog is WIPVerilog-DMS ExtensionVerilog-AMS
  8. 8. Verilog-AMS: Examples`include “disciplines.vams”module res10ohm (res_in,res_out);inout res_in, res_out;electrical res_in, res_out;parameter real RES_VALUE = 10.0;analog beginV(res_in, res_out) <+RES_VALUE*I(res_in, res_out);endendmodule`include “disciplines.vams”module dig2ana (dig_in,ana_out);input dig_in;output ana_out;wire dig_in;electrical ana_out;real ana_value;analog beginif (dig_in == 1) ana_value = 1.1;else ana_value = 0.0;V(ana_out) <+ transition(ana_value, 0,10e-12);/endendmodule
  9. 9. On ModelingValidation is as good as the modelsThe models need to be accurate enoughAnd for speed, they need to have enough abstractionsVerilog-AMSVerilog/SV SPICEAccuracySpeed
  10. 10. Mixed Signal ToolsCombine two different methods of simulationEvent-driven simulation as found in logic simulatorsContinuous-time simulation as found in circuit simulatorsUse digital simulator and analog simulatorMentor’s ADMS : Modelsim + EldoSynopsys’s Discovery-AMS: VCS + NanosimCadence’s AMS: NC-Sim + SpectreOn top of these the tool has toSplit the netlist in Verilog and SPICE and insertion of connectmodulesSet up and run the simulation by synchronizing the time steps oftwo simulators
  11. 11. Steps in MSVStep 1: ModelingIdentify the CKT blocks which needs to be modeled in AMSCreate AMS models with inputs from CKT teamExtensively calibrate these models with the corresponding CKT blocksStep 2: Block ValidationExtensive validation of all the closed loops and complex features in lower leveltestbenchesEach analog block can have any one of the views: Digital, AMS, SPICEStep 3: Cluster/System Level ValidationValidate the sequence and inter-dependencies of the features validated at blocklevelMost of the traditional digital validation techniques can be used, e.g.,randomization, coverage, Specman/SV based testbenches etc.Reuse of corresponding digital validation environment is possible
  12. 12. Example: Charge Pump PLLRef: August, N., “A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intels Test Chips”,ISQED 2008
  13. 13. Analog Driver (Verilog-AMS Module)Test (SV Program)Harness (SV Class)MSV Testbench in SVBFM1 (SV Class)BFMN (SV Class)Checker1 (SV Class)CheckerN (SV Class)Interface1 InterfaceNDUT (Mixed Analog and Digital)ClockGeneratorAnalogSourcesResetGeneratorSV Wrapper (SV Module)Top Level (SV Module)Ref: August, N., “A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intels Test Chips”, ISQED 2008AnalogDigital
  14. 14. ConclusionsMixed Signal Validation has become an important component ofthe validation spaceThe MSV tools have maturedMany fatal bugs which were earlier found only in post-siliconcan be uncovered in MSVMost of the digital validation techniques can be used
  15. 15. ReferencesVerilog-AMS Language Reference Manualhttp://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.3/VAMS-LRM-2-3.pdf“The Designer’s Guide to Verilog-AMS”, Kenneth S.Kundert and Olaf Zinke, Springer, 2004Verilog-AMS models examples:http://www.designers-guide.org/VerilogAMS/
  16. 16. Q&A

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