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Simulation Versus Acceleration, Versus Emulation

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Simulation Versus Acceleration, Versus Emulation

  1. 1. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-external 1Simulation Versus ?Anoosh HosseiniCisco Systems
  2. 2. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 2IntroductionSimulation versus acceleration, versus emulationWhich solution is right for me?When we use simulation
  3. 3. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 3Simulation, Acceleration, EmulationNot going to argue between the threeThe right solution is a factor of:–Complexity and size of the chip/system–The goals, the amount of time allocated, Time to Market, andpotential impact–Module or full chip centric DV plan–Is the focus DV or SW dev–The methodology, process, and procedures of a company–The vision, leadership, and engineers who are going to execute theplan
  4. 4. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 4Acceleration (Circa ~1999)Acceleration resulted in 5-10X speed up give testbenchoverhead.Developed light weight TB to leverage HW for 200X(over Sparc 450Mhz)Cycle based simulation resulted in 50XBuilt a C model of the XR 12000 fabric wired to NLincards. One LC accelerated RTL, the rest C modelsof LC.
  5. 5. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 5Distributed Simulation (Circa ~2002)10 ASIC CRS-1 linecard simulationGlobally developed, mixed DV languages, librariesDecided on developing both a distributed simulation library, andlow overhead Perl based DV environmentASIC’s used as building blocks compiled as independent entitiesVirtual schematic wired up chips at runtimeScaled to 32 ASIC fabric simulationNo emulation/acceleration solutionLeveraged large compute farm
  6. 6. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 6Emulation (Circa 2005-6)25M gate ASICEmulated with home brew FPGA solution250KhzFound bugs after 4 hour runSW bringup tested on emulation platform
  7. 7. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 7SOC Simulation for SW Development ( Circa2003-2007)New High End SOC Packet ProcessorNo full chip RTL for 2-3 yearsNeed to Develop SW in the absence of Silicon & RTLDeveloped a C model of the SOCPredicted performance within 6-10%Control plane + data plane integration in simulationLive BGP 1M route updates, VoIP etcEmbedded SW run on RTL and Silicon flawlesslyProduct enters system test at record pace
  8. 8. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 8SOC Simulation As Basis For Embedded SWDevNeed to support tens to hundreds of developersProprietary tools vs open sources: License fees add up!IDE for managing and visualizing simulationAdvanced tracing and analysisSophisticated checks and assertionAdvanced temporal breakpointsSingle step forwards and backwards in time
  9. 9. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 9Future Possibilities For SOC simulationBreak the problem down to two components: processorsimulation, custom logic simulationProcessor Simulation: Fast ISS technology, InstructionSet emulation/translationCustom logic: Traditional simulation, FPGA’s
  10. 10. © 2007 Cisco Systems, Inc. All rights reserved.Simulation-DV-External 10

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