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Nanometer Testing: Challenges and Solutions                             Jais Abraham                   AMD India Design Ce...
Characteristics of Nanometer DevicesDesign trends Increasing corners of operation (multiple frequencies, voltage, power sc...
Test Challenges – IncreasedParametric Variations  Source : “Parametric Failures in CMOS ICs- A Defect       Based Analysis...
At Least Test will Find It?                                             e-              e-                                ...
Test Challenges – New FailureMechanisms                            Cu Voids     Open                                   Sho...
Test Challenges - Cost of Test        Source : International Technology Roadmap for Semiconductors, 2001
Test Challenges – Power Test power could be more than functional power – more regions of the device operating than in func...
Test Challenges - Yield LearningDefect sizes scale as quickly or faster than the device features Difficulty in localizing ...
SOLUTIONS
New Fault Models - Bridge FaultTestingBridge fault testing detects shorts between interconnects                    0      ...
Bridge Fault TestingNumber of possible bridges in a design is exponential tothe number of nets  Bridge node pair extractio...
High resistance bridging faults                              Bridge Resistance Data*         Source: “Test challenges in n...
Delay FaultDC tests (eg based on stuck-at, logic bridge model) areno longer adequate AC tests which ensure that the design...
Delay Fault TestingDelay fault tests check if any node in the design is slowerto rise or fall than it shouldRequires desig...
Small Delay Defects   Source: “Test Method Evaluation Experiments and Data”, Nigh et al., ITC2000
Small Delay Fault Testing                                  small delay test          0.4                0.1               ...
Reducing the Cost of Scan TestsScan in 1                                                            Scan out 1Scan in 2   ...
Scan Compression                 Scan chain group 1          Scan chain group N                              Scan chain gr...
Reducing Power During Test Divide and conquer      Switch lesser logic while reducing test time Prevent the functional log...
What is the Problem?   Design 1                        Design 2               • Same Die Size               • Same Complex...
What is the Problem?   Design 1                          Design 2   77% Yield                        42% Yield  Interactio...
Scan based diagnosticsTo enable effective use of scan patterns for yieldlearning, the patterns should have Capability to i...
Scan based diagnostics                                       Layout                           Defect     mapping          ...
Economics                            $$$$        Yield                Accelerated Yield Learning                Standard Y...
ConclusionNanometer testing presents new challenges not seenhithertoWithout a single-eyed focus on test, either of thefoll...
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Nanometer Testing: Challenges and Solutions

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Nanometer Testing: Challenges and Solutions

  1. 1. Nanometer Testing: Challenges and Solutions Jais Abraham AMD India Design Centre
  2. 2. Characteristics of Nanometer DevicesDesign trends Increasing corners of operation (multiple frequencies, voltage, power scenarios) Increasing integration (SOCs, SIPs) Permeation of high bandwidth serial/ differential interfacesProcess issues Process variations becoming key concern Increasing wiring densities leading to complex signal integrity problems Dominance of new kinds of defects based on the metal subsystem
  3. 3. Test Challenges – IncreasedParametric Variations Source : “Parametric Failures in CMOS ICs- A Defect Based Analysis”, Hawkins et al., ITC2002
  4. 4. At Least Test will Find It? e- e- L TARGET L EFFECTIVE Minor bridging defects etc. Current vs. Speed LimitCurrent L EFFECTIVE = L TARGET - X e- e- X : Lot1 L TARGET O : Lot2 L EFFECTIVE L EFFECTIVE = L TARGET + X Source: Madge, et. al., 2004 Speed
  5. 5. Test Challenges – New FailureMechanisms Cu Voids Open Shorts
  6. 6. Test Challenges - Cost of Test Source : International Technology Roadmap for Semiconductors, 2001
  7. 7. Test Challenges – Power Test power could be more than functional power – more regions of the device operating than in functional mode – switching of logic during scan shift With increasing design frequencies & integration – Can the tester supply the power required in the test mode – Can the package support the power required in the test mode – Will the part be able to withstand the power consumption during high voltage testing
  8. 8. Test Challenges - Yield LearningDefect sizes scale as quickly or faster than the device features Difficulty in localizing faults increases one order of magnitude every six years Defective chips offer significant information on these failure mechanismsYield learning is becoming increasingly important To tune the manufacturing processes to achieve higher profits To reduce the time for volume production since product life cycles are coming down
  9. 9. SOLUTIONS
  10. 10. New Fault Models - Bridge FaultTestingBridge fault testing detects shorts between interconnects 0 A 0 0 1 1 B 0
  11. 11. Bridge Fault TestingNumber of possible bridges in a design is exponential tothe number of nets Bridge node pair extraction is done from layout based on proximity analysis Critical Area AnalysisFour possible bridge fault tests exist for a pair of nodes Could lead to a large test vector count
  12. 12. High resistance bridging faults Bridge Resistance Data* Source: “Test challenges in nanometer”, Kundu et al., ITC2000
  13. 13. Delay FaultDC tests (eg based on stuck-at, logic bridge model) areno longer adequate AC tests which ensure that the design works at the rated speed are required
  14. 14. Delay Fault TestingDelay fault tests check if any node in the design is slowerto rise or fall than it shouldRequires design techniques to obtain high coverage On-chip PLL based clocking Support for multiple clock domains Knowledge of device timing exceptionsConsume 2x-5x times the number of test patterns forstuck-at fault testing
  15. 15. Small Delay Defects Source: “Test Method Evaluation Experiments and Data”, Nigh et al., ITC2000
  16. 16. Small Delay Fault Testing small delay test 0.4 0.1 transition test 0.3 0.3 0.2 0.5
  17. 17. Reducing the Cost of Scan TestsScan in 1 Scan out 1Scan in 2 Scan out 2Scan in 3 Scan out 3Scan in 4 Scan out 4Scan in 5 Scan out 5 Test time = length of scan chain x #patterns x (1/frequency of shifting) Test volume = length of scan chain x #patterns x 2
  18. 18. Scan Compression Scan chain group 1 Scan chain group N Scan chain group 2 Scan in 1 C E o x m Scan in 2 p p a r n e d s e s Scan in N r o r
  19. 19. Reducing Power During Test Divide and conquer Switch lesser logic while reducing test time Prevent the functional logic from switching during scan shift using data gating Power aware ATPG patterns which prevent transitions that don’t result in additional coverage
  20. 20. What is the Problem? Design 1 Design 2 • Same Die Size • Same Complexity • Same Foundry • Same Process
  21. 21. What is the Problem? Design 1 Design 2 77% Yield 42% Yield Interactions Between Design and Manufacturing
  22. 22. Scan based diagnosticsTo enable effective use of scan patterns for yieldlearning, the patterns should have Capability to identify failures – Requires high test coverage Capability to isolate the failures – Accurately map the failures to the physical location of the failures
  23. 23. Scan based diagnostics Layout Defect mapping suspect coordinates Physical Failure Analysis Failure Diagnostics Information Defect information ATPG based failure diagnostics Manufacture Wafer Failure Information Test
  24. 24. Economics $$$$ Yield Accelerated Yield Learning Standard Yield Improvement Time
  25. 25. ConclusionNanometer testing presents new challenges not seenhithertoWithout a single-eyed focus on test, either of thefollowing scenarios are likely: Low Test Quality : High escape rates of defective devices High Test Cost : Affecting profitability Slow ramp to volume : Missing critical time-to-market windowsThe solution to these problems requires a tightinteraction between the test experts, silicon technologyexperts and ATE experts

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