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Modeling System Behaviors: A Better Paradigm on Prototyping
“Modeling System behaviors”….A better Paradigm on prototyping -Nilesh Ranpura
Electronic System Structure System development process Software input/output Hardware input/output Software Hardware Abstraction trade offsdevelopment development process process
System Abstraction and Development ProcessSystem Development happens this way Design FlowBecause,1. “Abstraction layers” ensure Concept Architecture specs threads running concurrently2. Different approach of specs SPI 5 Chip/Block specs due to different types of team Hardware3. More than one customer with and Board/proto specs proto specs different nature/features Product Specs Not documented System data/environment Reference Platforms
Which are those System Properties ? Hardware & Environmental Software co-exist System Safety/Mixed Signal Properties Standards/ Compliance NewPerformance Approaches : Error injection Green mode
(1)PCIe Switch Applications – System InterconnectCompute Blade Compute Blade Compute BladeMemoryMemory CPU CPU Memory Memory Memory Memory CPU CPU Memory Memory Memory Memory CPU CPU Memory Memory I/O Hub I/O Hub I/O Hub PCIe PCIe Inter-Domain Switch Inter-Domain Switch PCIe System Interconnect Switch Storage Local I/O Blade Blade Storage Processor Processor Processor Fibre Channel SATA / SAS Expander Dual GbE Dual GbE Controller Controller Controller FC FC GbE GbE GbE GbE
Model parameter ValuesParameter Value RemarkMPS 128 TestbenchPayload 128/256/512 TestcasePacket types MRD,MWR,IRD TestcaseTraffic pattern Multicast, One to one, Testbench Many to oneSpeed 2.5Ghz, 5Ghz TestcaseState PM or non PM TestbenchActive Port 2/4/5/6/8 TestcaseNo of packets 20/100/500/5000 TestcaseMisc. ECRC, etc
Model Latency definition Latency is the delay between starting and completing action Latency Definition: Payload Switch efficiency Theoretical(GBps) Actual throughput (GBps) (Bytes) (Actual/Theoretical) % 32 2.462 2.000 81% 64 3.048 2.905 95% 128 3.459 3.360 97% Throughput (pkts/sec) = (total number of pkts(i.e. 500)/(time_t1 - time_t0)) Throughput (bits/sec) = (throughput (pkts/sec) * length * 32) In this case, length = Payload size + 3DW header Theoretical max throughput assumes a 20 byte framing overhead on top of payload. After removing 8b/10 coding, useful x8 Gen2 unidirectional throughput is 4 GB/s. (4 GBps * payload) / (payload + 20) = theoretical max (second column above)
Usage Model and Error Model CPU CPU P2P NTB NTB NTB NTB P2P CPU Memory CPU Memory P2P P2P P2P P2P P2P P2P P2P P2P I/OI/O I/O I/O I/O I/O I/O I/O I/O Hub I/O Hub ... . . . . ... PCIe Switch PCIe Switch I/O I/O 1GbE 1GbE I/O I/O 1GbE 1GbE Internal Switch Error External Error
(2)Modeling Channel properties and Mixed signal for Simple Link1. Model as much as digital blocks up to last stage2. Last analog Transceiver can be modelled and converted in to Differential digital by just inverting it.3. Next slide depicts digital noise and transmission model
(2)Introduce Digital Noise •Inversion •bit stuffing •dummy bits Noise Model 22 20 •Inversion 15 8 bit value of 5 •bit stuffing 20(sample value) •dummy bits 4 3 Noise Model1. Send 22, 20. 15, 5(which are analog sample’s value) in digital format but in parallal. So no. of data lines = no. of analog samples * 8 bit2. Introduce noise in numbers by inversion or value changing.
(2)Actual System High speed PHY MACPAM modulation and Signal pathprocessing block
(2)Actual System High speed PHY MAC •Inversion •bit stuffing •dummy bitsNoise Model PAM modulation and Signal path processing block 1. Modeled PAM modulation scheme over digital block 2. Created noise model to make noise variation between -20dB to 30dB for high speed signals on Cable. 3. Simulated virtual NEXT, FEXT, ISI with predictable noise model. 4. Loop back and system loop back mode tested