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HW Emulators:Does it belong in yourVerification tool chest?DV Club, May 23rd, 2007Jai KumarVerification TechnologistSun Mi...
Slide 2Verification Challenges• Large SoCs -> Multi-core, multi-thread every where> Complex IOs: ENET, PCIE, etc.> Verific...
Slide 3Jai KumarDV ClubUltraSPARC T1 Processor• A true revolutionary processor• Up to eight 4-way multithreadedcores for u...
Slide 4Jai KumarDV ClubUltraSPARC T2 Processor• True SoC• 8 SPARC Cores, 8threads each• Shared 4MB L2 8-banks, 16-wayassoc...
Slide 5What is an Accelerator/Emulator?• Emulation- synonomous with HW Acceleration;subtle difference – involves target sy...
Slide 6Jai KumarDV ClubConvince it is the right thing to do...Gulfstream jetEmulator HW
Slide 7Jai KumarDV ClubCost of Bugs – simple analysis• Showstopper bug early in design phase> Cost: almost negligible• Sho...
Slide 8Jai KumarDV ClubWhen you put everything togetherand your simulator comes to acrawl....Who do you call?EmulatorsEmul...
Slide 9Design Size Impact on Sim Speed0 20 40 60 80 100 120 140 1601101001000100001000001000000SW SimAccelerationEmulation...
Slide 10Jai KumarDV ClubWhen you need to run millions ofcycles to catch those nasty deepcorner case bugs....Who do you cal...
Slide 11Jai KumarDV ClubSimplified Bug Find Rate1 2 3 4 5 6 7 8 9 10 11 12 130102030405060708090Bug RateM cyclesTimeBugRat...
Slide 12Jai KumarDV ClubWhen you need to boot firmware,and Solaris....Who do you call?EmulatorsEmulatorsSimulation - ~27ye...
Slide 13Jai KumarDV ClubWhen you need to run real worldPCIE, ENET IO traffic on yourSoCs....Who do you call?EmulatorsEmula...
Slide 14Jai KumarDV ClubEmulation Resources – at a glanceDriveDriveWalkWalk RunRun FlyFlyFlexibility: Supported RTL, TestB...
Slide 15Jai KumarDV ClubUsage ModelDFTBlock-Level Full-Chip System Post-SiliconTapeOutSW Simulator (VCS/XSIM)Verification ...
Slide 16Jai KumarDV ClubEmulation Verification:Get System HW/SW right the first time:•Prevent Functional Bug escapes (redu...
Slide 17Jai KumarDV ClubPlanning for Success● Setup Emulation Environment early -− Create technology-awareness within team...
Slide 18Jai KumarDV ClubHW Emulation Results• Initial design bringup in co-simulation mode with ISS• Target-less emulation...
Slide 19Jai KumarDV ClubSummary• Exponential complexity with large SoCs> multi-core,> multi-threads,> complex IOs• HW Emul...
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HW Emulators: Does it Belong in your Verification Tool Chest?

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HW Emulators: Does it Belong in your Verification Tool Chest?

  1. 1. HW Emulators:Does it belong in yourVerification tool chest?DV Club, May 23rd, 2007Jai KumarVerification TechnologistSun Microsystems Inc.jai.kumar@sun.comhttp://sun.com
  2. 2. Slide 2Verification Challenges• Large SoCs -> Multi-core, multi-thread every where> Complex IOs: ENET, PCIE, etc.> Verification state-space explosion• Fierce Competition -> Time-to-Market> Cost• Tools not keeping the pace with requirements -> Capacity> Performance
  3. 3. Slide 3Jai KumarDV ClubUltraSPARC T1 Processor• A true revolutionary processor• Up to eight 4-way multithreadedcores for up to 32 simultaneousthreads• All cores connected through a134.4GB/s crossbar switch• High-bandwidth 12-wayassociative• 4 DDR2 channels (23GB/s)• Power : 63W @1.2GHz, 1.2v• ~300M transistors• 378 sq. mm die• Verification covered in earlier DVClub presentation
  4. 4. Slide 4Jai KumarDV ClubUltraSPARC T2 Processor• True SoC• 8 SPARC Cores, 8threads each• Shared 4MB L2 8-banks, 16-wayassociative• 4 dual-channelFBDIMM memorycontrollers• 2 1/10 Gb ENET portsw/ onboard packetclassification andfiltering• 1 PCIE x8 1.0 port
  5. 5. Slide 5What is an Accelerator/Emulator?• Emulation- synonomous with HW Acceleration;subtle difference – involves target system hw• High-level proto-typing system – virtual silicon• RTL is synthesized to gates; gates are mapped toFPGA or custom-processor based HW to executedesign in parallel at hw speed• Ease-of-use – make it appear as a fast“simulator” - more than 10,000X faster than SWSimulator
  6. 6. Slide 6Jai KumarDV ClubConvince it is the right thing to do...Gulfstream jetEmulator HW
  7. 7. Slide 7Jai KumarDV ClubCost of Bugs – simple analysis• Showstopper bug early in design phase> Cost: almost negligible• Showstopper bug close to tapeout> Cost: schedule impact• Showstopper bug after tapeout> Cost: Few Silicon respins, schedule impact• Showstopper bug close at Revenue Release> Loss of Revenue at $1+ Million per day> Reduce competitive edge• Showstopper bug 1year after Revenue Release> Cost of recall at $150Million> Damages corporate reputationGetting SW/HW right the first time is critical to survival!Source: N.Winkworth & B.Blohm
  8. 8. Slide 8Jai KumarDV ClubWhen you put everything togetherand your simulator comes to acrawl....Who do you call?EmulatorsEmulators
  9. 9. Slide 9Design Size Impact on Sim Speed0 20 40 60 80 100 120 140 1601101001000100001000001000000SW SimAccelerationEmulationDesign Size (M gates)Performance(cycles/sec)
  10. 10. Slide 10Jai KumarDV ClubWhen you need to run millions ofcycles to catch those nasty deepcorner case bugs....Who do you call?EmulatorsEmulators
  11. 11. Slide 11Jai KumarDV ClubSimplified Bug Find Rate1 2 3 4 5 6 7 8 9 10 11 12 130102030405060708090Bug RateM cyclesTimeBugRate-SimulationCycles
  12. 12. Slide 12Jai KumarDV ClubWhen you need to boot firmware,and Solaris....Who do you call?EmulatorsEmulatorsSimulation - ~27yearsEmulation - 8.5hours
  13. 13. Slide 13Jai KumarDV ClubWhen you need to run real worldPCIE, ENET IO traffic on yourSoCs....Who do you call?EmulatorsEmulators
  14. 14. Slide 14Jai KumarDV ClubEmulation Resources – at a glanceDriveDriveWalkWalk RunRun FlyFlyFlexibility: Supported RTL, TestBench constructsSolarisBootTIme26.7 Years 2.6 Years 2Days19Hrs 8 Hrs 30minsCompetitor XSW Simulator Xtreme Server Palladium2
  15. 15. Slide 15Jai KumarDV ClubUsage ModelDFTBlock-Level Full-Chip System Post-SiliconTapeOutSW Simulator (VCS/XSIM)Verification TimelineTharas CoSimXtreme CoSimXtreme Targetless EmulationShort, Directed Tests/ISS ComparedLong, Random Tests/Self CheckingFirmware/SW StackPalladium Targetless/ICEIO Verif(PCIE/ENET)
  16. 16. Slide 16Jai KumarDV ClubEmulation Verification:Get System HW/SW right the first time:•Prevent Functional Bug escapes (reduce Silicon re-spins - find bugs before tape-out)•Facilitate early SW Development and SystemIntegration•Aid Post-Silicon Debug & Fix Validation
  17. 17. Slide 17Jai KumarDV ClubPlanning for Success● Setup Emulation Environment early -− Create technology-awareness within team early in design phase− Decide Usage mode – co-sim, targetless, in-circuit emulation− Minimize learning curve - integrate into existing simulation flow− Not everything can be run on the emulator – prioritize & plan usage● Reduce Time-to-Model Build -− Apply RTL enforcement (use lint, emulator tools);● Minimize Modeling Issues− Array Modeling Methodology – abstract higher, make it “synthesizable”, race free− Optimize for Capacity and Performance: Eliminate non-functional models, abstractlow-level details, minimize and align clocks● Simplify Debug− Implement critical-set of Monitors for acceleration− Invest in debug tools to ease the debug complexity− Do not use it as yet another simulator (minimize waveform dumps)Maximize ROI.
  18. 18. Slide 18Jai KumarDV ClubHW Emulation Results• Initial design bringup in co-simulation mode with ISS• Target-less emulation for fastest throughput - trillions of cycles• Ran really long directed tests• Ran a number of self-checking random code generators to targettests to specific functionality – some tests run for days• Reset Sequence testing, RAS Testing, On-Chip Debug test• PCIE & ENET Testing using Speed Bridges• JTAG Scan Testing using In-Circuit Emulation• Motherboard bringup and test using In-Circuit Emulation• Facilitated readiness of silicon test/debug tools• Post-Silicon RTL bug fix validation
  19. 19. Slide 19Jai KumarDV ClubSummary• Exponential complexity with large SoCs> multi-core,> multi-threads,> complex IOs• HW Emulation is a must> Traditional SW simulators alone are not enough• Cost is justified in big scheme of productdevelopment

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