Design VerificationResearch and TeachingKerstin EderDesign Automation and VerificationDepartment ofCOMPUTER SCIENCE
COMSM0115: Design VerificationAim:“To familiarize students with the routinetasks and the latest techniques in designverification, and to give them thetheoretical background plus some of thepractical skills expected from aprofessional design verification engineer.”
SyllabusIntroduction to HW Design Flow and Functional VerificationVerification Flow and ToolsTraditional simulation-based Verification:basic testbench architecture, directed testing, driving & checking tutorialVerification Planning ProcessCoverage:metrics: structural, functional, analysis, need to combine metricsAutomation for Verification:constrained pseudo-random stimulusgenerationself-checking testbenchesCoverage Driven VerificationAssertion Based VerificationFunctional Formal Verification
Design Verification ResearchExploiting state-of-the-art techniques from otherareas of CS to advance Design VerificationFormal specification, refinement, derivation andverification by mathematical proofReassessing processor design decisions – impact onverificationCoverage Directed Test Generation:Formal approachesFeedback-based approaches – machine learningMethodology development for coverage balancingIndustrial Collaboration with:IBM Research Labs in Haifa (Israel)Local semiconductor industry: STM, Infineon, Clearspeed,Xmos, BRCM, Icera etcEDA: Cadence and Mentor Graphics
Opportunities to get involvedUndergraduate student projects– Final year project BSc:400h (40 CP), part-time, October to May– Final year project MEng:400h (40 CP), full-time, February to MayMSc student projects– 200h (20 CP), part-time, February to May– 600h (60 CP), full-time, June to SeptemberPhD– 3 years 6 months full-time researchEngD– 4 years full-time research and professional training– 75% of time spent in industry– Portfolio-basedGet involved:Contact Kerstin.Eder@bristol.ac.uk to explore collaboration opportunities
Ramaram Naresh (MSc AMSE student at University of Bristol)Email ID : firstname.lastname@example.orgExperience : Worked as Member Technical staff in GDMicro Systems Pvt Ltd for THREE plus years.Interested in : SOC Verification, Analog & Mixed signaldesign.Domain Expertise : SOC Verification, ReferenceVerification Methodology & AMBA AHB/APB bus systems.Projects Done : Dual core 2 million gate countSystem-on-chip using 90nm technology, AHBVerification IP using VERA.Role : Verification of chip at block, system and productionlevel.Languages : C, C++, Verilog, Unix, Perl.