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Adopting SystemVerilog / OVMAndrew Bond DVClub 22nd April 2009Copyright 2009 Icera Inc 1
OverviewCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 2• The “Verification Challenge” at Icera• Why we are i...
Verification @ IceraCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 3
Verification @ IceraCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 4• Two silicon design sites• Small design ...
ChipVerification @ IceraCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 5CPUProgrammableDSPMemorySub-SystemSys...
Why SystemVerilog / OVM?Copyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 6
Why SystemVerilog / OVM?Copyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 7• The “Open” in OVM• Vendor / License...
Plus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 8• Getting started is quick• LRM in general provide...
Plus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 9• Constraints aren’t as complex• Strangely this ca...
Minus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 10• Vendor support• Supported language features ar...
Minus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 11• Few good quality examples of more complex conc...
Making the Switch Less PainfulCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 12
Making the Switch Less PainfulCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 13• Start from the bottom• A UVC...
ConclusionsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 14
ConclusionsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 15• You can create an “Advanced Verification Enviro...
THANK YOUCopyright 2009 Icera Inc 16Andrew Bond DVClub 22nd April 2009
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Adopting SystemVerilog/OVM

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Adopting SystemVerilog/OVM

  1. 1. Adopting SystemVerilog / OVMAndrew Bond DVClub 22nd April 2009Copyright 2009 Icera Inc 1
  2. 2. OverviewCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 2• The “Verification Challenge” at Icera• Why we are interested in SystemVerilog and OVM• Plus points• Minus points• Making the switch less painful• Conclusions
  3. 3. Verification @ IceraCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 3
  4. 4. Verification @ IceraCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 4• Two silicon design sites• Small design team• Even smaller verification team• All designers must help with verification• Verification split into 3 tasks:• Designers own “smoke” testing• Sign-off verification environments• Formal Property Checking• Cadence Incisive customer
  5. 5. ChipVerification @ IceraCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 5CPUProgrammableDSPMemorySub-SystemSystemInter-Connect
  6. 6. Why SystemVerilog / OVM?Copyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 6
  7. 7. Why SystemVerilog / OVM?Copyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 7• The “Open” in OVM• Vendor / License independence• Visibility of source code• A World full of developers• Methodology seemed sound• Evolved from the eRM/URM we have previously used• Incorporates another mature methodology in AVM• SystemVerilog is still fundamentally a HDL• More familiar to “part-time” verification engineers• Native to the simulator• SystemVerilog class based approach familiar to C++ programmers
  8. 8. Plus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 8• Getting started is quick• LRM in general provides good SystemVerilog examples• The OVM Reference and User Guide are pretty good• Can get good feedback from the OVM Forum• Successfully created “real” verification environments• Roughly equivalent development time as equivalent eenvironments• Including multiple layers of UVCs
  9. 9. Plus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 9• Constraints aren’t as complex• Strangely this can make both the development and debug easier• So far haven’t encountered a blocking issue• SystemVerilog seems a natural testbench language• The DPI is a massive improvement over the PLI/VPI
  10. 10. Minus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 10• Vendor support• Supported language features aren’t always known before you findthem• Can make design choices hard – lots of simple test cases• Debug features aren’t as mature as they are for other supportedlanguages• AVM and URM• Not 100% harmonious – you will be referred to the olddocumentation• Some concepts are blurred – sequences/scenarios, comparators
  11. 11. Minus PointsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 11• Few good quality examples of more complex concepts• Those provided with the source code vary in style, quality anddocumentation level• OVM Forum examples can be hard to find• The Factory: where, when and how to use isn’t always obvious• The definition of a master / slave• Coverage / Covergroups• Statically defined• Goes against the factory based approach of OVM• Can make creating coverage base classes tricky• Flexibility of bin definitions• Multi-cycle coverage requires support code
  12. 12. Making the Switch Less PainfulCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 12
  13. 13. Making the Switch Less PainfulCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 13• Start from the bottom• A UVC doesn’t have to relate to a specific design block• Get your base classes right• There is no such thing as a “soft” constraint• It’s easier to add something than take it away• Randomized scenario driven verification over constrained random• Start with what the design has to achieve and work outwards. With the morelimited SystemVerilog constraints, this is a more natural fit• Combinatorial / multi-cycle interfaces are still awkward• Try and keep to a TLM even when the interface isn’t a simple fit• The print statement is your new best friend!
  14. 14. ConclusionsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 14
  15. 15. ConclusionsCopyright 2009 Icera Inc Andrew Bond DVClub 22nd April 2009 15• You can create an “Advanced Verification Environment” usingSystemVerilog and OVM as it stands today in roughly the sametimescales as other advanced verification languages• Part-time verification engineers do seem more comfortable creatingSystemVerilog infrastructure than with other advanced verificationlanguages• Vendor support is getting better• Yet to see the vendor-specific value-add• Yet to see how “Open” OVM really is• SystemVerilog / OVM is just a tool and not a miracle• There is no substitute for knowing what you are verifying and why
  16. 16. THANK YOUCopyright 2009 Icera Inc 16Andrew Bond DVClub 22nd April 2009

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