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© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 1Accelerated System DVThrough ReuseEdwar...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 2AgendaWhy Perform Multi-ASIC Simulation...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 3The RealityCisco is a large geographica...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 4System Level Bugs – Connection ErrorEac...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 5System-Level Bugs – Specification Misma...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 6ASIC DV Escape – Broad Input BehaviorNo...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 7Commonly Discovered System IssuesFIFO D...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 8AgendaWhy Perform Multi-ASIC Simulation...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 9System Simulation ChallengesTechnical i...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 10The ProblemHow do we rapidly get to mu...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 11Generic Testbench StructureDriversMoni...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 122-Chip Environment• Traditional 2-Chip...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 13Ideal 2-Chip EnvironmentSOCKETGoal reu...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 14SolutionSocketsim Tool – Chip-to-chip ...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 15AgendaWhy Perform Multi-ASIC Simulatio...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 16What is the Socketsim tool?PLI applica...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 17Socketsim toolSimilar to Avery Design ...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 18Socketsim PLISenderRegister callback o...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 19Socketsim Verilog instances – SPI4.2//...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 20More Socketsim FeaturesBidirectionals ...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 21AgendaWhy Perform Multi-ASIC Simulatio...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 22Testbench MethodologyBorrowed from Cad...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 23Mechanism for synchronizing test flowT...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 24Other Sideband SignalingMessaging Sema...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 25Passing Configuration via FileFile I/O...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 26Testbench Methodology SummaryRecommend...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 27AgendaWhy Perform Multi-ASIC Simulatio...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 28PerformanceAll ENVs slow down to slowe...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 29Performance AnalysisParameters which w...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 30AgendaWhy Perform Multi-ASIC Simulatio...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 31SummaryThe recommended testbench metho...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 32Related Documentationhttp://www.avery-...
© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 33
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Accelerated System DV Through Reuse

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Accelerated System DV Through Reuse

  1. 1. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 1Accelerated System DVThrough ReuseEdward Arthur/John Cashman/Tim Ganley/Mark StricklandCisco Systems, Inc.
  2. 2. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 2AgendaWhy Perform Multi-ASIC Simulation?The Challenges of Multi-ASIC SimulationThe Socketsim ToolThe Testbench MethodologyOther System Simulation ConsiderationsSummary
  3. 3. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 3The RealityCisco is a large geographically diverse companyLarge 10M+ gate ASICs are developed by different teamsEach team could (and probably will) have its own tool flow andmethodologySystem simulation typically occurs late in development cycleThe chips need need to interoperate!
  4. 4. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 4System Level Bugs – Connection ErrorEach ASIC works on its own, but is not connectedconsistently with the ASIC specs at the higher levelASICXASICYOut[1]Out[0]In[0]In[1]Problem
  5. 5. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 5System-Level Bugs – Specification MismatchEach component matches its spec, but system does notworktranslate inputvalue A tooutput value BSystem SpecASICXASICYSystem Block Diagramtranslate A to 5 translate 6 to BASIC X Spec ASIC Y SpecRTL TB= RTL TB=Sim OK Sim OKProblem
  6. 6. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 6ASIC DV Escape – Broad Input BehaviorNot all combinations of possible input space were triedin ASIC DV; specific behavior from source ASIC causesa problemASIC X SpecA5 clocksB12 clocksCThis combination nottested in DV for Y andreveals a bugASICXASICYASIC Y SpecA1 to 200 clocksB1 to 200 clocksCABC40,000 timingcombinations
  7. 7. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 7Commonly Discovered System IssuesFIFO Depth Assumptions – e.g. SPI4.2 LMax on/offPhysical layer interface interoperability – e.g. FlowControlInternal header transport and signaling protocolinteroperability – e.g. Priority bit interpretationReset SequencePerformanceValidation of end-to-end flow control
  8. 8. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 8AgendaWhy Perform Multi-ASIC Simulation?The Challenges of Multi-ASIC SimulationThe Socketsim ToolThe Testbench MethodologyOther System Simulation ConsiderationsSummary
  9. 9. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 9System Simulation ChallengesTechnical issues– System resources (memory)– Different high-level verification languages (HVLs)– Encrypted IP tied to specific simulators– Porting a design to a different simulator– Different versions of the same HVLs or simulators– Operating System dependencies– Work around language issues
  10. 10. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 10The ProblemHow do we rapidly get to multi-ASIC simulation?
  11. 11. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 11Generic Testbench StructureDriversMonitorsScoreboardDUTTestbenchEnvironment (ENV)Running on asingle system(SYS)ScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFM
  12. 12. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 122-Chip Environment• Traditional 2-Chip Environment would take too mucheffort (i.e. combining testbenches, re-architecting ENVs)ScoreboardENVDUTSYSdrivermonitorBFMdrivermonitorBFMScoreboardENVDUT1SYSDUT2drivermonitorBFMdrivermonitorBFMdrivermonitorBFMScoreboardENVDUTSYSdrivermonitorBFMdrivermonitorBFM
  13. 13. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 13Ideal 2-Chip EnvironmentSOCKETGoal reuse as much a possibleA socket accomplishes this goal!• Maintain ENV and SYS of both simulationsScoreboardENV1DUT1drivermonitorBFMSYS1drivermonitorBFMScoreboardENV2DUT2drivermonitorBFMSYS2drivermonitorBFM
  14. 14. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 14SolutionSocketsim Tool – Chip-to-chip interfacescommunicate over socketsTestbench Methodology – Chip-leveltestbenches written for reuse at system-level
  15. 15. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 15AgendaWhy Perform Multi-ASIC Simulation?The Challenges of Multi-ASIC SimulationThe Socketsim ToolThe Testbench MethodologyOther System Simulation ConsiderationsSummary
  16. 16. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 16What is the Socketsim tool?PLI application which monitors Verilog signals andpropagates signal changes across sockets betweenenvironmentsProvides virtual wires between two testbenches running ondifferent systemsEach environment syncs up each “heartbeat”VerilogVPI – PLIMPICHMPICHVPI – PLIVerilogsocket
  17. 17. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 17Socketsim toolSimilar to Avery Design SimCluster toolhttp://www.avery-design.com~2,800 lines of C/C++ codeMPI underneath (MPICH 1.2.5.2)VCS (V7.2R18+) and NC (5.3+) supportedLinux and Solaris supportedNo additional license required ☺VerilogVPI – PLIMPICHMPICHVPI – PLIVerilogsocket
  18. 18. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 18Socketsim PLISenderRegister callback onchanges of inputs to socketSave all changes up to deltacycleReceiverReplay changes on outputsof socket applying at eachtime sliceImplied wire delay oversocket equal to delta cycleSENDER:@heartbeatsend bufferto remote hostRECEIVER:Blocks waitingfor buffer,playbackchangesSENDER:@signal changesave value/timeto buffer
  19. 19. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 19Socketsim Verilog instances – SPI4.2// “Left ASIC” sidesocketsim #(.IN_WIDTH(20),.OUT_WIDTH(20))socket(.ins({tb_spi_tx_data[15:0],tb_spi_tx_ctl,tb_spi_rx_stat[1:0],tx_sync}),.outs({tb_spi_rx_data[15:0],tb_spi_rx_ctl,tb_spi_tx_stat[1:0],rx_sync}));// “Right ASIC” sidesocketsim #(.OUT_WIDTH(20),.IN_WIDTH(20))socket(.outs({NpRxData[15:0],NpRxControl,NpTstat[1:0],rx_sync}),.ins({NpTxData[15:0],NpTxControl,NpRstat[1:0],tx_sync}));
  20. 20. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 20More Socketsim FeaturesBidirectionals supportedHeartbeat user configurable at runtimeMultiple point-to-point connections allowedChipA has interfaces to ChipB and ChipCCompression supported for wiiiiiiiiiiiiiide busesPeers communicate directlyHVL↔HVL communicationUse Verilog tasks as wrappers for signals which cross the socket
  21. 21. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 21AgendaWhy Perform Multi-ASIC Simulation?The Challenges of Multi-ASIC SimulationThe Socketsim ToolThe Testbench MethodologyOther System Simulation ConsiderationsSummary
  22. 22. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 22Testbench MethodologyBorrowed from Cadence eRM methodologyDecouple BFM’s driver from scoreboardBFM’s drivers should not put objects onto scoreboardMonitors watch wires in both directions and forward informationto scoreboardSOCKETScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFMScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFMPut these local drivers in PASSIVE mode
  23. 23. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 23Mechanism for synchronizing test flowTestflow synchronization – sync upthe various phases of eachenvironment with sideband signalPhases will have differentdurationsReset()Init()Main()Post()End()ENV1Reset()Init()Main()Post()End()ENV2End SimulationStart SimulationSocket
  24. 24. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 24Other Sideband SignalingMessaging Semaphore – besides the data/control signals that passacross the socket, pass sideband signals during test forconfiguration, special event or sequence (i.e. backpressure event,register sequence)BackpressureeventcfginformationSOCKETScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFMScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFMSequencedriverSequencedriver
  25. 25. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 25Passing Configuration via FileFile I/O - for on-the-fly configuration synchronizationBoth ENVs could read common fileOne ENV could write cfg, the other read itWrite_ascii_struct() Read_ascii_struct()ScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFMScoreboardENVDUTdrivermonitorBFMSYSdrivermonitorBFMSequencedriverSequencedriverSOCKET
  26. 26. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 26Testbench Methodology SummaryRecommended testbench methodology for multi-ASICsystem simulation:Each BFM’s driver should not put objects onto scoreboardEach BFM’s driver can be turned off (passive mode)Monitors will simply place data objects on the scoreboardScoreboard uses data objects from monitors, system state andtransfer function to generate expected results
  27. 27. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 27AgendaWhy Perform Multi-ASIC Simulation?The Challenges of Multi-ASIC SimulationThe Socketsim ToolThe Testbench MethodologyOther System Simulation ConsiderationsSummary
  28. 28. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 28PerformanceAll ENVs slow down to slowest ENV + overhead10%-40% slowdown seen– Each environment must sync up every heartbeat which pegsperformance to the slowest environment– Additional overhead comes from message passing overnetwork
  29. 29. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 29Performance AnalysisParameters which will affect performanceMultiprocessor serverCache thrashingMemory contentionCPUs of same speedHeartbeat durationVarying amount work/heartbeatHow many socketsSocket widthStartup time (compile/load/init/…)More work needs to be done – we’ve only skimmed the surface
  30. 30. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 30AgendaWhy Perform Multi-ASIC Simulation?The Challenges of Multi-ASIC SimulationThe Socketsim ToolThe Testbench MethodologyOther System Simulation ConsiderationsSummary
  31. 31. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 31SummaryThe recommended testbench methodology (CadenceeRM) enables efficient chip-level testbench reuse at thesystem-levelSocketsim solves the problem of connecting chip-levelenvironments to form system-level environments- certain environments can only be simulated this way
  32. 32. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 32Related Documentationhttp://www.avery-design.com (SimCluster tool)http://web.archive.org/web/20060429011636/http://www.avery-design.com/web/avery_hdlcon02.pdf (Paper describing socket simulationtechniques)
  33. 33. © 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 33

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