Real-Time Performance and Voice Quality on Single Core RISC ...

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  • Real-Time Performance and Voice Quality on Single Core RISC ...

    1. 1. Getting Real-time Performance and Voice Quality on Single Core RISC Devices Matt Randmaa, VP of Engineering D2 Technologies www.d2tech.com
    2. 2. Presentation Outline <ul><li>VoIP Endpoint Device Software Overview </li></ul><ul><ul><li>VoIP Endpoint Example, Functionality, Software Blocks </li></ul></ul><ul><ul><li>Traditional Software Architecture (RISC + DSP) </li></ul></ul><ul><ul><li>New Software Architecture – VoIP on RISC </li></ul></ul><ul><li>Real-time requirements in VoIP </li></ul><ul><ul><li>Hard Real-Time, Soft Real-Time, Best Effort </li></ul></ul><ul><li>RISC SoC Design Considerations </li></ul><ul><li>Toolchain/BSP Considerations </li></ul><ul><li>Software Design Considerations </li></ul><ul><li>Conclusion </li></ul>
    3. 3. VoIP Endpoint Example: Analog Telephony Adaptor (ATA) <ul><li>Ethernet to FXS adaptor </li></ul><ul><ul><li>Optional second Ethernet port for bridging/routing; FXO for PSTN </li></ul></ul><ul><li>Enables a POTS phone to make VoIP calls </li></ul><ul><ul><li>May support FAX </li></ul></ul><ul><li>SIP User Agent application </li></ul><ul><ul><li>Uses SIP protocol to establish calls </li></ul></ul><ul><li>Implements many CLASS features </li></ul><ul><ul><li>Call Waiting, Caller ID, 3-way Calling, Call Transfer, Call Forwarding, etc </li></ul></ul>
    4. 4. Other Endpoint examples <ul><li>SOHO Router with VoIP </li></ul><ul><li>WIFI AP with VoIP </li></ul><ul><li>WIFI ATA </li></ul><ul><li>WIFI handset </li></ul><ul><li>Dual mode phones </li></ul><ul><li>VoIP enabled PDAs, Game Units, MP3 players, iPods </li></ul><ul><li>Etc etc. </li></ul>
    5. 5. Legacy HW/SW Architecture: RISC + DSP <ul><li>RISC Processor Responsible for: </li></ul><ul><li>Voice Application, Protocol </li></ul><ul><li>IP Stack, Data/Voice Packets </li></ul><ul><li>DSP Driver </li></ul><ul><li>DSP Processor Responsible for: </li></ul><ul><li>Hard real-time telephony interface </li></ul><ul><li>DSP algorithms (MHz intensive) </li></ul><ul><li>Separate DSP application </li></ul><ul><ul><li>Required to be semi-autonomous </li></ul></ul>
    6. 6. New SW/HW Architecture: Single CPU
    7. 7. Single CPU Advantages / Challenges <ul><li>Advantages: </li></ul><ul><ul><li>Eliminates DSP </li></ul></ul><ul><ul><li>Leverages existing SoC chips </li></ul></ul><ul><ul><li>No Interprocessor communication </li></ul></ul><ul><ul><li>Single Tools / Development Environment </li></ul></ul><ul><li>Challenges: </li></ul><ul><ul><li>Hard real-time requirements </li></ul></ul><ul><ul><li>MHz burden on RISC </li></ul></ul><ul><ul><li>Data/Voice/Application software must co-exist </li></ul></ul><ul><ul><li>Telephony interface peripheral </li></ul></ul>
    8. 8. Real-time Requirements in VoIP <ul><li>VoIP Endpoint Device Software Overview </li></ul><ul><ul><li>VoIP Endpoint Examples, Functionality, Software Blocks </li></ul></ul><ul><ul><li>Traditional Software Architecture (RISC + DSP) </li></ul></ul><ul><ul><li>New Software Architecture – VoIP on RISC </li></ul></ul><ul><li>Real-time requirements in VoIP </li></ul><ul><ul><li>Hard Real-Time, Soft Real-Time, Best Effort </li></ul></ul><ul><li>RISC SoC Design Considerations </li></ul><ul><li>Toolchain/BSP Considerations </li></ul><ul><li>Software Design Considerations </li></ul><ul><li>Conclusion </li></ul>
    9. 9. Information Flow in VoIP
    10. 10. Hard Real-Time in VoIP <ul><li>Hard Real-Time: Deadline-based processes in which a failure to meet the deadline will result in loss of voice data and unacceptable system behavior. </li></ul><ul><li>Hard real-time requirements in VoIP: </li></ul><ul><ul><li>Telephony Driver </li></ul></ul><ul><ul><li>DSP Algorithms </li></ul></ul>
    11. 11. Hard Real-Time Requirement: Telephony Driver <ul><li>Telephony Driver: Transmits voice samples to/from the hardware CODEC </li></ul><ul><li>Nature of communication: Synchronous serial interface, 64 _ kbps per channel </li></ul><ul><ul><li>8000 samples/s, 8 bits/sample </li></ul></ul><ul><ul><li>One sample transmitted/received every 125 us </li></ul></ul>
    12. 12. Hard Real-Time Requirement: Telephony Driver (continued) <ul><li>Failure in copying in/out each sample before the 125 _ us deadline results in dropping a voice sample. </li></ul><ul><ul><li>Resulting impacts on voice quality </li></ul></ul><ul><ul><ul><li>Can be a noticeable click. </li></ul></ul></ul><ul><ul><ul><li>Echo canceller can fail, resulting in perceptible echo to far end. </li></ul></ul></ul><ul><ul><ul><li>FAX pass-through or FAX Relay can fail. </li></ul></ul></ul><ul><ul><ul><li>Causes drift in jitter buffers, which will may cause dropped packets </li></ul></ul></ul><ul><ul><li>If subsequent deadlines are missed (domino effect), call failure and system instability can result. </li></ul></ul>
    13. 13. Hard Real-Time Requirement: DSP Algorithms <ul><li>DSP Algorithms in ATA: Process the voice stream from Telephony Driver and from IP stack to do: </li></ul><ul><ul><li>Voice Compression </li></ul></ul><ul><ul><li>Echo Cancellation </li></ul></ul><ul><ul><li>Tone Generation / Detection </li></ul></ul><ul><ul><ul><li>DTMF, FAX/Modem, Call Progress, Caller ID </li></ul></ul></ul><ul><ul><li>Packet Loss Compensation </li></ul></ul><ul><li>Nature of communication: Block based processing </li></ul><ul><ul><li>Typically 80 voice samples per block </li></ul></ul><ul><ul><li>One block processed every 10 ms </li></ul></ul>
    14. 14. Hard Real-Time Requirement: DSP Algorithms (continued) <ul><li>Failure in completing DSP algorithm processing by the end of the 10 ms deadline results in: </li></ul><ul><ul><li>Telephony driver will play out old data to hardware CODEC. </li></ul></ul><ul><ul><li>Far side also gets bad data due to loss of codec data. </li></ul></ul><ul><ul><li>Echo canceller can diverge, causing echo to be heard on subsequent blocks. </li></ul></ul><ul><ul><li>Tone detection can fail, resulting in mis-detection of DTMF digits or FAX tones. </li></ul></ul><ul><ul><li>Again, if subsequent deadlines are missed (domino effect), call failure and system instability can result. </li></ul></ul>
    15. 15. Soft Real-Time in VoIP <ul><li>Soft Real-Time: Processes which should execute in a timely manner, for which system behavior degrades (but may not be unacceptable) if the deadline is missed. </li></ul><ul><li>Soft real-time requirements in VoIP: </li></ul><ul><ul><li>Voice Packetization and Transport </li></ul></ul><ul><ul><li>Voice Application and Protocol </li></ul></ul>
    16. 16. Soft Real-Time Requirement: Voice Packetization and Transport <ul><li>Voice packetization and transport: Packetize the compressed audio and send it out the IP interface; alternatively, receive a packet from the IP interface and provide it to the VoIP software. </li></ul><ul><li>Nature of communication: </li></ul><ul><ul><li>Transmission: Normally, one packet ready every 10, 20, or 30 ms. </li></ul></ul><ul><ul><li>Reception: Subject to network jitter, one every 10, 20, or 30 ms. </li></ul></ul><ul><li>Deadline for processing: </li></ul><ul><ul><li>Processing should complete within the packet duration (10, 20, 30 ms), in order to keep from getting behind. </li></ul></ul>
    17. 17. Soft Real-Time Requirement: Voice Packetization and Transport (continued) <ul><li>Repercussions of failure to meeting deadline: </li></ul><ul><ul><li>May be handled by the Jitter Buffer on the receiving side. </li></ul></ul><ul><ul><li>Best-case </li></ul></ul><ul><ul><ul><li>Missing deadline causes jitter buffer to grow, but does not cause lost packets; Results in increased latency because of a larger jitter buffer. </li></ul></ul></ul><ul><ul><li>Worst-case </li></ul></ul><ul><ul><ul><li>Missing deadline causes jitter buffer to discard a too-late packet; Packet loss compensation used to minimize impact on voice quality. </li></ul></ul></ul>
    18. 18. Soft Real-Time Requirement: Voice Application and Protocol <ul><li>Nature of communication: </li></ul><ul><ul><li>Responds to reception of SIP packets, telephony events, and internal timers in order to drive Telephony Application functionality. </li></ul></ul><ul><li>Deadline for processing: </li></ul><ul><ul><li>Processing should be responsive enough for successful user experience. </li></ul></ul><ul><ul><li>Certain time-outs exist in SIP; however, retransmission techniques in the protocol allow recovery of some missed deadlines. </li></ul></ul>
    19. 19. Soft Real-Time Requirement: Voice Application and Protocol (continued) <ul><li>Repercussions of failure to meeting deadline: </li></ul><ul><ul><li>Noticeable lack of responsiveness of device. </li></ul></ul><ul><ul><li>Call failures are possible for excessive delays. </li></ul></ul><ul><li>However, voice application and protocol deadlines are typically on the order of hundreds of milliseconds to several seconds. </li></ul><ul><ul><li>As long as the Voice Application and Protocol are not blocked indefinitely, they should meet timing requirements. </li></ul></ul>
    20. 20. Best Effort in VoIP <ul><li>Best Effort: Processes for which there is no deadline, but for which faster execution results in better system performance. </li></ul><ul><li>Best Effort requirements in VoIP: </li></ul><ul><ul><li>Data IP Packet Transport </li></ul></ul>
    21. 21. Best Effort Requirement: Data Packet IP transport <ul><li>Data Packet IP transport: Process the reception, transmission, forwarding, and bridging of TCP packets. </li></ul><ul><li>Nature of communication: </li></ul><ul><ul><li>Packets can be received at wireline speeds (e.g. 100 Mbps). </li></ul></ul><ul><ul><li>Device processes as many packets as it can, discarding others. </li></ul></ul><ul><li>Deadline for processing: </li></ul><ul><ul><li>No deadline for processing, other than TCP ACK timeout. </li></ul></ul><ul><li>Repercussions of failure to meeting deadline: </li></ul><ul><ul><li>TCP packets retransmitted. </li></ul></ul><ul><ul><li>Lower data bandwidth. </li></ul></ul><ul><li>These repercussions are intentional and acceptable. </li></ul>
    22. 22. Implications of Real-time Requirements <ul><li>A VoIP device has multiple processes with different MHz consumption and real-time needs. </li></ul><ul><li>This places stringent requirements on the OS, BSP, Memory, Cache, other software running on the RISC core, and the SoC design itself. </li></ul><ul><ul><li>Each of these areas needs careful consideration. </li></ul></ul><ul><li>This requires a system-wide approach rather than ad-hoc optimization of each piece. </li></ul>
    23. 23. RISC SoC Design Considerations <ul><li>VoIP Endpoint Device Software Overview </li></ul><ul><ul><li>VoIP Endpoint Examples, Functionality, Software Blocks </li></ul></ul><ul><ul><li>Traditional Software Architecture (RISC + DSP) </li></ul></ul><ul><ul><li>New Software Architecture – VoIP on RISC </li></ul></ul><ul><li>Real-time requirements in VoIP </li></ul><ul><ul><li>Hard real-time, soft real-time, best effort </li></ul></ul><ul><li>RISC SoC Design Considerations </li></ul><ul><li>Toolchain/BSP Considerations </li></ul><ul><li>Software Design Considerations </li></ul><ul><li>Conclusion </li></ul>
    24. 24. RISC SoC Design Considerations <ul><li>If VoIP requirements are taken into consideration at SoC design time, changes to the SoC design can result in improved VoIP system performance. </li></ul><ul><li>Areas of importance for VoIP: </li></ul><ul><ul><li>Cache size and type </li></ul></ul><ul><ul><li>Memory bandwidth </li></ul></ul><ul><ul><li>On-chip scratch memory </li></ul></ul><ul><ul><li>Telephony Interface Hardware </li></ul></ul>
    25. 25. Cache size and type, and its effect on G.729AB MHz performance
    26. 26. Memory bandwidth and its effect on G.729AB MHz performance
    27. 27. On-chip scratch memory and its effect on VoIP performance <ul><li>Use of on-chip SRAM can speed system performance by preventing cache miss penalties. </li></ul><ul><li>With a large enough on-chip SRAM, significant savings can result (>30%). </li></ul><ul><li>However, the software has to be modified to take advantage of on-chip SRAM. </li></ul>
    28. 28. Telephony Interface Hardware: SoC’s Without a TDM port <ul><li>Currently most RISC based SoCs have no synchronous serial interface appropriate for CODECs. </li></ul><ul><ul><li>VoIP designs require a CPLD, increasing Bill of Materials (BOM). </li></ul></ul><ul><ul><li>Minimization of CPLD size will consume more MHz. </li></ul></ul><ul><li>Costs to support 2-channel telephony interface: </li></ul><ul><ul><li>> $.50 CPLD cost </li></ul></ul><ul><ul><li>~10 MHz consumed by telephony interface software </li></ul></ul><ul><ul><li>More complicated Board and Software design </li></ul></ul>
    29. 29. SoC’s With a TDM port <ul><li>The next generation of VoIP-capable RISC chips add: </li></ul><ul><ul><li>Telephony interface </li></ul></ul><ul><ul><li>DMA capabilities </li></ul></ul><ul><li>Benefits of using TDM/DMA for 2-channel telephony interface: </li></ul><ul><ul><li>< $.10 to add TDM port to SoC </li></ul></ul><ul><ul><li>~1 MHz consumed by telephony interface software </li></ul></ul><ul><ul><li>Real-time deadline loosened from 125 us to as high as 10 ms. </li></ul></ul><ul><ul><li>Simpler Board and Software design </li></ul></ul>
    30. 30. Toolchain / BSP Considerations <ul><li>VoIP Endpoint Device Software Overview </li></ul><ul><ul><li>VoIP Endpoint Examples, Functionality, Software Blocks </li></ul></ul><ul><ul><li>Traditional Software Architecture (RISC + DSP) </li></ul></ul><ul><ul><li>New Software Architecture – VoIP on RISC </li></ul></ul><ul><li>Real-time requirements in VoIP </li></ul><ul><ul><li>Hard real-time, soft real-time, best effort </li></ul></ul><ul><li>RISC SoC Design Considerations </li></ul><ul><li>Toolchain/BSP Considerations </li></ul><ul><li>Software Design Considerations </li></ul><ul><li>Conclusion </li></ul>
    31. 31. Toolchain / BSP Considerations: RTOS <ul><li>OS requirements: </li></ul><ul><ul><li>Guaranteed worst-case task switch latency that meets the VoIP latency deadlines. </li></ul></ul><ul><ul><li>A preemptive kernel. </li></ul></ul><ul><ul><li>A scheduler that prioritizes real-time tasks above non real-time tasks. </li></ul></ul><ul><li>Examples: </li></ul><ul><ul><li>Wind River VxWorks </li></ul></ul><ul><ul><li>MontaVista Linux (contains real-time improvements in the 2.6 Linux kernel) </li></ul></ul><ul><ul><li>Others (Nucleus, SuperTask, eCOS) </li></ul></ul>
    32. 32. Toolchain / BSP Considerations: RTOS (continued) <ul><li>Final OS choice involves cost tradeoffs: </li></ul><ul><ul><li>License/royalty cost </li></ul></ul><ul><ul><li>Flash / Memory footprint. </li></ul></ul><ul><ul><li>Strong Tools Development Environment. </li></ul></ul><ul><ul><li>Bundled network/application software can lower development costs. </li></ul></ul>
    33. 33. Toolchain / BSP Considerations: Optimizing Compiler
    34. 34. Toolchain / BSP Considerations: Peripheral Drivers <ul><li>Peripheral drivers (Ethernet, Serial, USB, etc) may have a hard real-time impact on Voice software: </li></ul><ul><ul><li>Peripheral ISR’s can hold off tasks past deadlines. </li></ul></ul><ul><li>To avoid this, peripheral drivers may have to be modified to: </li></ul><ul><ul><li>Separate the time critical portions of the driver from portions that can be run at lower priority. </li></ul></ul><ul><ul><li>Minimize the task latency imposed on real-time VoIP processes due to ISR’s. </li></ul></ul>
    35. 35. Software Design Considerations <ul><li>VoIP Endpoint Device Software Overview </li></ul><ul><ul><li>VoIP Endpoint Examples, Functionality, Software Blocks </li></ul></ul><ul><ul><li>Traditional Software Architecture (RISC + DSP) </li></ul></ul><ul><ul><li>New Software Architecture – VoIP on RISC </li></ul></ul><ul><li>Real-time requirements in VoIP </li></ul><ul><ul><li>Hard real-time, soft real-time, best effort </li></ul></ul><ul><li>RISC SoC Design Considerations </li></ul><ul><li>Toolchain/BSP Considerations </li></ul><ul><li>Software Design Considerations </li></ul><ul><li>Conclusion </li></ul>
    36. 36. Software Design Considerations <ul><li>VoIP Software Partitioning </li></ul><ul><ul><li>VoIP software should be partitioned into different tasks based on priority, not function. </li></ul></ul><ul><ul><li>This minimizes the MHz consumed in hard real-time tasks </li></ul></ul><ul><ul><ul><li>This decreases negative effects due to the latency it imposes on other tasks. </li></ul></ul></ul>
    37. 37. Software Design Considerations, continued <ul><li>Task Priority Organization </li></ul><ul><ul><li>Care has to be taken to make the optimal priority assignments for each task. </li></ul></ul><ul><ul><ul><li>Sub-optimal assignment of task priorities can easily result in 40% higher MHz load due to the creation of unnecessary task switching. </li></ul></ul></ul>
    38. 38. Conclusion <ul><li>Single-core RISC SoC’s are the new approach for low-cost VoIP endpoints. </li></ul><ul><li>Combining Voice, Data, and Application Software has challenges. </li></ul><ul><li>A strong systems-level approach is required to conquer the challenges. </li></ul>
    39. 39. Questions… Thank You.

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