UFS has very low pin count, as depicted in this slide. It has two wires for Tx, two wires for Rx, and reset and clock pin.For UFS controller implementation, you have UFS host and UFS device.On the host side, there is the physciallayer with UFS M-PHY. The core logic includes the UniPro functions. Connecting the core logic to the core processor is the HCI, host controller interface. HCI is also defined by JEDEC.On the device side, it has the same UFS M-PHY and similar core logic with the UniPro function. It also has the NAND flash memory controller with interface to NAND flash.Device side
To maximize reusability, UFS adopted a layered architecture to include three major layers. At the physical layer, the interconnect layer connects electrically the UFS host and UFS device.Transport Layer is responsible for encapsulating the protocol into the appropriate frame structure for the interconnect layer.At the software application layer, the command set layer incorporate the SCSI standard as the baseline protocol for UFS specification.Let’s take a look of what UniPro does. UniPro stands for Universal Protocol defined by MIPI. UniPro has four layers, L1.5 the PHY adapter, L2 the data link layer, L3, the network layer, and L4, the transport layer.