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SCHEMATIC           REV             PB NUMBER         VER        BOM RELEASE DATE                                         ...
RJ45/USB                                  AVIP      CONN                                      CONN                        ...
RJ45/USB                                                                         AVIP     CONN                            ...
56                                      CPU_RST_V1P1_N                                                                    ...
CPU,           FSB                                                                               U7D1                     ...
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Diagrama-xbox360

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Mapas de distintas placas de xbox 360

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Diagrama-xbox360

  1. 1. SCHEMATIC REV PB NUMBER VER BOM RELEASE DATE K7 X803600-011 RETAIL XX/XX/XXPAGE CONTENTS PAGE CONTENTS [1] COVER PAGE [33] SB, PCIEX + SMM GPIO + JTAG [2] CLOCK DIAGRAM [34] SB, SMC [3] RESET/ENABLE DIAGRAM [35] SB, FLASH + USB + SPI [4] CPU, CLOCKS + EEPROM + STRAPPING [36] SB, ETHERNET + AUDIO + SATA [5] CPU, FSB [37] SB, STANDBY POWER + DECOUPLE XENON [6] CPU, FSB POWER + PLL POWER [38] SB, MAIN POWER + DECOUPLE [7] CPU, CORE POWER [39] SB OUT, ETHERNET [8] CPU, POWER [40] SB OUT, AUDIO [9] CPU, DECOUPLING [41] SB OUT, FLASH[10][11][12] CPU, DECOUPLING CPU, DECOUPLING GPU, FSB [42] [43] [44] SB OUT, FAN + INFRARED + BUTTONS CONN, AVIP CONN, RJ45 + USB COMBO RETAIL[13][14] GPU, VIDEO + PCIEX + EEPROM GPU, MEMORY CONTROLLER A + B [45] [46] CONN, GAME PORTS + MEMORY PORTS BACKUP CLOCK + V_5P0 DUAL REV K7[15][16] GPU, MEMORY CONTROLLER C + D GPU, PLL POWER + FSB POWER [47] [48] CONN, ODD AND HDD CONN, ARGON + POWER FAB K[17] GPU, CORE POWER + MEM POWER [49] VREGS, INPUT + OUTPUT FILTERS[18] GPU, DECOUPLING [50] VREGS, CPU CONTROLLER[19] DUAL ETHERNET PHY [51] VREGS, GPU OUTPUT PHASE 1,2,3[20] MEMORY, A (TOP) [52] VREGS, GPU CONTROLLER[21] MEMORY, A MIRRORED (BOTTOM) [53] VREGS, GPU OUTPUT PHASE 1,2[22] MEMORY, B (TOP) [54] VREGS, SWITCHED 1.8, 5.0V[23] MEMORY, B MIRRORED (BOTTOM) [55] VREGS, LINEAR REGULATORS[24] MEMORY, C (TOP) [56] XDK, DEBUG CONN[25] MEMORY, C MIRRORED (BOTTOM) [57] DEBUG BOARD, CPU + GPU BREAKOUT[26] MEMORY, D (TOP) [58] DEBUG BOARD, CPU CONN[27] MEMORY, D MIRRORED (BOTTOM) [59] DEBUG BOARD, CPU CONN + TERM[28] ANA, CLOCKS + STRAPPING [60] DEBUG BOARD, CPU TERM[29] ANA, VIDEO + FAN + JTAG [61] DEBUG BOARD, TITAN + YETI CONN[30] ANA, POWER + DECOUPLING [62] DEBUG BOARD, GPU CONN + TERM[31] DEBUG MAPPING, WN DBG VS WN XDK [63] XDK, LEDS[32] POWER TRACE EMI CAPS [64] LABELS AND MOUNTINGRULES:1.)2.)3.) (APPLIED WHEN POSSIBLE) MSB TO LSB IS TOP TO BOTTOM WHEN POSSIBLE: INPUTS ORDER OF PAGES=CHIP ON LEFT, INTERFACES, OUTPUTS ON RIGHT TERMINATION, POWER, DECOUPLING PLEASE REFER XENONTO THE XENON DESIGN SPEC4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS5.) LANED SIGNALS ARE GROUPED ON SYMBOLS6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS BOM RELEASE DATE XX/XX/XX PB NUMBER X803600-0119.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE SIGNATURE DATE10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION12.)13.) SUFFIX SUFFIX _P FOR P JUNCTION _EN FOR ENABLE DRN BY MICROSOFT XBOX14.) CLK FOR CLOCKS, RST FOR RESETS CHK BY TITLE15.) PWRGD FOR POWER GOOD SCH, PBA, XENON ENGR APVD DRAWING PROJECT NAME PAGE REV XENON_FABK APVD MICROSOFT[PAGE_TITLE=COVER PAGE] Wed Aug 24 09:41:55 2005 APVD CONFIDENTIAL XENON_RETAIL 1/73 K7
  2. 2. RJ45/USB AVIP CONN CONN POWER FAN CONN CONN ENET ENET_CLK(25MHZ) CLOCK DIAGRAM PHY I2S_MCLK(12.288MHZ) AUDIO ANA_XTAL_IN(27MHZ) I2S_BCLK(3.072MHZ) DAC GPU VR DEBUG CONN ANA ANA BCKUP STBY_CLK(48MHZ) GPU VR CNTL SB SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) DVD PCIEX_CLK_DP/DN(100MHZ) SATA AUD_CLK(24.576MHZ) CONN CPU_CLK_DP/DN(100MHZ) RISCWATCH PIX_CLK_OUT_DP/DN(100MHZ) CONN GPU_CLK_DP/DN (100MHZ) DVD PWR CONN MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ) ANA BCKUP MEM CLAM C+D MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ) GPU CPU CPU VR MA_CLK1_DP/DN(800MHZ) MA_CLK0_DP/DN(800MHZ) MB_CLK1_DP/DN(800MHZ) MB_CLK0_DP/DN(800MHZ) 1P8 VR FLSH HDD CONN TITAN JTAG 3P3 VR CONN VMEM VR MEM EFUSE VR CLAM A+B CPU VR 5P0 VR CNTL MPORT VR GAME CONN IR EJECT MEM MEM BIND ARGON SW CONN CONN SW CONN DRAWING PROJECT NAME PAGE REV XENON_FABK MICROSOFT<PAGE_TITLE=CLOCK DIAGRAM> Wed Jul 27 21:53:30 2005 XENON_RETAIL 2/73 K7 CONFIDENTIAL
  3. 3. RJ45/USB AVIP CONN CONN POWER FAN CONN CONN RESET/ENABLE DIAGRAM EXT_PWR_ON_N ENET AUD_CLAMP PHY ENET_RST_N AUDIO PSU_V12P0_EN AUD_RST_N DAC GPU VR ANA_CLK_OE ANA_RST_N ANA VREG_GPU_EN_N GPU VR CNTL SMC_RST_N SB_RST_N DVD SATA SB VREG_GPU_PWRGD EXT_PWR_ON_N CONN CPU_CHECKSTOP_N CPU_RST_N CPU_PWRGD GPU_RST_N RISCWATCH DVD GPU_RST_DONE CONN PWR SMC_DBG_EN CONN VREG_CPU_PWRGD MEM_RST CPU VREG_3P3_EN VR MEM_SCAN_EN MEM CLAM C+D MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN GPU CPU MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN MEM_SCAN_EN MEM_RST HDD 3P3 CONN VR CPU_PWRGD TITAN JTAG MEM CONN DEBUG CLAM A+B CONN VREG_1P8_EN_N VMEM VR EFUSE VR VREG_5P0_EN_N CPU VR 5P0 VR CNTL VREG_EFUSE_EN VREG_CPU_EN GAME CONN IR EJECT MEM MEM BIND ARGON SW CONN CONN SW CONN DRAWING PROJECT NAME PAGE REV MICROSOFT[PAGE_TITLE=RESET/ENABLE DIAGRAM] XENON_FABK Wed Jul 27 21:53:44 2005 CONFIDENTIAL XENON_RETAIL 3/73 K7
  4. 4. 56 CPU_RST_V1P1_N OUT CPU_RST_N 1 R7R4 2 CPU, CLOCKS + EEPROM + STRAPPING 34 IN 3.92K 1% 402 CH 1 46 IN CPU_CLK_DP 1 1 R7R16 2 C7R112 N: STUFF C?,C? WITH ZERO OHM RS FOR WN FT2P11 FTP 360PF N: STUFF C?,C? WITH .01UF CAPS FOR SHIVA 6.19K 1% 10% 1 50V FT2P12 FTP 402 CH 2 NPO 603 CPU_PWRGD 1 R7R10 2 CPU_PWRGD_V1P1_N 34 IN CPU_CLK_DN 46 IN 3.92K 1% 402 CH 1 V_GPUCORE 1 R7R11 2 C7R113 V_GPUCORE 360PF U7D1 1 OF 10 IC 6.19K 1% 10% V_GPUCORE 402 CH 50V TP7R1 2 NPO CPU VERSION 20 2 R6R4 1 603 PROBE AJ25 CORE_CLK_DP CORE_IF_BGR_PLL AK17 CPU_CORE_IF_BGR_PLL 1 1K 5% TP6D1 AH25 2 2 1 1 402 CH CORE_CLK_DN 1 PROBE R6D1 R6D2 1 931 1.07K R6R9 R6R6 2 AJ2 HARD_RESET_B EFU_POWERON C6 VREG_EFUSE_EN OUT 55 SMT 10K 2 R6R5 1 AF16 1% 1% 10K 5% POWER_GOOD 5% CH CH EMPTY 1K 5% SMT 402 402 CH 402 CH FSB_CLK_DP AK23 FSB_CLK_DP FSB_HF_CLKOUT_DP AH22 CPU_FSB_HF_CLKOUT_DP 1 2 402 FSB_CLK_DN CPU_FSB_HF_CLKOUT_DN OUT 402 2 AK22 FSB_CLK_DN FSB_HF_CLKOUT_DN AJ22 2 OUT CPU_FSB_CLK_SEL AG18 FSB_CLK_SEL FSB_IMPED_CAL_DP AK25 CPU_FSB_IMPED_CAL_DP FSB_IMPED_CAL_DN AK24 CPU_FSB_IMPED_CAL_DN CPU_EXT_CLK_EN AF18 EXT_CLK_EN 1 TP7R3 R6R8 CPU_PLL_BYPASS AH16 PROBE 1 PLL_BYPASS AK14 CPU_RES0_DP 1 10K RESISTOR0_DP 5% 1 RESISTOR0_DN AK15 CPU_RES0_DN 2 R6R7 CPU_PULSE_LIMIT_BYPASS AJ16 PULSE_LIMIT_BYPASS EMPTY 10K R7R17 TP7R4 402 5% 10K 1 1 R7R24 2 SMT PROBE 2 CPU_TRIGGER_IN AG16 TRIGGER_IN CH 5% R7D1 VDDS0_DP AH13 CPU_VDDS0_DP 1 402 CH 10K 5% VDDS0_DN AK12 CPU_VDDS0_DN 2 2 10K 402 CH TP7R2 402 5% V_GPUCORE PROBE 2 CH CPU_SYS_CONFIG0 AK3 SYS_CONFIG0 VDDS1_DP AJ4 CPU_VDDS1_DP SMT 1 402 CPU_SYS_CONFIG1 AH1 SYS_CONFIG1 VDDS1_DN AK5 CPU_VDDS1_DN 2 2 CPU_POST_IN<0..4> SMT DB7R1 0 AH10 POST_IN0 TP OUT 1 AJ10 POST_IN1 CPU_PSRO0_OUT 1 1 PSRO0_OUT AK16 1 2 AK9 POST_IN2 R7R15 R7R8 TP6R1 3 AK10 POST_IN3 10K 10K PROBE 1 4 AK11 POST_IN4 5% 5% 1 2 CPU_ANL_1 R7R9 EMPTY EMPTY 10K 402 402 SMT 5% 2 2 4 IN CPU_SPI_SI B3 SPI_SI SPI_CLK A2 CPU_SPI_CLK OUT 4 B2 CPU_SPI_EN CH LAYOUT: MUST BE ACCESSIBLE SPI_EN OUT 4 402 1 2 R6R10 1 SPI_SO A3 CPU_SPI_SO 4 2 2 C6R46 CPU_ANL_1_R OUT 1 10UF R6E1 1 10% 5.11K 1% TEMP_P AK20 CPU_TEMP_P 29 R7R6 6.3V 402 EMPTY IN 10K 10K 2 AG24 ANL_1 TEMP_N AK21 CPU_TEMP_N 29 5% R7R7 EMPTY OUT 5% 10K 1206 CPU_ANL_2 AF24 ANL_2 CH CH 5% VID0 C4 CPU_VREG_APS0 OUT 49 402 402 CPU_SPARE0 AK1 B5 CPU_VREG_APS1 1 CH SPARE0 VID1 OUT 49 2 402 TP6R2 CPU_SPARE1 AJ1 A4 CPU_VREG_APS2 SPARE1 VID2 OUT 49 2 PROBE VID3 B4 CPU_VREG_APS3 49 1 2 CPU_VREG_APS4 OUT CPU_TEST_EN AH4 TE VID4 A5 49 V_GPUCORE OUT SMT VID5 C5 CPU_VREG_APS5 OUT 49 1 1 1 FTP FT7T5 R7R14 X02046-002 1 FTP FT7T2 1 FTP FT7T4 10K J7F1 1 FTP FT7T1 1 FTP FT7T3 5% 2X3HDR FTP FT7T7 1 1 1 1 1 1 1 CH 1 2 CPU_SPI_SI R7R1 R7R2 402 OUT 4 R7R21 R7R12 R7R13 R7R22 R7R23 0 0 2 3 4 CPU_SPI_WP_N OUT 4 V_MEM V_MEM 10K 10K 10K 10K 10K 5% 5% 5 6 5% 5% 5% 5% 5% EMPTY EMPTY CH CH CH CH CH 402 402 EMPTY 402 402 402 402 402 2 2 2 2 2 2 2 1 1 V_MEM C6F1 .1UF R7F3 0 1 2 3 4 10% 10K U7E1 IC 6.3V 2 X5R 5% 1 1 1 1 1 AT25020A 402 EMPTY CPU_SPI_CLK R6E2 CPU_SPI_CLK_R 6 8 402 4 IN SCK VCC R7R20 R7R5 R7R3 R7R19 R7R18 CPU_SPI_SO_R 5 SDI 2 1K 5% 2 R7F7 1 10K 10K 10K 10K 10K 402 CH SDO 2 CPU_SPI_SI_R CPU_SPI_SI 4 5% 5% 5% 5% 5% OUT 7 HOLD_N* 1K 5% EMPTY EMPTY EMPTY EMPTY EMPTY CPU_SPI_SO R7E7 CPU_SPI_EN_R 1 402 CH 402 402 402 402 402 4 IN CS_N* 1 2 2 2 2 2 1K 5% 3 WP_N* GND 4 1 4 V_MEM 402 CH R7F4 FT7R4 FTP V_MEM 100 1 3 FT7R6 FTP X800552-001 5% 1 2 FT7R2 FTP 2 R7E8 1 CH 1 1 1 FT7R1 FTP 1 402 0 R7U3 10K 5% 2 FT7R5 FTP 10K 402 CH 5% CH 2 R7F1 1 402 2 R7F2 10K 5% 4 IN CPU_SPI_EN 402 EMPTY CPU_SPI_WP_N IN 4 1K 5% 402 CH DRAWING PROJECT NAME PAGE REV XENON_FABK MICROSOFT[PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] Wed Aug 24 09:27:00 2005 XENON_RETAIL 4/73 K7 CONFIDENTIAL
  5. 5. CPU, FSB U7D1 2 OF 10 IC CPU VERSION 20 12 IN FSB_GP_CP0_CLK_DP Y30 GP_CP0_CLK_DP CP_GP0_CLK_DP AG29 FSB_CP_GP0_CLK_DP OUT 12 12 IN FSB_GP_CP0_CLK_DN Y29 GP_CP0_CLK_DN CP_GP0_CLK_DN AG30 FSB_CP_GP0_CLK_DN OUT 12 12 FSB_GP_CP0_FLAG_DP AD29 GP_CP0_FLAG_DP CP_GP0_FLAG_DP AK27 FSB_CP_GP0_FLAG_DP 12 IN FSB_GP_CP0_FLAG_DN FSB_CP_GP0_FLAG_DN OUT 12 AD30 GP_CP0_FLAG_DN CP_GP0_FLAG_DN AK28 12 IN OUT 12 IN FSB_GP_CP0_DATA0_DP V28 GP_CP0_DATA0_DP CP_GP0_DATA0_DP AD28 FSB_CP_GP0_DATA0_DP OUT 12 12 IN FSB_GP_CP0_DATA0_DN V27 GP_CP0_DATA0_DN CP_GP0_DATA0_DN AD27 FSB_CP_GP0_DATA0_DN OUT 12 12 FSB_GP_CP0_DATA1_DP V30 GP_CP0_DATA1_DP CP_GP0_DATA1_DP AE29 FSB_CP_GP0_DATA1_DP 12 IN FSB_GP_CP0_DATA1_DN FSB_CP_GP0_DATA1_DN OUT 12 V29 GP_CP0_DATA1_DN CP_GP0_DATA1_DN AE30 12 IN FSB_GP_CP0_DATA2_DP FSB_CP_GP0_DATA2_DP OUT 12 W29 GP_CP0_DATA2_DP CP_GP0_DATA2_DP AF30 12 IN OUT 12 IN FSB_GP_CP0_DATA2_DN W30 GP_CP0_DATA2_DN CP_GP0_DATA2_DN AF29 FSB_CP_GP0_DATA2_DN OUT 12 12 IN FSB_GP_CP0_DATA3_DP Y28 GP_CP0_DATA3_DP CP_GP0_DATA3_DP AF27 FSB_CP_GP0_DATA3_DP OUT 12 12 IN FSB_GP_CP0_DATA3_DN Y27 GP_CP0_DATA3_DN CP_GP0_DATA3_DN AF28 FSB_CP_GP0_DATA3_DN OUT 12 12 FSB_GP_CP0_DATA4_DP AA29 GP_CP0_DATA4_DP CP_GP0_DATA4_DP AH30 FSB_CP_GP0_DATA4_DP 12 IN FSB_GP_CP0_DATA4_DN FSB_CP_GP0_DATA4_DN OUT 12 AA30 GP_CP0_DATA4_DN CP_GP0_DATA4_DN AH29 12 IN FSB_GP_CP0_DATA5_DP FSB_CP_GP0_DATA5_DP OUT 12 AB28 GP_CP0_DATA5_DP CP_GP0_DATA5_DP AH27 12 IN OUT 12 IN FSB_GP_CP0_DATA5_DN AB27 GP_CP0_DATA5_DN CP_GP0_DATA5_DN AH28 FSB_CP_GP0_DATA5_DN OUT 12 12 IN FSB_GP_CP0_DATA6_DP AB30 GP_CP0_DATA6_DP CP_GP0_DATA6_DP AJ29 FSB_CP_GP0_DATA6_DP OUT 12 12 IN FSB_GP_CP0_DATA6_DN AB29 GP_CP0_DATA6_DN CP_GP0_DATA6_DN AJ30 FSB_CP_GP0_DATA6_DN OUT 12 12 FSB_GP_CP0_DATA7_DP AC29 GP_CP0_DATA7_DP CP_GP0_DATA7_DP AK30 FSB_CP_GP0_DATA7_DP 12 IN FSB_GP_CP0_DATA7_DN FSB_CP_GP0_DATA7_DN OUT 12 AC30 GP_CP0_DATA7_DN CP_GP0_DATA7_DN AK29 12 IN OUT 12 IN FSB_GP_CP1_CLK_DP G30 GP_CP1_CLK_DP CP_GP1_CLK_DP P30 FSB_CP_GP1_CLK_DP OUT 12 12 IN FSB_GP_CP1_CLK_DN G29 GP_CP1_CLK_DN CP_GP1_CLK_DN P29 FSB_CP_GP1_CLK_DN OUT 12 12 FSB_GP_CP1_FLAG_DP L28 GP_CP1_FLAG_DP CP_GP1_FLAG_DP U30 FSB_CP_GP1_FLAG_DP 12 IN FSB_GP_CP1_FLAG_DN FSB_CP_GP1_FLAG_DN OUT 12 L27 GP_CP1_FLAG_DN CP_GP1_FLAG_DN U29 12 IN OUT 12 IN FSB_GP_CP1_DATA0_DP E28 GP_CP1_DATA0_DP CP_GP1_DATA0_DP L30 FSB_CP_GP1_DATA0_DP OUT 12 12 IN FSB_GP_CP1_DATA0_DN E27 GP_CP1_DATA0_DN CP_GP1_DATA0_DN L29 FSB_CP_GP1_DATA0_DN OUT 12 12 FSB_GP_CP1_DATA1_DP E30 GP_CP1_DATA1_DP CP_GP1_DATA1_DP M30 FSB_CP_GP1_DATA1_DP 12 IN FSB_GP_CP1_DATA1_DN FSB_CP_GP1_DATA1_DN OUT 12 E29 GP_CP1_DATA1_DN CP_GP1_DATA1_DN M29 12 IN FSB_GP_CP1_DATA2_DP FSB_CP_GP1_DATA2_DP OUT 12 F29 GP_CP1_DATA2_DP CP_GP1_DATA2_DP N27 12 IN FSB_GP_CP1_DATA2_DN FSB_CP_GP1_DATA2_DN OUT 12 F30 GP_CP1_DATA2_DN CP_GP1_DATA2_DN N28 12 IN OUT 12 IN FSB_GP_CP1_DATA3_DP G28 GP_CP1_DATA3_DP CP_GP1_DATA3_DP N30 FSB_CP_GP1_DATA3_DP OUT 12 12 IN FSB_GP_CP1_DATA3_DN G27 GP_CP1_DATA3_DN CP_GP1_DATA3_DN N29 FSB_CP_GP1_DATA3_DN OUT 12 12 FSB_GP_CP1_DATA4_DP H29 GP_CP1_DATA4_DP CP_GP1_DATA4_DP R27 FSB_CP_GP1_DATA4_DP 12 IN FSB_GP_CP1_DATA4_DN FSB_CP_GP1_DATA4_DN OUT 12 H30 GP_CP1_DATA4_DN CP_GP1_DATA4_DN R28 12 IN FSB_GP_CP1_DATA5_DP FSB_CP_GP1_DATA5_DP OUT 12 J28 GP_CP1_DATA5_DP CP_GP1_DATA5_DP R30 12 IN FSB_GP_CP1_DATA5_DN FSB_CP_GP1_DATA5_DN OUT 12 J27 GP_CP1_DATA5_DN CP_GP1_DATA5_DN R29 12 IN OUT 12 IN FSB_GP_CP1_DATA6_DP J30 GP_CP1_DATA6_DP CP_GP1_DATA6_DP T30 FSB_CP_GP1_DATA6_DP OUT 12 12 IN FSB_GP_CP1_DATA6_DN J29 GP_CP1_DATA6_DN CP_GP1_DATA6_DN T29 FSB_CP_GP1_DATA6_DN OUT 12 12 FSB_GP_CP1_DATA7_DP K29 GP_CP1_DATA7_DP CP_GP1_DATA7_DP U27 FSB_CP_GP1_DATA7_DP 12 IN FSB_GP_CP1_DATA7_DN FSB_CP_GP1_DATA7_DN OUT 12 K30 GP_CP1_DATA7_DN CP_GP1_DATA7_DN U28 12 IN OUT X02046-002 V_GPUCORE 1 1 1 1 1 1 1 1 1 C6R14 C6R25 C6R37 C6T19 C6T7 C6T27 C6T33 C6T32 C6R6 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF 10% 10% 10% 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 402 402 402 402 402 402 402 402 402 DRAWING PROJECT NAME PAGE REV MICROSOFT[PAGE_TITLE=CPU, FSB] XENON_FABK XENON_RETAIL 5/73 K7 Wed Aug 24 09:27:01 2005 CONFIDENTIAL

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