System Hierarchyin Printed ElectronicsDr. Andreas SchallerASCAndreas Schaller Technology Consultinginfo@andreas-schaller.deDr. Andreas SchallerSystem Hierarchy in Printed Electronics1
OverviewSystem Hierarchy in Printed Electronics21. Introduction2. IEEE Electronics System Hierarchy3. Costs4. Environment5. Summary S
Electronic Consumer DevicesSystem Hierarchy in Printed Electronics31985 1990 1995 2000 2005 2010 ->- 1980TelevisionTV-SetComputerC64RecorderDVDDigitalSony MavicaPortableNokia 5110MobileRazrWearableIpod nanoEmbedded SiliconProduct Example 8088 386 486 Pentium Pentium 4 Core 2 Core 4Transitor Volume 5000 275000 1600000 3100000 42000000 200000000 2000000000Feature Size 2 µm 1.5 µm 0.8 µm 0.35 µm 0.13 µm 65 nm 45 nmIC PackagesPackage Example DIP PLCC QFP FQFP BGA CSP SiP/MCMPackage Type Pin Pin Lead Lead Ball Ball BallPitch Size 2.5 mm 1.7 mm 1.0 mm 0.4 - 1.0 mm 0.7–1.5 mm 0.5 mm 0.25–0.4 mmSmall IC PackagingPackage Example SOT-23 SOIC SOPPackage Type Lead Lead LeadPitch Size 3mm 1.7 mm 0.65 mmPassive ComponentsPackage Example 1206 0603 0402 0201 01005Pitch Size 2.5 mm 2.5 mm 3.2 mm × 1.6 mm 1.6 mm × 0.8 mm 1.0 mm × 0.5 mm 0.6 mm × 0.3 mm 0.4 mm × 0.2 mmPackage Technology THT THT SMT SMT SMT SMT SMTInterconnect TechnologyComponent Placement THT THT/SMT SMT ( Descrete + IC ) SMT ( Descrete + IC ) SMT ( Descrete + IC ) SMT (Mix ) SMT (Mix )Material Curing Wavesoldering Wave/Reflowsoldering Reflow ( 220° C ) Reflow ( 220° C ) Reflow ( 250° C ) Reflow ( 250° C ) Reflow ( 250° C )Mfg-Concept Batch Processing Batch Processing in-line (1-Sided) in-line (2-Sided) in-line (2-Sided/dual line) in-line (2-Sided/dual line) in-line (2-Sided/dual line)Printed Wiring BoardProcess Subtractive Subtractive Subtractive Subtractive Subtractive Subtractive / Semi-additiveLayers Soldermask Multilayer/drilling Via /Laserdrilling Micro-Via / HDILine Space/Width 100/100 100/100 75/75 50/50 50/50 40/40 25/25ProductSample
Future ICT Markets”Internet of Things”System Hierarchy in Printed Electronics4Green CarsFactoriesof the FutureEnergy-efficientBuildingsFuture Internet• Microelectronics• Ubiquitous positioning• Wirelessly communicatingsmart systems• Non-silicon based components• Energy harvesting technologies• Privacy- and security-by-designSurfaceMountTechnologyPrintedTechnologyEmbeddedIntelligenceIntegrated Smart Systems
Electronic Consumer Devices(Future Internet )System Hierarchy in Printed Electronics5GPSLibrarySocialNetworksLocationARPaymentCouponsLoyaltyTV/CinemaFlightTicketingProductInfoWellnessTicketingGamingSportB2COLEDSmart PackagingDiagnosisLarge Area SensorsFutureInternet
Integrated Smart SystemsMain devices and applicationsSystem Hierarchy in Printed Electronics6
IEEE Electronics System HierarchySystem Hierarchy in Printed Electronics7
SMT HierarchySystem Hierarchy in Printed Electronics8Connections between physically separatesystems such as host computer toterminals, computer to printers, and so on.Level 5 Connections between systemsLevel 4 SubassemblyLevel 3 Connections between PWBsLevel 2 Printed Wiring Board (PWB)Level 1 Integrated CircuitsLevel 0 Monolithic Silicon Chip Gate-to-gate interconnections on amonolithic silicon chipConnections between two subassemblies.For example, a rack or frame may holdseveral shelves of subassemblies thatmust be connected together to make up acomplete system.Connections between PWBs, includingPWB-to-PWB interconnections or card-to-motherboard interconnections.Printed wiring board (PWB) level ofinterconnections. Printed conductor pathsconnect the device leads of componentsto PWBs and to the electrical edgeconnectors for off-the-boardinterconnection.Packaging of silicon chips into dual-in-linepackages (DIPs), small outline integratedcircuit (SOICs), chip carriers, multichippackages, and so on, and the chip-levelinterconnects that join the chip to the leadframes.
Printed Electronics (PET)System Hierarchy in Printed Electronics10Source : Acreo
PET HierarchySystem Hierarchy in Printed Electronics11Level 5 Connections between systems Ambient IntelligenceLevel 4 Subassembly System IntegrationLevel 3 Connections between PWBs Smart SystemLevel 2 Printed Wiring Board (PWB) System-in-FoilLevel 1 Integrated Circuits Functional LayersLevel 0 Monolithic Silicon Chip Printable InkSilver InkPrintedAntennaRFID LabelBattery AssistedLabelSmart PackageRFID SystemSMT PET Example
PET ApplicationsSystem Hierarchy in Printed Electronics12OE-A Roadmap Products
CostsSystem Hierarchy in Printed Electronics13
Integrated Smart SystemsCostsSystem Hierarchy in Printed Electronics14Ink(Organic and/or Inorganic)Foils and/or Paper Inkjet / Gravure / ScreenPrintingAssembly(Lamination)LaminationLabeling(none if integrated)Battery and/or ICAntenna and/or SensorConnectingwire / wirelessTagged Object( included in BOM)
Optimized CostsSystem Hierarchy in Printed Electronics15RFIDRFIDPrintingFoilsAdded Value ?
System on FoilsSystem Hierarchy in Printed Electronics16Source: iNEMI Roadmap on INTERCONNECTION SUBSTRATES - ORGANICAntennaRFLogicSensor4 layers could be the limit before the alignment costs become the bottleneckAssumption:>100 μm feature sizeRatio of differences in cost per layer
Large Area SensorsIntegrated Pyro/Piezoelectric SensorsIntegrated organic physical sensor• Capacitive sensor part is based on ferroelectric polymer• Sensor response to ΔT, Δp controls the transistor„s gate• Transistor transforms high-impedance sensor signal to low-impedance output signal• Monolithically integrated on flexible substrateSensorTransistorSystem Hierarchy in Printed Electronics18
p ~ 40 µC/m2Kd33 = 24 pC /NSensor and TransistorsSystem Hierarchy in Printed Electronics19VGVDSVGVDSSensorTransistors
Human-Machine InterfaceAll-printed sensor with ACREO display• Control with/without touch• Minimized number of materials• Large Areas Electronics• Very robustSystem Hierarchy in Printed Electronics21http://cid-2e87bf9055410c4c.photos.live.com/self.aspx/ASC-Andreas%20Schaller%20Technology%20Consulting/3Plast.wmv
Medical ComplianceLow Cost Printed MemorySystem Hierarchy in Printed Electronics2714-bit inkjetted WORM bank Uwrite= 10 V and Rs= 330 Ω.•resistive memory: electrically induced sintering high-resistance->low-resistance)•key point : electrically post-fabrication programmable
Technology ComparisonSystem Hierarchy in Printed Electronics32$$$CO2Assumptions :- Production environment not included- Battery MFG not included, only BOM- Recycling not included
CO2 FootprintSystem Hierarchy in Printed Electronics331. Use PhaseAs there is no long use phase for „disposable“ smart packaging the CO2impact depends on the manufacturing phase.2. Manufacturing phaseThe drying / sintering processes are the main driver for level 1. This needs tobe optimized !3. Printed ElectronicsMoving into a clean room environment for production would significantlydecrease the CO2 benefits of PET vs. SMT4. Organic ElectronicsWhat would have changed if we had used organic material ?
Environmental ImpactPrinted ElectronicsSystem Hierarchy in Printed Electronics34Improvement in %PET vs. SMTROHSComplianceEconomicMfg CostsLifecycleCO2-FootprintWEEERecycling RateSummarySMT/PET fully passed60%48%10%TechnologyEnergy forproduction(MJ.Wp-1)CO2footprint(gr.CO2-eq.Wp-1)Energypaybacktime(years)mc-Si 24,9 1293 1,95CdTe 9,5 542 0,75CIS 34,6 2231 2,71OPV 2,4 132 0,19Source : A. L. Roes et al, Progress in Photovoltaics 17, 372 (2009)Source : KonarkaSource : Sumitomo Chemical Source : PriMeBitsOPVSmartPackagingSource : SonySource : LGOLED
SummarySystem Hierarchy in Printed Electronics35Smart Objects are driven by LEVEL 5(Content driven) Connectivity enables an object to become ”smart”Flexible Electronics is driven by LEVEL 4Customer Benefits is flexible-to-install vs. flexible-to-useIntegrated Smart Systems are driven by LEVEL 3Application driven system integrationLarge Area Electronics is driven by LEVEL 2Macro electronics for functional area maximization (vs. microminiaturization)Printed Electronics is driven by LEVEL 1Low cost and environmental preferred manufacturingOrganic(Inorganic) Electronics is driven by LEVEL 0Multi-functional materials for electronic and sensing functions
RoadmappingSystem Hierarchy in Printed Electronics362011 Roadmap onLarge Area Flexible ElectronicsPublished 01/2011
PE has to evolve from alow cost to an enabling technologySystem Hierarchy in Printed Electronics37Source : Thin FilmSource : PolyICSource : Polymer Vision / WistronSource : Stora EnsoSource : Sensible SolutionsSource : PrelonicSource : NTERAFLEXIBILITY !TRANSPARENCY !CONNECTIVITY !
Questions ?System Hierarchy in Printed Electronics38Andreas Schaller Technology Consulting Unternehmergesellschaft (haftungsbeschränkt)Dr. Andreas SchallerEmail : firstname.lastname@example.orgAndreas Schaller Technology Consulting Unternehmergesellschaft (haftungsbeschränkt)Office : Schulstr. 11, 95676 WiesauManagement : Dr. Andreas SchallerDistrict Court : AG Weiden, HRB 3499