Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

Peaceful coexistence among architectures


Published on

Title: Peaceful coexistence among architectures
Author: Andreas Olofsson
Location: Panel, HPEC 2009
Date: September 2009

Published in: Technology
  • Be the first to comment

  • Be the first to like this

Peaceful coexistence among architectures

  1. 1.   Peaceful coexistence among architectures Andreas Olofsson, Adapteva HPEC 2009
  2. 2. HPEC 20092 Introduction to Adapteva  We are a fabless semiconductor company busy  developing the world's most energy efficient C­ programmable floating point processors targeted at  embedded applications.  Prototype in hand, product slated for middle of next  year
  3. 3. HPEC 20093 Why ASICs?  Because flexibility wastes energy: − Given the same conditions ASICs have a 50x­1000x energy  efficiency edge over GPUs, DSPs, FPGAs, and  Microprocessors.  The problems: − Expensive to (re)design, long turnaround times − Very difficult to get specification right the first time − Limited number of design teams who can design deep sub­ micron ASICs
  4. 4. HPEC 20094 Breaking down ASIC costs  "The cost of ASICs are sky rocketing", Moshe Gavrielov,  CEO at Xilinx SOC ASIC FPGA HARDWARE $16,875,000 $1,200,000 $900,000 SOFTWARE $6,750,000 $300,000 $300,000 TOOLS $5,000,000 $500,000 $0 FABRICATION $2,500,000 $200,000 $0 IP $5,000,000 $500,000 $0 TOTAL $36,125,000 $2,700,000 $1,200,000 ➢ Conclusion: Architecture development cost is heavily  dependent on architecture and end application
  5. 5. HPEC 2009 5 The “Ideal” Embedded Solution Peaceful coexistence between architectures... FPGA Great at interfaces and bit level  processing Great at math! Limited flexibility Simple programming Great at control,  human interfaces, and  knowledge extraction “SOFT” ASIC
  6. 6. HPEC 2009 PIPELINE REGISTER  FILE DCACHE CONTROL ICACHE 6 Energy Waste in Processors ➢ Conclusion: The hardware­software energy efficiency  gap can reduced from 100x to less than 3x with an  appropriate architecture. TYPICAL, 1% EFFICIENCY FOCUSED, 37% EFFICIENCY REGISTER  FILE ARITHMETIC PIPELINE DCACHE CONTROL ICACHE ARITHMETIC GENERIC PROCESSOR ALU MEMORY CONTROL
  7. 7. HPEC 20097 Adapteva's Vision for Soft ASICs  ANSI C­programmable IEEE Floating  Point Signal Processing  16 to 4096 independent cores 50 GFLOP/Watt @ 65nm Real Performance uP MEMORY DMAROUTER