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Enrichment lecture EE Technion (part B) on the subject of VHDL-2008 (April 2012)

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- 1. הרצאת העשרה בנושא VHDL Introduction (or beyond LAB #1 experiments) part II Version 1.0 - May 2012 Amos Zaslavsky 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 1 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 2 VHDL-2008 is here (alive and kicking..) Improvements in VHDL-2008 are in areas:The Original VHDL-1987 standard was very powerful ! A Short History LessonPrevious updated revisions were minor – VHDL-1993 (files, direct instantiation, extended naming of identifiers, Making VHDL language stronger some minor coding style change, shared variables .. ) (many more features.. ) – VHDL-2002 (protected shared variables, improved buffer mode, bigger real .. ) Making VHDL language easier to useBecause the basic version was very powerful and modifications were very (less cumbersome.. )minor, many tool vendors ignored modifications or upgraded their toolsvery slowly (why bother ..)Many people consider only Verilog 2001 to be a matching competitor toVHDL (this tie situation continues from 2001 until 2005) Enhancements in the area of VerificationSystemVerilog (2005) is a superset of Verilog that improves its (adding powerful features to existingverification capabilities. Some are beyond VHDLs verification capabilities. capabilities + More coming soon.. )VHDL-2008 is a Major Revision with many improvement 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 01 Page: 3 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 01 Page: 4
- 2. The final goal ()מה מתבשל בתנור Presentation goalsWhy update VHDL ? Instead, why not adopt SystemVerilog as verificationLanguage ?VHDL already includes many system-level modeling features such as: records,access types (pointers), Protected types & shared variables, PSL and many many מטרהother advanced features that can be enhanced with relatively little effort, and newfeatures can be added in a way that integrates cleanly with existing features.Organizations using VHDL already have significant experience using thelanguage and a pool of people familiar with the language.Using SystemVerilog wold force users to learn a language that is different or haveto manage multilingual environments (causing lower productivity) ההצבעה על כיווניםFinal Goal: VHDL = Verification & Hardware Description LanguageThe next enhancements are mostly Verification focused: ()מבלי להעמיק בחומר ומבלי לעבור על כל התוספות – Object Oriented Classes – Verification Data structures – More powerful Randomization (enhancing existing capabilities) – Functional Coverage – & Incorporating good things from SystemVerilog, SystemC, Vera & E 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 01 Page: 5 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 6 We will no go into all the modifications.. Topics can all be found in For More information ( or use the new LRM :-( ) תמיכה במהדורה השניה שתצא בתחילת שנת הלימודים הבאה 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 7 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 8
- 3. Topics that will be Mentioned here Topics that will be Mentioned hereMore reserved words Simulation/VerificationMore convenient Comments More convenient combinatorial descriptionsMore powerful & convenient constant string assignments More convenient sync descriptions Simulation/VerificationMore convenient mixed bit & vector Logical operations New to_string(_) functions onlyUnary reduction operations expressions written to ports when instantiation of componentsMore built in arrays Revision of Modes (port directions) Simulation/Verification directednumeric_std_unsigned from IEEE replaces std_logic_unsigned from More convenient & powerful generate statementsSynopsys Forcing signals through hierarchies using external namesBetter relations Forcing signals through hierarchies using external names Simulation/Verification onlyNew maximum(_), & minimum(_) functions Forcing ports: Driving value & Effective valueNew Fixed point and float vectors Embedded PSLThe Context design unit IP (Intellectual Property) protection Simulation/VerificationThe condition operator VHDL Procedural Interface (VHPI) directedMore convenient Case operationsconditional assignments & selected assignments in process 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 9 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright Page: 10 Reserved names VHDL87 abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded if in inout is label library linkage loop More reserved map mod nand new next words nor not null of on open or others out package port procedure process range record register rem report return select severity signal subtype then to transport type units until use variable wait when while with xor 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 11 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 12
- 4. More reserved names VHDL-93/2002/2008group impure inertial literal posponedpure reject rol ror sharedsla sll sra srl unaffectedxnor VHDL-93protected VHDL-2002 More convenient VHDL-2008 Commentsassume assume_guarantee context coverdefault fairness force parameterproperty release restrict restrict_guaranteesequence strong vmode vpropvunit PSL words 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 13 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 14 Comments-- this comment ends with <CR> <LF>y <= a and b and c ; -- right part of this line is a comment-- this-- is More powerful &-- a convenient constant-- long string assignments-- comment/* this is a delimiter comment in VHDL-2008 */ 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 15 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 16
- 5. Old & New bit-string literals Specifying width in new bit-string literalsy <= b"11110110" ; -- binary Padding with leading zeros on the left ok on older versions 13d"246" => "0000011110110"y <= x"F6" ; -- hex 13o"366" => "0_000_011_110_110" 13x"f6" => "0_0000_1111_0110"y <= "1111" & "011" & 0 ; -- default vector is bin 10o"0366" => "0_011_110_110" 10x"0f6" => "00_1111_0110”y <= x"f" & o"3" & 0 ; -- octal & lowercase too Signed values (Unsigned is the default) 12ux"f6" => "0000_1111_0110" (unsigned extension)y <= 246 ; -- error 12x"f6" => "0000_1111_0110" (unsigned extension) 12sx"f6" => "1111_1111_0110" (signed extension)y <= d"246" ; -- ERROR d is not a legal prefix assigning std_logic_vector with meta-charactersy <= d"246" ; -- OK in VHDL-2008 ! 12o"01X" => "000_111_XXX" 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 17 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 18 Mixed vector & bit operations -- a polarity changer ? entity op_bv1 is a7 port ( x : out bit_vector(7 downto 0) ; x7 a6 a : in bit_vector(7 downto 0) ; x6 b : in bit ) ; a5 x5 end op_bv1 ; a4 x4 More convenient architecture arc_op_bv1 of op_bv1 is a3 mixed bit & vector x3 begin a2 Logical operations x <= a xor b ; x2 a1 end arc_op_bv1 ; x1 a0 x0 Not legal on older Versions b OK on VHDL-2008 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 19 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 20
- 6. Solution on older versions Solution on older versions-- a polarity changer -- some other solutions (less elegant)entity op_bv1 is a7 port ( x : out bit_vector(7 downto 0) ; x7 x <= a xor ( b & b & b & b & b & b & b & b ) ; a6 a : in bit_vector(7 downto 0) ; x6 b : in bit ) ; a5 x <= a xor ( b , b , b , b , b , b , b , b ) ; x5end op_bv1 ; a4 x4architecture arc_op_bv1 of op_bv1 is a3 x <= ( a(7) xor b , a(6) xor b , a(5) xor b , a(4) xor b , x3 signal b_bv : bit_vector ( 7 downto 0 ) ; a2 a(3) xor b , a(2) xor b , a(1) xor b , a(0) xor b ) ;begin x2 a1 b_bv <= ( others => b ) ; x1 x(7) <= a(7) xor b ; a0 x <= a xor b_bv ; x0 x(6) <= a(6) xor b ;end arc_op_bv1 ; x(5) <= a(5) xor b ; x(4) <= a(4) xor b ; b . .. 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 21 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 22 What had to be done in older versions -- no reduced operations on old VHDL entity reduced_vec is port ( din : in bit_vector(7 downto 0) ; parity : out bit ) ; end reduced_vec ; architecture arc_reduced_vec of reduced_vec is Unary reduction begin operations parity <= din(7) xor din(6) xor din(5) xor din(4) xor din(3) xor din(2) xor din(1) xor din(0); end arc_reduced_vec ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 23 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 24
- 7. Unary reduction operations in VHDL-2008-- reduced operations on a vector (VHDL-2008)entity reduced_vec is port ( din : in bit_vector(7 downto 0) ; parity : out bit ) ;end reduced_vec ;architecture arc_reduced_vec of reduced_vec isbegin More built in arrays parity <= xor din ;end arc_reduced_vec ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 25 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 26 boolean, integer, real & time arrays boolean, integer, real & time arrays-- decoder 3->8 using numeric relations -- decoder 3->8 using numeric relationsentity dec3t8 is entity dec3t8 is port ( din : in integer range 0 to 7 ; port ( din : in integer range 0 to 7 ; enable : in boolean ; enable : in boolean ; d : out boolean_vector(7 downto 0) ) ; d : out boolean_vector(7 downto 0) ) ;end dec3t8 ; end dec3t8 ;architecture arc_dec3t8 of dec3t8 is architecture arc_dec3t8 of dec3t8 isbegin begin -- positional association -- named association d <= ( ( din=7 ) and enable , d <= ( 7 => ( din=7 ) and enable , in old VHDL only bit_vector in old VHDL only bit_vector ( din=6 ) and enable , (or std_logic_vector) and 6 => ( din=6 ) and enable , (or std_logic_vector) and ( din=5 ) and enable , strings 5 => ( din=5 ) and enable , strings ( din=4 ) and enable , 4 => ( din=4 ) and enable , boolean_vector, boolean_vector, ( din=3 ) and enable , integer_vector, real_vector, 3 => ( din=3 ) and enable , integer_vector, real_vector, time_vector time_vector ( din=2 ) and enable , 2 => ( din=2 ) and enable , ( din=1 ) and enable , 1 => ( din=1 ) and enable , ( din=0 ) and enable ) ; 0 => ( din=0 ) and enable ) ;end arc_dec3t8 ; end arc_dec3t8 ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 27 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 28
- 8. New: numeric_std_unsigned The most popular 3 declarations (math operations on vectors) -- Using the classic package of Synopsys in old VHDL library ieee ; use ieee.std_logic_1164.all ; std_logic_unsigned from use ieee.std_logic_unsigned.all ; Synopsys is replaced by Replaced by: numeric_std_unsigned from -- Same thing with new package of IEEE in VHDL-2008 IEEE library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std_unsigned.all ; -- a new package ! More operations (divisions,power)8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 29 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 30 Problems with old = relations Better relations ’1‘ ’X‘ ’U‘ false false true ’H‘ ’Z‘ ’U‘ Not behaving like real hardware Return Boolean8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 31 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 32
- 9. New (matched) ?= relation Problems with old relations - (<)Any compare to ‘-’ Any compare to Strong ‘0’ & ‘1’ ‘W’ ‘X’ & ‘Z’ is (don’t care) is ‘1’ ‘U’ is ‘U’ equal weak ‘L’ & ‘H’ same as ‘X’ U < X < 0 < 1 < Z < W < L < H < - Vectors are and-ed together, with any ‘X’ producing ‘X’ result and any ‘0’ producing ‘0’ result No Meaningful hardware behavior Behaving like real hardware Return Boolean 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 33 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 34 New (matched) ?< relation Other Matched relations Are all created by operations on the previous relations ?/= is an inverted ?= ?>= is iverted ?< ?<= is ?< or-ed with ?= Example of usage: library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std_unsigned.all ; -- present for math meaning entity good_compare2 is port ( a : in std_logic_vector(3 downto 0) ; b : in std_logic_vector(2 downto 0) ; a_gte_b : out std_logic ) ; end good_compare2 ; architecture arc_good_compare2 of good_compare2 is Any compare to ‘-’ Any compare to Strong ‘0’ & ‘1’ ‘W’ ‘X’ & ‘Z’ is(don’t care) is error ‘U’ is ‘U’ equal weak ‘L’ & ‘H’ same as ‘X’ begin a_gt_b <= ( a ?>= b ) ; -- matching directional compare Behaving like real hardware end arc_good_compare2 ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 35 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 36
- 10. Order of Precedence of operators Order of precedence of operators8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 37 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 38 minimum(_) & maximum(_) functions Can be used with the following data types: character, bit, integer, real, time, string, boolean_vector, bit_vector, integer_vector, real_vector, time_vector, std_logic_vector and many more types .. (any data types that relations can be operated on) Usage: maximum( object1 , object2 ) -- max between 2 New maximum(_), & maximum ( array_type ) -- returns max array element minimum(_) functions Example of usage: constant w1 : integer := 3 ; constant w2 : integer := 2 ; signal y : std_logic_vector(maximum(w1,w2) downto 0) ;8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 39 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 40
- 11. More Powerful vector data types The new Powerful data types – Unsigned fixed - ufixed – Signed fixed - sfixed – Floating Point - float They are all vectoric data types ! Useful for: – Large dynamic range (including fractions) New Fixed point and – Complex Arithmetic and DSP applications float vectors fixed types consume less hardware resources but have lower dynamic range, float has more dynamic range but hardware is more complex Support for synthesis: In a short time – For example, Altera has already the flowing floating point macrofunctions: ALTFP_ABS, ALTFP_ADD_SUB, ALTFP_COMPARE, ALTFP_CONVERT, ALTFP_DIV, ALTFP_EXP, ALTFP_INV, ALTFP_INV_SQRT, ALTFP_LOG, ALTFP_MULT, ALTFP_SQRT, and more coming soon... & fixed = integers 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 41 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 42ufixed & sfixed declarations & assignments ufixed & sfixed declarations & assignments c c c c Declarations & assignments (negative index range is fraction) Code example of an adder 1 1 1 1 . 0 0 0 0 signal u : ufixed (1 downto -4) ; library ieee ; 1 1 1 1 . 0 0 0 0 Example signal s : sfixed (3 downto -1) ; use ieee.fixed_pkg.all ; 1 1 1 1 0 . 0 0 0 0 ... entity fixed_vec is u <= "101010" ; -- 10.1010 = 2.625 port ( a,b : in ufixed(3 downto -4) ; -- width 8 s <= "11100" ; -- 1110.0 = -2 y : out ufixed(4 downto -4) ) ; -- width 9 Equivalent Assignments (parameters are index ranges) end fixed_vec ; u <= to_ufixed(2.625,1,-4) ; -- 10.1010 = 2.625 architecture arc_fixed_vec of fixed_vec is s <= to_sfixed( -2 ,3,-1) ; -- 1110.0 = -2 begin Equivalent Assignments (parameter copies ranges from declarations of u y <= a + b ; -- both sides are width 9 and s respectivly) end arc_fixed_vec ; u <= to_ufixed(2.625,u) ; -- 10.1010 = 2.625 Operands are 8 bit wide & Result is 9 bits (Full Precision math with no s <= to_sfixed( -2 ,s) ; -- 1110.0 = -2 automatic modulo-truncation) 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 43 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 44
- 12. with old vector (integer) math with old vector (integer) mathBoth sides of assignments are not equal so it is not a legal code Now you get automatic modulo-truncation -- error -- OK but with different results c c c c library ieee ; library ieee ; 1 1 1 1 Example use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all ; 1 1 1 1 use ieee.std_logic_unsigned.all ; use ieee.std_logic_unsigned.all ; 1 1 1 0 entity vec_math is entity vec2_math is port ( a,b : in std_logic_vector(3 downto 0) ; port ( a,b : in std_logic_vector(3 downto 0) ; y : out std_logic_vector(4 downto 0) ) ; y : out std_logic_vector(3 downto 0) ) ; end vec_math ; end vec2_math ; architecture arc_vec_math of vec_math is architecture arc_vec2_math of vec2_math is begin begin y <= a + b ; -- error y <= a + b ;end arc_vec_math ; end arc_vec2_math ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 45 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 46 with old vector (integer) math Other operations on ufixedHandling the truncated bit Result size -- Handling truncation bit library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; entity vec3_math is port ( a,b : in std_logic_vector(3 downto 0) ; y : out std_logic_vector(4 downto 0) ) ; end vec3_math ; example: architecture arc_vec3_math of vec3_math is signal A : ufixed (7 downto -4) ; begin signal B : ufixed (3 downto -9) ; y <= (0 & a) + (0 & b) ; Width of multiplication result end arc_vec3_math ; ufixed(7+3+1 downto (–4)+(–9)) No meaning for abs(_) and unary -(_) with ufixed 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 47 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 48
- 13. Other operations on sfixed More operationsResult size Mixing with integer and real signal a : sfixed (8 downto -5); signal b : real ; ... y <= a + b ; Equivalent to last assignment (b converted to ranges of a) y <= a + sfixed(b,8,-5) ; Relation (Compare operations) = , /= , < , > , >= , <= , ?= , ?/= , ?< , ?> , ?>= , ?<= Logical operations and, or, nand, nor, xnor, not Conversion functionsAdded operations meaning for abs(_) and unary -(_) with sfixed sll, srl, rol, ror, sla, sra Conversion functions to_sfixed(_),to_ufixed(_),to_real(_),to_integer(_),to_std_logic(_), to_string(_),resize(_) 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 49 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 50 Beyond fixed - float Float Fixed – more (dynamic range + hardware) less (dynamic range + hardware) – constant relative accuracy constant absolute accuracy What’s wrong with real – Fixed range of 64 bit not suitable for all applications – No easy and direct access to bits of number New Floating point Package float_pkg enables usage of vectors – Standard 32 bit & 64 bit numbers (IEEE-754) – Standard 128 bit numbers – Any width (compliant with IEEE-854) 3 Parts (mandatory) sign.exponent.fraction Examples in next foils.. 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 51 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 52
- 14. float32 example (normalized) float32 example (normalized) Structure the previous function to_float(_) converts real to float Structure of standard 32 bit floating point vector = float32 Bit 8 (MSB) is the sign bit S Exponent Mantissa or fraction or significand bits (7 downto 0) are for exponent 8 bit 23 bit bits (-1 downto 23) are for mantissa=fraction=significand Direction of vector must always be downto Normalization method of fraction is 1.fraction (1 not represented) Equivalent declaration to the previous one: Calculation of a normalized number signal f : float32 ; -- a shorter way NORMILIZED _ NUM = (−1) SIGN ⋅ 2 EXPONENT −127 ⋅ (1.0 + FRACTION ) Equivalent assignments: example: f <= to_float(6.5,f) ; use ieee.float_pkg.all ; f <= 0 & "10000001" & "10100000000000000000000" ; .. signal f : float (8 downto -23) ; -- bit 8 is sign Calculation of last assignment: .. (−1) SIGN ⋅ 2 EXPONENT −127 ⋅ (1.0 + FRACTION )begin f <= to_float(6.5,8,23) ; = 2129−127 ⋅ (1.0 + 0.625) = (4) ⋅ (1.625) = 6.5 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 53 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 54 float32 example (normalized) float32 example (un-normalized) The smallest possible normalized values (exponent must not be zero) Un-normalized (De-Normalized) values have a zero exponent f <= 0 & "00000001" & "00000000000000000000000" ; DENORMILIZED _ NUMBER = (−1) SIGN ⋅ 2−126 ⋅ ( FRACTION ) f <= 1 & "00000001" & "00000000000000000000000" ; Calculation of the smallest normalized positive value Biggest values are & calculation of biggest positive value: EXPONENT −127 f <= ’0 & "00000000" & "11111111111111111111111" ; (−1) SIGN ⋅2 ⋅ (1.0 + FRACTION ) f <= 1 & "00000000" & "11111111111111111111111" ; 1−127 =2 ⋅ (1.0 + 0.0) = 2−126 DENORMILIZED _ NUMBER = (−1) SIGN ⋅ 2−126 ⋅ ( FRACTION ) −38 ≈ (1.175494350) ⋅10 = (−1) SIGN ⋅ 2−126 ⋅ (1 − 2−23 ) ≈ (1.175494210) ⋅10-38 Mid values are & calculation of mid positive value: exponent 00000000 is considered un-normalized and is calculated f <= 0 & "00000000" & "10000000000000000000000" ; differently (next foils) f <= 1 & "00000000" & "10000000000000000000000" ; DENORMILIZED _ NUMBER = (−1) SIGN ⋅ 2−126 ⋅ ( FRACTION ) = 2−126 ⋅ (0.5) = 2−127 ≈ (5.87747..) ⋅10-39 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 55 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 56
- 15. float32 example (un-normalized) float32 example (big-normalized)Smallest values are & calculation smallest positive value: The biggest possible normalized values (exponent no zeros) &f <= 0 & "00000000" & "00000000000000000000001" ; calculation of it’s valuef <= 1 & "00000000" & "00000000000000000000001" ; f <= 0 & "11111110" & "11111111111111111111111" ; f <= 1 & "11111110" & "11111111111111111111111" ; DENORMILIZED _ NUMBER = (−1) SIGN ⋅ 2−126 ⋅ ( FRACTION ) (−1) SIGN ⋅ 2 EXPONENT −127 ⋅ (1.0 + FRACTION ) = 2−126 ⋅ (2−23 ) = 2−149 = 2254−127 ⋅ (1.0 + (1 − 2−23 )) ≈ (1.401298..) ⋅10-45 = 2+127 ⋅ (2.0 − 2−23 ))Any smaller number then that, is considered zero & calculation of it’spositive value (zero) is: ≈ (3.402823...) ⋅1038f <= 0 & "00000000" & "00000000000000000000000" ;f <= 1 & "00000000" & "00000000000000000000000" ; Values beyond that are considered infinite: DENORMILIZED _ NUMBER = (−1) SIGN ⋅ 2−126 ⋅ ( FRACTION ) f <= 0 & "11111111" & "00000000000000000000000" ; = (−1) SIGN ⋅ 2−126 ⋅ (0) f <= 0 & "11111111" & "00000000000000000000000" ; =0 Infinite is result of division of non zero by zero. 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 57 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 58 float32 example (NaN) Example of floating point dividerExponent 11111111 and fraction that is not all zeros is NaN -- example of a floating point dividerResult of: library ieee ; – division of 0 by 0 use ieee.float_pkg.all ; – Square root of -1 entity fdiv is – Addition of +infinity and -infinity port ( a,b : in float32 ; – division of infinity by infinity y : out float32 ) ; – others.. end fdiv ;The fraction is considered a Payload that specifies code of problem architecture arc_fdiv of fdiv is Non Standard floating pointsQuiet NaN or qNaN (MSB of fraction is 1) Signaling NaN or sNaN can be declared too begin(MSB of fraction is 0) y <= a / b ; standard 64 & 128 bitf <= 0 & "11111110" & "1??????????????????????" ; signal a,b : float64 ;f <= 1 & "11111110" & ”0??????????????????????” ; end arc_fdiv ; signal a,b : float128 ; -- non standard 16 bitAfter Quiet NaN or qNaN calculations can continue signal a,b : float(5 downto -10) ;After Signaling NaN or sNaN calculations are stopped -- non standard 7 bits (minimum) signal a,b : float(3 downto -3) ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 59 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 60
- 16. Example of floating point divider More standard float formats (64 & 128 bits)force a x"40d00000" ;# 6.5 Declaring standard 64 & 128 bit standard floatsforce b x"40d00000" ;# 6.5 signal f1 : float(11 downto -52) ; -- standard 64run 100 ns ;# expected x3f800000 = 1.0 signal f2 : float(15 downto -112) ; -- standard 128force b x"3f800000" ;# 1.0run 100 ns ;# expected x40d00000 = 6.5 An alternative declarationsforce b x"00000000" ;# 0.0 signal f1 : float64 ; -- standard 64 bitrun 100 ns ;# expected x7f800000 = inf signal f2 : float128 ; -- standard 128 bitforce a x"00000000" ;# 0.0 The general Normalized formula:run 100 ns ;# expected x7f800001 = NaN NORMILIZED _ NUM = (−1) SIGN ⋅ 2 EXPONENT −( EXPONENT _ BIAS ) ⋅ (1.0 + FRACTION ) EXPONENT _ BIAS = 2 EXPONENT _ WIDTH −1 − 1 The General De-Normalized Formula: DENORMILIZED _ NUM = (−1) SIGN ⋅ 2− ( EXPONENT _ BIAS −1) ⋅ ( FRACTION ) EXPONENT _ BIAS = 2 EXPONENT _ WIDTH −1 − 1 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 61 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 62 More standard float formats (64 & 128 bits) More on float format The Standard 64 float Formula: Non standards of 16 bits & 7 bits examples or others possible too.. signal f3 : float(5 downto -10) ; -- 16 bit signal f4 : float(3 downto -3) ; -- minimum 7 bits NORMILIZED _ N 64 = (−1) SIGN ⋅ 2 EXPONENT −1023 ⋅ (1.0 + FRACTION ) Operations supported − (1022) +, –, *, /, rem, mod, abs(_), –(unary) DENORMILIZED _ N 64 = (−1) SIGN ⋅2 ⋅ ( FRACTION ) Ranges are adjusted to the widest exponent & fraction -- adjusting floats with different ranges The Standard 64 float Formula: library ieee ; use ieee.float_pkg.all ; entity fadd is port ( a : in float( 8 downto -23) ; NORMILIZED _ N128 = (−1) SIGN ⋅ 2 EXPONENT −16383 ⋅ (1.0 + FRACTION ) b : in float(11 downto -52) ; Adjusted to this y : out float(11 downto -52) ) ; end fadd ; DENORMILIZED _ N128 = (−1) SIGN ⋅ 2− (16382) ⋅ ( FRACTION ) architecture arc_fadd of fadd is begin y <= a + b ; end arc_fadd ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 63 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 64
- 17. More on float format More on float format Last assignment is equivalent to: Last assignment is equivalent to: y <= resize(a,11,52) + b ; y <= a + to_float(b,a) ; y <= resize(a,b) + b ; If any operand has non strong ‘0’ or ‘1’ or non strong ‘L’ or ‘H’ result is type real is automatically adjusted to the float operand: “XX..X”-- real type adjusted to float Relations are all supportedlibrary ieee ; use ieee.float_pkg.all ; = , /= , < , > , >= , <=entity fadd2 is ?= , ?/= , ?< , ?> , ?>= , ?<= port ( a : in float(8 downto -23) ; Adjusted to this Logical operations are all supported b : in real ; and, or, nand, nor, xnor, not y : out float(8 downto -23) ) ; Many functions supported:end fadd2 ; – to_float(_), to_real(_), to_integer(_), to_stdlogic(_), to_stdlogic_vector(_)architecture arc_fadd2 of fadd2 is – resize(_)begin – to_string(_) y <= a + b ; – more...end arc_fadd2 ; Will soon be supported by synthesis ! 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 65 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 66 The context design unit Makes including a group of libraries and packages easier using a single name reference Example of declaration (and then declaration to library proj_lib): context easy is library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; library proj_lib ; The Context use proj_lib.proj_pack.all ; design unit use std.textio.all ; use ieee.std_logic_textio.all ; end context ; Example of usage: library proj_lib ; context proj_lib.easy ; entity . . . is . . . 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 67 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 02 Page: 68
- 18. The ?? condition Operator -- Introducing the condition operator "??" library ieee ; use ieee.std_logic_1164.all ; entity condition is port ( din : in std_logic ; dout : out boolean ) ; end condition ; The condition architecture arc_condition of condition is operator begin dout <= ?? din ; -- convert std_logic to boolean end arc_condition ; ‘1’ or ‘H’ is converted to true other values (’0’,’L’,’X’,’Z’,’U’,’W’’-’) are converted to false 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 69 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 70 Old style (not convenient) Old style (using the ?? operator)entity condition1 is -- using the ?? operator port( cs0,cs1,pol : in bit ; architecture arc_condition2 of condition2 is din : in bit_vector(3 downto 0) ; dout : out bit_vector(3 downto 0) ) ; beginend condition1 ; process (din,cs0,cs1,pol)architecture arc_condition1 of condition1 is begin Not booleanbegin if ?? ( cs1 and not cs0 and pol ) then process (din,cs0,cs1,pol) begin boolean dout <= din ; if cs1 = 1 and cs0 = 0 and pol = 1 then elsif ?? ( cs1 and not cs0 and not pol ) then dout <= din ; dout <= not din ; elsif cs1 = 1 and cs0 = 0 and pol = 0 then else dout <= not din ; else dout <= ( others => 0 ) ; dout <= ( others => 0 ) ; end if ; end if ; end process ; end process ; end arc_condition2 ;end arc_condition1 ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 71 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 72
- 19. Old style (?? implicitly implied) Where can this implicitly implied ?? be used-- the ?? operator implicitly impliedarchitecture arc_condition3 of condition3 is After an if clause (as in previous example) in an if statementbegin After an elsif clause in an if statement process (din,cs0,cs1,pol) After an until clause in a wait statement begin OK too After an assert statement if cs1 and not cs0 and pol then After a while clause in a while loop statement dout <= din ; After a when clause in a next statement elsif cs1 and not cs0 and not pol then After a when clause in an exit statement dout <= not din ; After an if clause (as in previous example) in an if generate statement else After an elsif clause in an if generate statement dout <= ( others => 0 ) ; In a boolean expression in a PSL declaration end if ; In a boolean expression in a PSL statement end process ;end arc_condition3 ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 73 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 74 There must be no ambiguity allowed-- implicit conversion NOT applied-- because of ambiguous interpretation !architecture arc_condition4 of condition4 isbegin process (din,cs0,cs1,pol) begin if cs1 and not cs0 and pol = 1 then -- error dout <= din ; More convenient elsif cs1 and not cs0 and pol = 0 then -- error Case operations dout <= not din ; else dout <= ( others => 0 ) ; end if ; end process ;end arc_condition4 ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 75 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 76
- 20. Priority encoder example (again) The old case statement case to_x01(din) is Direct inputs when "1000" | "1001" | "1010" | "1011" din(3) din(2) din(1) din(0) | "1100" | "1101" | "1110" | "1111" => high low dout <= "11" ; gs <= 1 ; priority priority when "0100" | "0101" | "0110" | "0111" => dout <= "10" ; gs <= 1 ; when "0010" | "0011" => 4 to 2 dout <= "01" ; gs <= 1 ; Priority Encoder when "0001" => dout <= "00" ; gs <= 1 ; when "0000" => dout <= "00" ; gs <= 0 ; when others => dout <= "XX" ; gs <= X ; report "unknown din" ; gs dout(1) dout(0) end case ; Group select Encoded outputs 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 77 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 78An new elegant matching case? statement Works with selected assignments toocase? din is -- using the ?= (built in matching) operator when "1---" => -- direct priority filter with - in code is dout <= "11" ; gs <= 1 ; treated as Φ -- matching selected assignment library ieee ; when "01--" => use ieee.std_logic_1164.all ; dout <= "10" ; gs <= 1 ; H is treated as 1 entity priority is L is treated as 0 when "001-" => no need for to_xo1() port ( din : in std_logic_vector(3 downto 0) ; dout <= "01" ; gs <= 1 ; dout : out std_logic_vector(3 downto 0) ) ; end priority ; when "0001" => architecture arc_priority of priority is dout <= "00" ; gs <= 1 ; begin when "0000" => with din select? -- VHDL-2008 dout <= "00" ; gs <= 0 ; dout <= "1000" when "1---" , when others => "0100" when "01--" , "0010" when "001-" , dout <= "XX" ; gs <= X ; report "unknown din" ; "0001" when "0001" ,end case ; "0000" when others ; end arc_priority ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 79 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 80
- 21. Complex assignments in process (1 of 2) -- mixed 4=>1 mux with enable entity mixedmux is port ( din : in bit_vector(3 downto 0) ; sel : in bit_vector(1 downto 0) ; conditional ena : in bit ; -- ena assignments & dout : out bit ) ; selected end mixedmux ; assignments in architecture arc_mixedmux of mixedmux is process begin process (din,sel,ena) 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 81 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 82 Complex assignments in process (2 of 2)process (din,sel,ena) begin if sel = "00" then -- conditional assignment in process dout <= din(0) when ena = 1 else 0 ; elsif sel = "01" then -- conditional assignment in process dout <= din(1) when ena = 1 else 0 ; elsif sel = "10" then -- selected assignment in process More convenient with ena select dout <= din(2) when 0 , combinatorial 0 when others ; descriptions else -- sel="11" -- selected assignment in process with ena select dout <= din(1) when 0 , 0 when others ; end if ; end process ;end arc_mixedmux ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 03 Page: 83 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 04 Page: 84
- 22. Complete sensitivity list in comb system -- complete sensitivity list for VHDL-2008 architecture arc_comrule2 of comrule2 is begin process ( all ) -- very elegant solution ! begin y <= a or b or c ; end process ; More convenient end arc_comrule2 ; sync descriptions -- good for latches too ! 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 04 Page: 85 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 05 Page: 86using rising_edge(_) with bit too, no dilemma -- using the rising_edge(_) function with bit too entity dff7 is port ( clk : in bit ; d : in bit ; q : out bit ) ; end dff7 ; architecture arc_dff7 of dff7 is Improved I/O operations begin with the ’image(_) & process ( clk ) ‘value(_) attributes begin (VHDL-93) if rising_edge(clk)then -- no more dilemma ! q <= d ; end if ; end process ; end arc_dff7 ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 05 Page: 87 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 06 Page: 88
- 23. The ‘image( ) attribute - VHDL-93 Returns a string representing the value data_type_nameimage(data_value) Usable only with scalar data types (not vectors) Useful for simulation or Verification (send strings to console) Here is an exampleprocess ( din ) -- din is integer begin assert false New to_string(_) functions report " [time=" & timeimage(now) & "]" & " [din=" & integerimage(din) & "]" severity note ;end process ; results Note: [time=100 ns] [din=0] Note: [time=200 ns] [din=3] 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 06 Page: 89 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 06 Page: 90 The to_string(_) function - VHDL-2008 to_string(_) function with more parameters Shown: units to use with time Here is an example Shown: width of the right side of decimal point with realprocess ( din ) -- din is std_logic_vector(11 downto 0) process ( din ) -- din is now real begin begin assert false assert false report " [time=" & to_string(now) & "]" & report " [time=" & to_string(now,ps) & "]" & " [din=" & to_string(din) & "]" " [din=" & to_string(din,10) & "]" severity note ; severity note ;end process ; end process ; results results Note: [time=100 ns] [din=101011001111] Note: [time=100000 ps] [din=1.0000000000] Note: [time=200 ns] [din=00001111HLXZ] Note: [time=200000 ps] [din=6.5000000000] All other old built in data types are supported too With type real you can also use other format strings like in printf of C: Data types ufixed, sfixed and float are supported too E%, e%, f%, g% 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 06 Page: 91 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 06 Page: 92
- 24. to_hstyring(_) & to_ostyring(_) functions Special functions to be used on vector types: to_hstring( vector_type ) to_ostring( vector_type ) Example with binary hex & octal presentation shown:process ( din ) -- din is std_logic_vector(11 downto 0)begin assert false expressions written report " [bin=" & to_string(din) & "]" & to ports when " [hex=" & to_hstring(din) & "]" & instantiation of " [oct=" & to_ostring(din) & "]" components severity note ;end process ; results on “101011001111” and “00001111HLXZ” Note: [bin=101011001111] [hex=ACF] [oct=5317] Note: [bin=00001111HLXZ] [hex=0FX] [oct=03XX] 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 06 Page: 93 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 94 wiring of signals constants & expressions in VHDL-87 only clean signals are possible u1: or_gate port map ( s , q , x1 ) ; In VHDL-93 wiring of constants is possibleu1: and_gate8 port map(output => y , Revision of Modes input(3 downto 0) => x(3 downto 0) , (port directions) input(7 downto 4) => 1&1&1&1’ ) ; in VHDL-2008 expressions are possible u1: or_gate port map ( not s , q , x1 ) ; 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 95 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 96
- 25. Old - Modes (port directions) Old - Modes (port directions)in buffer – The default mode – Out signal can not be externally bussed – In signal can not be written (LHS) internally – Out signal can be written (LHS) internally – In signal can only be read (RHS) internally – Out signal can also be read (RHS) internally – Should be used more often !out VHDL-2002 – Out signal can be externally bussed linkage recommends – Out signal can not be read back (RHS) internally ! – Signal passes through removing this mode – Out signal can Only be written (LHS) internally – Signal can not be read from – Signal can not be writteninout – Rarely used (usually for power supplies) – inout signal can be externally bussed – inout signal can be read back (RHS) internally – No internal restrictions (read write) 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 97 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 98 Old - Modes (port directions) New - Modes (port directions)buffer connected to out or inout from within a hierarchy in – Warning: Can not associate buffer signal with out or inout signal – The default mode – Restriction removed already on VHDL-2002 – In signal can not be written (LHS) internally – Many people did not know about it – In signal can only be read (RHS) internally – Many tools ignored the 2002 revision Will be used as normal output (not I/O) BUS out – Out signal can be externally bussed – Out signal can be read back (RHS) internally ! – Out signal can be written (LHS) internally buffer out out buffer inout inout Usually inout used for I/O – inout signal can be externally bussed – inout signal can be read back (RHS) internally – No internal restrictions (read write) Will be used as I/O BUS (synthesis tools prefer this mode) People will probably stop using buffer 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 99 8/5/2012 VHDL(13) - Amos Zaslavsky © Copyright CH 07 Page: 100

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