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Adv. FPGA Motor Control--EBV & Univ. of Koln: Embedded World 2010

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Adv. FPGA Motor Control--EBV & Univ. of Koln: Embedded World 2010

  1. 1. Advanced Motor Control with FPGA Learning Zone @ Embedded World 2010 Prof. Dr-Ing. Jens Onno Krah © 2010 Altera Corporation—Public
  2. 2. Motivation for using FPGA’s for Motor Control Reduce number of Components ΣΔ ADCs Digital Encoder Interface Fieldbus IP core Soft Core Nios® II CPU Increase Performance • No Sampling Issues (aliasing) • No Calculation Delay • High Switching Frequency Increase Flexibility • Fewer Fieldbus Option Cards • Enable Motion Control IP Prof. Dr.-Ing. Jens Onno Krah
  3. 3. 3 Layer Model Layer 3 RAM with 32-Bit data bus Software TCP / IP IRQ for Init & ASM / “C” stack Control Config. FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 6~ (state MAC BiSS filter PWM machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  4. 4. 3 Layer Model RAM with 32-Bit data bus Field Bus Layer 3 Software Real Time TCP / IP IRQ for Init & ASM / “C” stack Control Ethernet Config. FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 6~ (state MAC BiSS filter PWM machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  5. 5. Fieldbus Interface - Real Time Ethernet Real Time Ethernet Implementations Software Hard- Soft- Hard- Soft- Application ware ware ware ware layer PDO SDO PDO SDO µC Stack MAC MAC MAC Hub / Switch Hub / Switch Hub / Switch PHY PHY PHY PHY PHY PHY RJ45 RJ45 RJ45 RJ45 RJ45 RJ45 a) Standard b) ASIC c) FPGA Prof. Dr.-Ing. Jens Onno Krah
  6. 6. Digital Encoder Interface Layer 3 RAM with 32-Bit data bus Software Motor ASM / “C” TCP / IP stack IRQ for Control Init & Config. Feedback Interface FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 6~ (State MAC BiSS filter PWM machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  7. 7. BiSS® Sensor-Mode “Timing” Transmissions Delay for Calculation adjustable Compensation of Propagation Delay m * Clocks n * Clocks Compensation of Propagation Delay Request n * Clocks = tCAL 0 to ~ 6-12 µsec m * Clock = tpropagation Clock Clockrate ... 10 MHz Propagation Setup < 50 nsec Data Delay Status Delay for Calculation Start MSB LSB W&A CRC MCD Max 64 Bit 2 Bit 6 Bit 1 Bit Store Acknowledge Ready Timeout sens Encoder (Start of transmission) Data Prof. Dr.-Ing. Jens Onno Krah
  8. 8. Motor Current Measurement using SD ADCs Current Measure Layer 3 RAM with 32-Bit data bus Software TCP / IP IRQ for Init & ASM / “C” stack Control Config. FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 6~ (State MAC BiSS filter PWM machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  9. 9. High Performance Current Measurement <5A < 50 A (150 A IGBT) > 25 A SMT Shunt MIPAC Shunt Hall (LEM) ΣΔ + Opto ΣΔ (int. or ext.) ΣΔ (no Opto / Ti) FalconEye Prof. Dr.-Ing. Jens Onno Krah
  10. 10. Pulse Width Modulation - PWM Layer 3 RAM with 32-Bit data bus Software ASM / “C” TCP / IP stack IRQ for Control Init & Config. PWM FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 6~ (State MAC BiSS filter PWM machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  11. 11. Field Oriented Control Layer 3 RAM with 32-Bit data bus Field Software ASM / “C” TCP / IP IRQ for Init & Oriented stack Control Config. Control FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 (State MAC PWM BiSS filter machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  12. 12. Field Oriented Control “C” + VHDL ~ = I T + ICONT 2 D DIPEAK MIPEAK } IPEAK } min Current Control MLGD, MLGQ MLGC, MLGP KTN, KC VBUS A torque = e jδ PWM ~ (-) (+) Id, Iq I a, I b - jδ D e A MPHASE δe MRESPOLES M MRESBW 3~ speed ϕe RK MPOLES δm D GVFBT p E E d Nios II / VHDL dt VHDL Beckhoff Fast , Special (IP): VHDL Field Oriented Control + Fieldbus → 20 000 Logic Elements Economic, Universal: Nios® II processor → 6 000 Logic Elements Prof. Dr.-Ing. Jens Onno Krah
  13. 13. Nios II - Custom Instruction – Accelerating sine and cosine short i_sin(int winkel) // mit Floating Point Unit { return (short)(32767. * sin(2*PI*winkel/65536.)) ; } short sinus_table[65] = {0,804, … ,32758,32767}; short quadrant = (winkel >> 14) & 3 ; short index = (winkel >> 8) & 63 ; short rest = winkel & 255 ; val = sinus_table[index] + // 0 … 90° -> 1st quadrant (((sinus_table[index+1]-sinus_table[index])*rest)>>8) ; 1st Order Taylor Approximation: Interpolation Points / 90° Accuracy / Bit 32 10,7 64 12,7 128 14,7 Prof. Dr.-Ing. Jens Onno Krah
  14. 14. Nios II - Custom Instruction – Accelerating sine and cosine Static inline short sin(short phi) { return ALT_CT_ABSMAX_INST(val,max) ; // 20 ns bei 100 MHz } Static inline short cos(short phi) { return ALT_CT_ABSMAX_INST(val,max) ; // 20 ns bei 100 MHz } The sin and cos instructions use: - 400 Logic Elements and - 2 DSP Blocks in addition to the Nios® II processor resources (Cyclone® III) Prof. Dr.-Ing. Jens Onno Krah
  15. 15. Nios II - Custom Instruction – Accelerating PI Control PI Control Nios II C: // FOC d-current PI-control i_e = i_cmd_d - i_act_d ; if ( i_e > i_lim ) { // limiting i_e = i_lim ; } else if( i_e < -i_lim ){ i_e = -i_lim ; } u_d_integral += (i_e * Ki_d) >> 10 ; // I-part if ( u_d_integral > u_lim ){ // anti wind up u_d_integral = u_lim; } else if( u_d_integral < -u_lim ) { u_d_integral = -u_lim ; } u_d_cmd = u_d_integral + ((i_e * Kp_d) >> 10) ; // + P-part if ( u_d_cmd > u_lim ){ // limit u_d_cmd = u_lim ; } else if( u_d_cmd < -u_lim ) { u_d_cmd = -u_lim ; } Prof. Dr.-Ing. Jens Onno Krah
  16. 16. Nios II - Custom Instruction – Accelerating PI Control “C” Code: int absmax(int val,int max) { if ( val > max ) { // pos. limit ? return max ; } else if( val < -max ) { // neg. Limit ? return -max ; } else { Max. return val ; val } } Using a Custom Instruction: ALT_CT_ABSMAX_INST(val,max) ; // 10 ns at 100 MHz The absmax instruction needs 159 Logic Elements (Cyclone® III) Prof. Dr.-Ing. Jens Onno Krah
  17. 17. FalconEye FPGA - 3 Layer Model Layer 3 RAM with 32-Bit data bus Speed up Software current loop TCP / IP IRQ for Init & ASM / “C” stack Control Config. interrupt FPGA IO (3.3 V) Nios II Soft Core CPU with Customer Instructions Layer 2 (IP) Fast 32-Bit Avalon Bus & IP - IP cross connections User Programmable logic FPGA / VHDL logic EnDAT Sinc3 (State MAC PWM BiSS filter machine) FPGA IO (3.3V) MII Layer 1 Special hardware, ADC: ΣΔ IGBT Flash: Configuration PHY RS 485 and prog. memory Driver & transceiver modulator Driver Prof. Dr.-Ing. Jens Onno Krah
  18. 18. Using Logic Elements to Reduce Calculation Time 0.1 µs 15 µs 5 µs current loop execution time requested Logic Elements ~5000 LE ~7000 LE 20 000 LE sin / cos / absmax Beckhoff IP Altera low cost custom instructions VHDL current loop tightly coupled memory EtherCAT IP Prof. Dr.-Ing. Jens Onno Krah
  19. 19. Advantages of Analog Current Control: • Fast - No additional sampling delay time • No aliasing issues (due to the sampling theorem) - No sub harmonics • Simple - Low number of components R2 C R1 - + Prof. Dr.-Ing. Jens Onno Krah
  20. 20. Advantages of Digital Current Control: • Complex control algorithms Iq - Field oriented control (FOC) - Space Vector Modulation (SVM) Ψ Id - Non linear control (saturation) δ • Predictive control - Smith predictor - Luenberger observer • Digital command (reference) and controlled value DSP - Field bus process data object - Exactly repeatable digital parameters (not only a scaled potentiometer) • Remote setup and diagnostics - Access via field bus to actual values, parameters and scope functions Prof. Dr.-Ing. Jens Onno Krah
  21. 21. Advantages of FPGA based Digital Control: • All advantages of analog current control • All advantages of digital current control + On-Chip position feedback interface - Resolver Digital Converter (via ΣΔ Modulator) - SinCos Encoder with only 2µ delay (via fast SAR ADC) - Digital Encoder: SSI, BiSS, EnDAT, Hiperface DSL (via RS 485 driver) + On-Chip field bus (EtherCAT) interface (via external PHY) + On-Chip ΣΔ decimation filter for high precision multi channel analog signal processing + Extreme fast and flexible 6-phase PWM with minimal delay time + Inverter / Motor Control Intellectual Property (IP) - 3-level Inverter - Matrix Inverter Prof. Dr.-Ing. Jens Onno Krah
  22. 22. FPGA Motor Control Reference Design FalconEye-FPGA (EBV-Elektronik) BLAC Motor FPGA Eval. Board Power Electronics Prof. Dr.-Ing. Jens Onno Krah
  23. 23. Power Supply 5 / 15 Vdc BLAC FalconEye Control  Logic or IM Power Supply  125 - 400 Vdc EMI Filter PFC Ballast Power Stage 400 3~ 90-240 Vac Vdc 0 – 300 V Motor P F C Avago Avago Vbus ΣΔ Feed- Ballast back Real Time Ethernet: VHDL IGBT Signals Motor Control Motor Current ΣΔ Resolver RS 485 SVM sinc3 FB IP or ΣΔ PHY MAC Motor Control ` or NIOS II IP ` SRAM PHY USB USB PC ` Blaster Flash ` JTAG Cyclone III C 40 „C“ Motor EBV DBC3C40 – FPGA Motor Controller Control Prof. Dr.-Ing. Jens Onno Krah
  24. 24. FalconEye Demonstrator: EBV Roller Dynamometer Hall 12 – Stand 376 Prof. Dr.-Ing. Jens Onno Krah

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