9 urmila bandaru_final_paper 91-98

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9 urmila bandaru_final_paper 91-98

  1. 1. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011 Optimized SVPWM for Multilevel Inverter Bandaru Urmila G.. Pulla Reddy Engineering College, Kurnool A.P., India E-mail: urmila913@gmail.com D. Subbarayudu Brindavan Institute of Technology, Kurnool A.P., India E-mail: dsr@gmail.comThe research is financed by Asian Development Bank. No. 2006-A171(Sponsoring information)AbstractMultilevel inverters have gained interest in recent years in high-power medium-voltage industry. Thispaper considered the most popular structure among the transformer-less voltage source multilevel inverters,the diode-clamped converter based on the neutral point converter. This paper proposes a single carriermulti-modulation SVPWM technique with an optimized space vector switching sequence. Simulationresults presents comparison of single and multicarrier optimized space vector switching sequence withgeneral switching sequence of nine-level diode-clamped inverter for the parameter total harmonic distortionand fundamental component of voltage.Keywords- Multilevel inverter, SVPWM, total harmonic distortion, Diode-clamped inverter, SCMMGS,MCMMGS, SCMMOS, MCMMOS1. IntroductionMultilevel inverters have drawn tremendous interest in high-power medium-voltage industry. In literature,inverters with voltage levels three or more referred as multilevel inverters. The inherent multilevel structureincrease the power rating in which device voltage stresses are controlled without requiring higher ratings onindividual devices. They present a new set of features that suits well for use in static reactive powercompensation, drives and active power filters. Multilevel voltage source inverter allows reaching highvoltages with low harmonics without use of series connected synchronized switching devices ortransformers. As the number of voltage levels increases, the harmonic content of output voltage waveformdecreases significantly. The advantages of multilevel inverter are good power quality, low switching losses,reduced output dv/dt and high voltage capability. Increasing the number of voltage levels in the inverterincreases the power rating. The three main topologies of multilevel inverters are the Diode clampedinverter, Flying capacitor inverter, and the Cascaded H-bridge inverter by Nabae et al. (1981). The PWMschemes of multilevel inverters are Multilevel Sin-Triangle Pulse Width Modulation-SPWM and SpaceVector Pulse Width Modulation-SVPWM. Multilevel Sin-Triangle PWM involves comparison ofreference signal with a number of level shifted carriers to generate the PWM signal. SVPWM involvessynthesizing the reference voltage space vector by switching among the nearest voltage space vectors.SVPWM is considered a better technique of PWM owing to its advantages (i) improved fundamentaloutput voltage (ii) reduced harmonic distortion (iii) easier implementation in microcontrollers and DigitalSignal Processor. This paper considered the most popular structure among the transformer-less voltagesource multilevel inverters, the diode-clamped converter based on the neutral point converter proposed byCarrara et al.(1992) with SVPWM technique. This paper proposes a single carrier modulation techniquewith an optimized space vector switching sequence for multilevel inverter. Simulation results presentscomparison of single and multicarrier optimized space vector switching sequence with general switchingsequence of nine-level diode-clamped inverter for the parameter total harmonic distortion and fundamentalcomponent of voltage. 91
  2. 2. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 20112. Diode-Clamped Multilevel InverterA three-phase nine-level diode-clamped inverter is shown in Fig.1. Each phase is constituted by 16switches (eight switches for upper leg and eight switches for lower leg). Switches S a1 through Sa8 of upperleg form complementary pair with the switches Sa1’ to Sa8’ lower leg of the same phase. The complementaryswitch pairs for phase ‘A’ are (Sa1, Sa1’), (Sa2, Sa2’), (Sa3, Sa3’), (Sa4, Sa4’), (Sa5, Sa5’), (Sa6, Sa6’), (Sa7, Sa7’),(Sa8, Sa8’) and similarly for B and C phases. Clamping diodes carry the full load current by Jose Rodriguezet al.(2002)Table1 shows phase to fictitious midpoint ‘o’ of capacitor string voltage (V AO) for various switching’s. Table 1 Nine-Level Inverter Voltage States Sa1 Sa2 Sa3 Sa4 Sa5 Sa6 Sa7 Sa8 VAO 1 1 1 1 1 1 1 1 +Vdc/2 0 1 1 1 1 1 1 1 +3Vdc/8 0 0 1 1 1 1 1 1 +Vdc/4 0 0 0 1 1 1 1 1 +Vdc/8 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 -Vdc/8 0 0 0 0 0 0 1 1 -Vdc/4 0 0 0 0 0 0 0 1 -3Vdc/8 0 0 0 0 0 0 0 0 -Vdc/2 Figure 1 Circuit Diagram of 3 Phase Nine Level Diode Clamped Inverter 92
  3. 3. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 818 718 618 518 018 418 318 218 118 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 828 728 628 528 028 428 328 288 817 128 717 617 517 017 417 317 217 117 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 827 838 738 638 538 038 438 338 238 816 138 716 727 627 527 027 427 327 227 127 616 516 016 416 316 216 116 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 826 837 848 748 648 548 048 448 348 248 148 815 715 726 637 537 037 437 337 237 137 737 615 626 526 026 426 326 226 126 ⃗ ⃗ ⃗ ⃗ ⃗ 515 015 415 315 215 115 ⃗ ⃗ ⃗ 808 608 ⃗ ⃗ ⃗ 708 508 008 ⃗ ⃗ 825 836 847 747 647 547 047 447 408 308 208 108 810 710 725 736 636 536 036 436 336 347 247 157 610 625 525 025 425 325 225 236 136 ⃗ 510 ⃗ 010 ⃗ ⃗ 310 ⃗ ⃗ ⃗ 125 410 210 110 ⃗ ⃗ 846 807 ⃗ ⃗ ⃗ ⃗ 858 758 658 558 058 ⃗ 820 835 735 746 707 607 507 007 407 458 358 258 814 158 714 720 620 635 646 546 046 446 346 307 207 107 614 514 205 535 ⃗ 435 ⃗ 435 335 235 246 146 ⃗ ⃗ ⃗ ⃗ ⃗ 014 020 868 420 768 320 220 120 135 ⃗ ⃗ ⃗ 806 758 668 568 068 ⃗ ⃗ ⃗ ⃗ ⃗ 414 757 314 657 214 114 824 830 845 745 607 557 057 457 468 368 268 813 606 506 168 713 724 730 630 546 006 406 306 357 257 157 545 ⃗ 045 ⃗ 613 624 524 035 ⃗ 445 ⃗ 345 245 206 106 ⃗ 030 878 430 778 ⃗ ⃗ 513 ⃗ 013 ⃗ 420 867 330 230 130 145 ⃗ ⃗ 767 324 678 ⃗ 840 805 658 314 424 667 224 124 578 078 ⃗ ⃗ ⃗ ⃗ 756 213 567 823 834 734 313 656 556 113 067 467 478 378 278 740 507 605 056 178 812 712 723 505 ⃗ 005 456 356 367 267 167 623 634 046 540 405 612 ⃗ ⃗ 040 440 ⃗ ⃗ 305 205 256 156 512 523 435 034 877 888 ⃗ ⃗ 866 434 334 788 340 688 ⃗ ⃗ ⃗ 012 855 320 423 766 777 240 140 105 ⃗ ⃗ 800 323 223 234 577 588 088 488 ⃗ ⃗ 844 700 214 755 666 677 134 312 655 123 822 833 733 744 600 212 112 566 066 077 477 377 388 288 ⃗ ⃗ 644 500 555 711 722 622 633 544 055 455 466 366 266 277 177 188 811 533 ⃗ 044 ⃗ 000 ⃗ 611 511 522 ⃗ 033 400 ⃗ 300 355 255 155 166 ⃗ 022 433 444 ⃗ 011 865 422 876 887 787 344 687 244 200 ⃗ 100 ⃗ ⃗ 411 322 333 ⃗ ⃗ ⃗ 850 750 311 765 776 676 233 576 133 587 144 087 487 ⃗ 832 704 211 222 076 ⃗ 843 804 604 650 665 565 122 065 476 376 387 287 ⃗ 721 643 111 050 465 276 732 743 543 504 550 450 365 265 176 187 821 532 ⃗ ⃗ ⃗ ⃗ ⃗ 350 621 632 032 043 004 404 304 150 165 ⃗ 021 ⃗ 875 432 886 443 786 343 686 586 204 ⃗ ⃗ ⃗ 521 421 243 250 ⃗ ⃗ 854 860 760 775 232 575 075 143 086 486 ⃗ 321 332 675 132 ⃗ 842 803 703 754 654 660 560 121 060 460 475 375 386 286 ⃗ 221 104 831 731 742 642 603 503 554 054 454 354 360 260 275 175 186 631 531 042 ⃗ ⃗ ⃗ 303 ⃗ 203 254 154 160 542 003 403 ⃗ 885 785 685 585 142 ⃗ ⃗ 031 431 442 342 242 103 ⃗ ⃗ ⃗ 670 085 485 ⃗ 870 770 331 231 570 131 070 ⃗ 802 853 864 664 564 064 464 470 370 385 ⃗ ⃗ 764 285 741 702 753 653 553 053 453 353 364 264 270 841 170 185 641 602 502 002 402 302 202 253 153 164 541 ⃗ ⃗ 341 ⃗ ⃗ ⃗ 102 ⃗ ⃗ 041 441 241 141 ⃗ ⃗ ⃗ 880 780 680 580 080 480 ⃗ 852 863 874 774 674 474 374 380 280 ⃗ 574 074 ⃗ 701 752 763 663 563 463 363 263 274 174 063 801 601 652 163 180 ⃗ 552 052 452 ⃗ 352 ⃗ 252 152 501 ⃗ ⃗ ⃗ ⃗ ⃗ 001 401 301 201 101 ⃗ 884 784 684 584 084 484 ⃗ 862 873 773 673 573 073 473 384 284 ⃗ 373 ⃗ 751 762 662 562 062 462 362 273 173 851 262 184 651 551 051 451 351 251 162 151 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 872 283 883 783 683 583 083 483 383 ⃗ 861 761 172 772 672 572 072 472 372 272 183 661 561 061 461 361 261 161 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 782 582 382 282 ⃗ 882 682 082 482 871 771 671 071 271 171 182 571 471 371 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 881 781 681 581 081 481 381 281 181 Figure 2 Nine-Level Inverter State Space Vector Diagram3. SVPWM ImplementationImplementation of SVPWM involves (i) Identification of the sector in which the tip of the reference vectorlays (ii) Determination of the nearest three voltage space vectors (ii) Determination of the duration of eachof these switching voltage space vectors (iv) Choosing an optimized switching sequence.Space vector diagram of nine-level inverter with its 729 (=39) vectors are shown in Fig 2. Every 60 degreesconstitute a sector. Sector1 diagram is shown in Fig 3. Each sector consists of 64 regions 177 vectors.3.1 Sector and region identificationThree phase instantaneous reference voltages (1) are transformed to two phase (2). Every 60 degrees, fromzero to 360 degrees constitute a sector [4][5]. Identification of the sector in which the tip of the referencevector lies is obtained by (3). (1) 93
  4. 4. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011 √ (2) √ ( ) ; ⁄ (3)Where θ is the angle varies from 0 to 2π.Amplitude and angle of the reference vector are obtained from (3).From Park’s transformation the di-phase, α-β components are: ( ) (4) √ ⁄ (5)Region is obtained by normalizing the di-phase components of the space vector (4)-(5) of an n-levelinverter through division by V dc/n-1, where Vdc is the dc link voltage.3.2 Determination of the duration of nearest three voltage space vectorsSwitch dwelling duration is obtained from (6)-(7). ⃗ ⃗ ⃗ ⃗ (6) (7)3.3 Determination of optimized switching sequenceConsider reference vector lying in sector1 region 21. The nearest three space vectors for switchingsequence are ⃗ , ⃗ , ⃗ . ⃗ 64 ⃗ ⃗ 63 49 62 ⃗ ⃗ ⃗ 48 61 0 36 47 60 ⃗ ⃗ ⃗ ⃗ 35 46 59 25 34 45 58 ⃗ ⃗ ⃗ ⃗ ⃗ 24 33 44 57 16 23 32 0 43 56 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 15 22 31 42 55 9 14 21 30 41 54 ⃗ ⃗ ⃗ P ⃗ ⃗ ⃗ ⃗ 8 13 20 29 40 53 4 7 12 0 19 28 39 52 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ 3 6 11 18 27 38 51 1 2 5 10 17 26 37 50 ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ ⃗ Figure 3 Sector1 Regions Space Vector Representation 94
  5. 5. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011The space redundant vectors for sector1 region 21, are, for ⃗ 0 6 8, 4 5 7, 3 0 6, 2 4 5, 1 3 0 (5 redundantvectors), for ⃗ 4 6 8, 3 5 7, 2 0 6, 1 4 5 (4 redundant vectors), and for ⃗ 4 5 8, 3 0 7, 2 4 6, 1 3 5 (4redundant vectors).An optimized switching sequence starts with virtual zero vector’s state. A virtual zero vectors are withminimum offset from zero vector of two-level inverter. Based on the principles derived in literature fortwo-level inverter, for Region 21, switching sequence is 0 6 8→4 6 8→ 4 5 8→ 4 5 7→ 3 5 7→ 3 0 7→ 3 06→ 2 0 6→ 2 4 6→ 2 4 5→ 1 4 5→ 1 3 5→ 1 3 0 during a sampling interval and 1 3 0→ 1 3 5→ 1 4 5→ 24 5→ 2 4 6→ 2 0 6→ 3 0 6→ 3 0 7 → 3 5 7→ 4 5 7→ 4 5 8 → 4 6 8 → 0 6 8 during the subsequentsampling interval. This sequence uses all the space redundant vectors of each state by Anish Gopinath etal.(2007), (2009).Consider two different outer regions 59 and 60 of Figure3 for switching sequence. Three vertices of region59 are ⃗ (2 0 8, 1 4 7), ⃗ (2 4 8, 1 3 7) and ⃗ (1 4 8). Virtual zero vector is ⃗ . The optimizedswitching sequence is 2 0 8 → 2 4 8 → 1 4 8 → 1 4 7 → 1 3 7 during a sampling interval and 1 3 7 → 1 47 → 1 4 8 → 2 4 8 → 2 0 8 during the subsequent sampling interval. Considering the region 60, Virtualzero vector is ⃗ (2 4 8, 1 3 7) and ⃗ (1 4 8), ⃗ (1 3 8) are the two other vertices. The optimizedswitching sequence is 2 4 8 → 1 4 8 → 1 3 8 → 1 3 7 during a sampling interval and 1 3 7 → 1 3 8 → 1 4 8→ 2 4 8 during the subsequent sampling interval [23]. This sequence utilizes vectors. Application of usageof same number of states also for inner regions reduced the total harmonic distortion with increasedfundamental component of voltage with single carrier modulation. Extending this for region 21, thesequence is 0 6 8→4 6 8→ 4 5 8→ 4 5 7 during a sampling interval and 4 5 7→ 4 5 8 → 4 6 8 → 0 6 8during the subsequent sampling interval discarding three redundant states from each vertex.4. Simulation ResultsSimulation is carried out on nine-level diode-clamped inverter for four methods of Space Vector PWMtechnique at switching frequency 1.5 KHz for different modulation indices. (i) SCMMGS-Single CarrierMulti-Modulation for General Switching Sequence (ii) MCMMGS-Multi-Carrier Multi-Modulation forGeneral Switching Sequence (iii) SCMMOS-Single Carrier Multi-Modulation for Optimized SwitchingSequence (iv) MCMMOS-Multi-Carrier Multi-Modulation for Optimized Switching Sequence.Multi-Carrier Multi-Modulation results reduced harmonic distortion with reduced fundamental component;however Single Carrier Multi-Modulation results reduced harmonic distortion with highly improvedfundamental component of voltage.Optimized switching sequence reduces harmonic distortion compared to General switching sequence.SVPWM-SCMMGS simulation results are shown from Figure4 through Figure7 for modulation index of0.85. Figure4 comprises pole, phase and line voltage for SCMMGS method. Pole, phase and line voltagefor MCMMGS method is Figure6. Line voltage THD for SCMMGS and MCMMGS are shown in Figure5and Figure7 respectively.SVPWM-SCMMOS results at modulation index of 0.85 are shown from Figure8 through Figure11. Figure8comprises pole, phase and line voltage for SCMMOS method. Pole, phase and line voltage for MCMMOSmethod is Figure10. THD of line voltage is shown in Figure9 and Figure11 respectively for SCMMOS andMCMMOS. 95
  6. 6. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011 50 0 -50 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 50 0 Selected signal: 1 cycles. FFT window (in red): 1 cycles -50 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 50 100 0 0 -50 -100 00 0.002 0.002 0.004 0.004 0.006 0.006 0.008 0.008 0.01 0.01 0.012 0.012 0.014 0.014 0.016 0.016 0.018 0.018 0.02 0.02 Time (s) Figure 4 MCMMGS 0.85 MI Pole, Phase and Line Voltage 1 Fundamental (50Hz) = 80.82 , THD= 9.57% 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 200 Figure 5 MCMMGS 0.85 MI Line Voltage THD 50 0 -50 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 100 0 -100 Selected signal: 1 cycles. FFT window (in red): 1 cycles 1000 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 100 VabS (V) 0 0 -100 -1000 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 Time (s) Figure 6 SCMMGS 0.85 Time (s) Phase MI Pole, and Line Voltage 1 Fundamental (50Hz) = 97.01 , THD= 10.20% 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 200 Figure 7 SCMMGS 0.85 MI Line Voltage THD 96
  7. 7. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011 50 0 -50 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 100 0 -100 0 0.002 Selected signal: 1 0.008 0.004 0.006 cycles. FFT window (in 0.014 1 cycles 0.01 0.012 red): 0.016 0.018 0.02 100 50 0 0 -50 -100 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 Figure 8 MCMMOS 0.85 MI(s) Time Pole, Phase and Line Voltage 1 Fundamental (50Hz) = 82.03 , THD= 10.87% 0.5 0 0 20 40 60 80 100 120 140 160 180 200 Figure 9 MCMMOS 0.85 MI Line Voltage THD 50 0 -50 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 100 0 -100 Selected signal: 1 cycles. FFT window (in red): 1 cycles 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 100 100 0 0 -100 -100 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 Figure 10 SCMMOS 0.85 MI Pole, Phase and Line Voltage Time (s) 1 Fundamental (50Hz) = 97.13 , THD= 9.54% 0.5 0 0 20 40 60 80 100 120 140 160 180 200 Figure 11 SCMMOS 0.85 MI Line Voltage THDTable2 gives the Total harmonic Distortion and fundamental component of line voltage for normalmodulation range.Figure12 shows chart of Modulation Index Vs THD of line voltage. 97
  8. 8. Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online)Vol 2, No 4, 2011 Table 2 Modulation Index Vs THD and Fundamental Component of Voltage MI SCMMGS MCMMGS SCMMOS MCMMOS THD V1 THD V1 THD V1 THD V1 0.866 9.42 98.96 11.79 87.03 9.17 98.98 11.89 87.52 0.85 10.20 97.01 9.57 80.82 9.54 97.13 10.87 82.03 0.8 12.65 90.91 9.45 76.73 10.54 91.5 9.99 78.05 0.75 15.65 84.79 15.22 70.38 10.97 85.64 13.26 75.1 0.7 19.35 78.69 18.37 56.52 12.75 80.01 11.47 65.67 0.6 26.89 66.32 25.67 49.29 12.96 68.39 15.02 60.27 30 SCMMGS 25 MCMMGS SCMMOS MCMMOS 20 15 10 5 0.6 0.65 0.7 0.75 0.8 0.85 0.9 Figure 12 Mi Vs THD of Nine-Level Inverter4. References Nabae, Takahashi, Akagi.(1981) “A neutral-point clamped PWM inverter”, IEEE Transactions on I.A., Vol. IA-17, No. 5, pp. 518-523. Carrara, Gardella, Marchesoni, Salutari, and Sciutto, (1992) “ A New Multilevel PWM Method: A theoretical Analysis”, IEEE Transactions on Power Electronics, Vol. 7, No. 3, July, pp.497-505. José Rodríguez, Jih-Sheng Lai, Fang Zheng Peng (2002) “Multilevel Inverters: A Survey of Topologies, Controls, and Applications”, IEEE Trans., VOL. 49, NO. 4, AUGUST Anish Gopinath, Baiju, (2007) “Space Vector PWM for Multilevel Inverters- A Fractal Approach” PEDS, Vol.56, No. 4, April, pp 1230-1237 Anish Gopinath, Aneesh Mohammed, and Baiju, (2009) “Fractal Based Space Vector PWM for Multilevel Inverters-A Novel Approach” IEEE Transactions on Industrial Electronics, Vol.56, No. 4, April, pp 1230-1237 98

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