Timer

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Timer

  1. 1. Programmable <br />Interval<br /> timer <br />8253 / 8254<br />
  2. 2. WHY 8253???<br />
  3. 3. 8253 VS 8254<br />
  4. 4. 8254 BLOCK<br />
  5. 5. BLOCK DIAGRAM OF 8254<br />
  6. 6.
  7. 7.
  8. 8. 8254 PIN DIAGRAM<br />
  9. 9. CONTROL WORD FORMAT<br />
  10. 10.
  11. 11. Modes of operation<br /><ul><li>Mode 0: INTERRUPT ON TERMINAL COUNT
  12. 12. The output becomes a logic 0 when the control word is written
  13. 13. Remains low even after count value loaded in counter
  14. 14. Counter starts decrementing after falling edge of clock
  15. 15. The OUT goes high upon reaching the terminal count & remains high till reloading
  16. 16. OUT can be used as interrupt
  17. 17. Writing a count register , when previous counting is in process  first byte when loaded stops the previous count,  second byte when loaded starts new count
  18. 18. Gate high  normal counting
  19. 19. Gate low  counting terminated and current count latched till GATE goes high again</li></li></ul><li>Mode 0: INTERRUPT ON TERMINAL COUNT<br />
  20. 20. Mode 1: One-shot mode. <br /><ul><li>monostablemultivibrator
  21. 21. gate input is used as trigger input
  22. 22. output remains high till the count is loaded
  23. 23. After application of trigger, output goes low and remains low till count becomes zero
  24. 24. Another count loaded, when output already low it does not disturb counting until a new trigger is applied at the gate
  25. 25. New counting starts after new trigger pulse</li></li></ul><li>Mode 1: One-shot mode<br />
  26. 26. <ul><li>Mode 2: RATE GENERATOR / DIVIDE BY N COUNTER
  27. 27. When N is loaded as count  after N pulses  OUT goes low for only one clock cycle then, count N is reloaded  OUT becomes high for N clock pulses
  28. 28. The number of clock pulses between the two low pulses is equal to the count loaded
  29. 29. gate  logic 0  no counting
  30. 30. Gate  logic 1  normal counting</li></li></ul><li>Mode 3: SQUARE WAVE RATE GENERATOR<br /><ul><li>When count N loaded is even  output remains HIGH for half the count and LOW for the rest half of the count
  31. 31. When count N loaded is odd  output remains HIGH for (N+1)/2 and low for (N-1)/2.
  32. 32. Repeated operation gives square wave
  33. 33. Generates a continuous square-wave with G set to 1.
  34. 34. If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.</li></li></ul><li>Mode 3: square wave generator<br />
  35. 35. Mode 4: Software triggered Strobe<br /><ul><li>After mode is set output goes high
  36. 36. When count is loaded counting down starts
  37. 37. On reaching terminal count output goes low for only one clock cycle, and then again output goes HIGH
  38. 38. The above said low pulse can be used as a strobe for interfacing MP with peripherals
  39. 39. When GATE is LOW  counting is inhibited and count is latched
  40. 40. If a new count is loaded while counting, previous counting stops and new counting started in next clock cycle</li></li></ul><li>Mode 4: Software triggered Strobe<br />
  41. 41. 20<br />Mode 5: Hardware triggered Strobe<br /><ul><li>This mode generates a strobe in response to the rising edge at the trigger
  42. 42. Mode is used to generate a delayed strobe in response to an externally generated signal
  43. 43. Once mode is programmed and counter loaded, OUT goes HIGH
  44. 44. Counter starts counting after the rising edge of the trigger (GATE)
  45. 45. The OUTPUT goes LOW for one clock period, when the terminal count is reached
  46. 46. Output will not go LOW until the counter content becomes zero after the rising edge of any trigger
  47. 47. GATE is used as trigger input</li></li></ul><li>Mode 5: Hardware triggered Strobe<br />
  48. 48.
  49. 49. Read Operations<br />There are three possible methods for reading the counters:<br /><ul><li> a simple read operation
  50. 50. the Counter Latch Command
  51. 51. the Read-Back Command</li></ul>Simple read operation:<br /><ul><li> The Counter which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic.
  52. 52. Otherwise, the count may be in the process of changing when it is read, giving an undefined result.</li></li></ul><li>Counter Latch Command:<br /><ul><li> SC0, SC1 bits select one of the three Counters
  53. 53. two other bits, D5 and D4, distinguish this command from a Control Word
  54. 54. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored.
  55. 55. The count read will be the count at the time the first Counter Latch Command was issued.</li></li></ul><li>Read-back control command:<br /><ul><li>The read-back control, word is used, when it is necessary for the contents of more than one counter to be read at a same time.</li></ul>Count : logic 0, select one of the <br />Counter to be latched<br />Status : logic 0, Status must be latched to be read status of a counter and is accessed by a read from that counter<br />
  56. 56. Status register:<br /><ul><li>shows the state of the output pin
  57. 57. check the counter is in NULL state (0) or not
  58. 58. how the counter is programmed </li>

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