FPGAs for speed and flexibility


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Learn about fpga-based system design for embedded computing I/O signal processing applications. This video discusses how Advanced Xilinx Virtex and Altera Stratix FPGAs make use of multiple digital clock managers and simultaneous parallel execution to rapidly compute a set of integrated processes including FFT, SERDES, FIFO management, logic sequencing, DDR control, and more. With integrated I/O and enablers such as a soft CPU and IP cores, plus tools such as Xilinx ISE, Altera Quartus, SimuLink, and MathLab; the FPGA can process logic much faster than any real-time system with less effort than ever before.

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FPGAs for speed and flexibility

  1. 1. FPGAs for Speed and Flexibility By: Rowland S. Demko Date: Sept’2011
  2. 2. Say What?• High Speed I/O Control• FPGA I/O Flexibility• Processing Power• Communications, Enablers, & Logic• Putting It All Together• Sophisticated Tools• You Can’t Do More for Less
  3. 3. High Speed I/O Control I/O LinesCPU PCI Bus FPGA Modulewith with Integrated I/ORTOS I/O Module nanoseconds1 usec I/O Lines Approaching 1000x Faster
  4. 4. FPGA I/O FlexibilitySmall FPGAs Front FPGA Rear FPGA I/Owith Fixed I/O I/O Configurations ConfigurabilityConfigurations PMC XMC AXM Mezzanine Modules:Supported on: Digital: AXM-D0xIP-EP20x Analog: AXM-Axx Supported on: I/O Types: PMC-LX/SX LVCMOS, LVTTL, PMC-VLX/VSX LVDS, eLVDS XMC-VLX/VSX
  5. 5. Processing Power• It’s all about Speed – IP-EP20x @ 125MHz – PMC-LX/SX @ 500MHz – PMC/XMC –VLX/VSX @ 550MHz• An then it’s about Simultaneous Parallel Execution – IP-EP20x DCM= None…1 Clock – PMC-LX/SX DCM= 8 – PMC/XMC –VLX/VSX DCM= 12
  6. 6. FPGA I/O Overview What have we learned so far… Faster More FPGAs are: Than a Powerful Front I/O Speeding? than…? Rear I/O Connector Connector FPGA PMC/XMC-Module I/O Lines I/O Lines FPGA Device BUS BUS Inter INTFCEI/O faceTypes:TTL,LVDS, I/O Types:RS422, LVCMOS, LVTTL,RS485, LVDS, eLVDSMore -6-
  7. 7. Communications, Logic & Enablers FPGA PMC/XMC-ModuleFront I/O Rear I/OConnector Connector FPGA DeviceI/O LOGIC I/O LinesTypes: - Traditional VHDLTTL, - IP CoresLVDS, Either:RS422, ENABLERS PCI, - Soft Core CPU BUSRS485, PCIX, - Operating System INTFCEMore PCIe - HLL Coded Logic Communications: - Front & Rear I/O - Bus Interface -7-
  8. 8. Putting it all Together Components: - 6 DCMs FPGA PMC/XMC-Module - FFT using DSPs - Logic Sequencer and FIFO Mgmt on Soft Core with C Language Logic I/O Lines FPGA Device DDR Apparatus DDR Control@ Controller @ FFT 1MHz 200MHz Image Process@ SDRAM 500MHz BUS Logic Intfce & SERDES Sequence SDRAM @ Control@ Either: & FIFO BUS PCI,AXM-D0x 400MHz Mgmt@ 100MHz INTFCE PCIX, 200MHz PCIe -8-
  9. 9. Sophisticated Tools• Xilinx ISE Foundation – Development• For FPGA Logic Debug and Timing Analysis – Xilinx:: Chipscope – Altera:: SignalTap• For Modeling and Process Simulation – SimuLink – MathLab
  10. 10. You Can’t Do More for Less• Process Logic Faster than any Real Time System• Soft-Cores enable powerful Customization of Capabilities and Re-Use• Off-the-Shelf I/O Customization• Scalability• Designed to Work as Independently as necessary• Applications: Control, DSP, Communications, RT Simulation…..You Name it
  11. 11. Looking to Deploy and FPGA ? Call Us: Acromag, Inc 248-295-0310 - 11 -