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Al2ed chapter12

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Al2ed chapter12

  1. 1. MIPS Processor Chapter 12 S. Dandamudi
  2. 2. Outline <ul><li>Introduction </li></ul><ul><li>Evolution of CISC Processors </li></ul><ul><li>RISC Design Principles </li></ul><ul><li>MIPS Architecture </li></ul>
  3. 3. Introduction <ul><li>CISC </li></ul><ul><ul><li>Complex instruction set </li></ul></ul><ul><ul><ul><li>Pentium is the most popular example </li></ul></ul></ul><ul><li>RISC </li></ul><ul><ul><li>Simple instructions </li></ul></ul><ul><ul><ul><li>Reduced complexity </li></ul></ul></ul><ul><ul><li>Modern processors use this design philosophy </li></ul></ul><ul><ul><ul><li>PowerPC, MIPS, SPARC, Intel Itanium </li></ul></ul></ul><ul><ul><ul><ul><li>Borrow some features from CISC </li></ul></ul></ul></ul><ul><ul><li>No precise definition </li></ul></ul><ul><ul><ul><li>We can identify some common characteristics </li></ul></ul></ul>
  4. 4. Evolution of CISC Processors <ul><li>Motivation to efficiently use expensive resources </li></ul><ul><ul><li>Processor </li></ul></ul><ul><ul><li>Memory </li></ul></ul><ul><li>High density code </li></ul><ul><ul><li>Complex instructions </li></ul></ul><ul><ul><ul><li>Hardware complexity is handled by microprogramming </li></ul></ul></ul><ul><ul><ul><li>Microprogramming is also helpful to </li></ul></ul></ul><ul><ul><ul><ul><li>Reduce the impact of memory access latency </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Offers flexibility </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Low-cost members of the same family </li></ul></ul></ul></ul></ul><ul><ul><li>Tailored to high-level language constructs </li></ul></ul>
  5. 5. Evolution of CISC Designs (cont’d)
  6. 6. Evolution of CISC Designs (cont’d) <ul><li>Example </li></ul><ul><ul><li>Autoincrement addressing mode of VAX </li></ul></ul><ul><ul><ul><li>Performs the following actions: </li></ul></ul></ul><ul><ul><ul><li>(R2) = (R2) + R3; R2 = R2 + 1 </li></ul></ul></ul><ul><ul><li>RISC equivalent </li></ul></ul><ul><ul><ul><li>R4 = (R2) </li></ul></ul></ul><ul><ul><ul><li>R4 = R4 + R3 </li></ul></ul></ul><ul><ul><ul><li>(R2) = R4 </li></ul></ul></ul><ul><ul><ul><li>R2 = R2 + 1 </li></ul></ul></ul>
  7. 7. Why RISC? <ul><li>Simple instructions </li></ul><ul><ul><li>Complex instructions are mostly ignored by compilers </li></ul></ul><ul><ul><ul><li>Due to semantic gap </li></ul></ul></ul><ul><li>Few data types </li></ul><ul><ul><li>Complex data structures are used relatively infrequently </li></ul></ul><ul><ul><li>Better to support a few simple data types efficiently </li></ul></ul><ul><ul><ul><li>Synthesize complex ones </li></ul></ul></ul><ul><li>Simple addressing modes </li></ul><ul><ul><li>Complex addressing modes lead to variable length instructions </li></ul></ul><ul><ul><ul><li>Lead to inefficient instruction decoding and scheduling </li></ul></ul></ul>
  8. 8. Why RISC? (cont’d) <ul><li>Large register set </li></ul><ul><ul><li>Efficient support for procedure calls and returns </li></ul></ul><ul><ul><ul><li>Patterson and Sequin’s study </li></ul></ul></ul><ul><ul><ul><ul><li>Procedure call/return: 12  15% of HLL statements </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Constitute 31  33% of machine language instructions </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Generate nearly half (45%) of memory references </li></ul></ul></ul></ul></ul><ul><ul><li>Small activation record </li></ul></ul><ul><ul><ul><li>Tanenbaum’s study </li></ul></ul></ul><ul><ul><ul><ul><li>Only 1.25% of the calls have more than 6 arguments </li></ul></ul></ul></ul><ul><ul><ul><ul><li>More than 93% have less than 6 local scalar variables </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Large register set can avoid memory references </li></ul></ul></ul></ul>
  9. 9. RISC Design Principles <ul><li>Simple operations </li></ul><ul><ul><li>Simple instructions that can execute in one cycle </li></ul></ul><ul><ul><ul><li>Operations can be hardwired (see next figure) </li></ul></ul></ul><ul><li>Register-to-register operations </li></ul><ul><ul><li>Only load and store operations access memory </li></ul></ul><ul><ul><li>Rest of the operations on a register-to-register basis </li></ul></ul><ul><li>Simple addressing modes </li></ul><ul><ul><li>A few addressing modes (1 or 2) </li></ul></ul><ul><li>Large number of registers </li></ul><ul><ul><li>Needed to support register-to-register operations </li></ul></ul><ul><ul><li>Minimize the procedure call and return overhead </li></ul></ul>
  10. 10. RISC Design Principles (cont’d)
  11. 11. RISC Design Principles (cont’d) <ul><li>Fixed-length instructions </li></ul><ul><ul><li>Facilitates efficient instruction execution </li></ul></ul><ul><li>Simple instruction format </li></ul><ul><ul><li>Fixed boundaries for various fields </li></ul></ul><ul><ul><ul><li>opcode, source operands,… </li></ul></ul></ul><ul><li>Other features </li></ul><ul><ul><li>Tend to use Harvard architecture </li></ul></ul><ul><ul><li>Pipelining is visible at the architecture level </li></ul></ul>
  12. 12. MIPS Architecture <ul><li>Registers </li></ul><ul><ul><li>32 general-purpose </li></ul></ul><ul><ul><ul><li>Identified as $0, $1, …,$31 </li></ul></ul></ul><ul><ul><ul><li>Register $0 is hardwired to zero </li></ul></ul></ul><ul><ul><ul><ul><li>Used when zero operand is needed </li></ul></ul></ul></ul><ul><ul><ul><li>Register $31 is used as the link register </li></ul></ul></ul><ul><ul><ul><ul><li>Used to store the return address of a procedure </li></ul></ul></ul></ul><ul><ul><li>A Program counter (PC) </li></ul></ul><ul><ul><li>2 special-purpose </li></ul></ul><ul><ul><ul><li>HI and LO registers </li></ul></ul></ul><ul><ul><ul><ul><li>Used in multiply and divide operations </li></ul></ul></ul></ul>
  13. 13. MIPS Architecture (cont’d)
  14. 14. MIPS Architecture (cont’d) <ul><li>MIPS registers and their conventional usage </li></ul>
  15. 15. MIPS Architecture (cont’d) <ul><li>MIPS addressing modes </li></ul><ul><ul><li>Bare machine supports only a single addressing mode </li></ul></ul><ul><ul><ul><li>disp(Rx) </li></ul></ul></ul><ul><ul><li>Virtual machine provides several additional addressing modes </li></ul></ul>
  16. 16. Memory Usage Placement of segments allows sharing of unused memory by both data and stack segments Last slide

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