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fco-lecture-8086

  1. 1. Introduction to 8086 Microprocessor Unit – 11 (GTU Syllabus) Chapter – 2 & 4 From the Book of Sunil Mathur, © 2011 by PHI
  2. 2. OutlineUnit No. 11: Introduction to Intel 8086ArchitectureChapter 2: Introduction to 8086 2.1. Introduction to 8086 2.2. The 8086 Microprocessor 2.2.1 BIU (BUS Interface Unit) 2.2.2 EU (Execution Unit)Chapter 4: Instructions Set of 8086 4.1 Introduction to instructions set of8086 4.2.1 Data Addressing Modes 4.3 Instruction Format 4.5. Instruction set of 8086 4.5.1 Data Transfer Instructions 4.5.2 Arithmetic Instructions 4.5.3 Logical Instructions
  3. 3. OutlineChapter 2: Introduction to 8086 2.1. Introduction to 8086 2.2. The 8086 Microprocessor 2.2.1 BIU (BUS Interface Unit) 2.2.2 EU (Execution Unit)
  4. 4. 2.1 Introduction to 8086 Microprocessor 8086 is next generation microprocessor and it iscompletely different from its predecessor 8085. Microprocessor8086 was introduced in 1978. Since its introduction, thearchitecture of 8086, so-called X86 architecture has undergonefive major stages i.e. 8086, 8088, and 80186, 80188 are themembers of the first generation of 80X86 family. The nextgeneration are the 80286 followed by the 80386, and then the80486. The Pentium is the fifth generation Intel microprocessor.Each generation built upon the basic concept of the previous withadditional features and improved performance.The 8086 was the first 80X86 families and is the basis for all Intelmicroprocessors that followed. It was a 16-bit microprocessor andsignificantly differ from the earlier 8-bit devices. It has 20 addresslines and capable of addressing 1 Mbyte memory space. Thevarious versions of the 8086 are operated on 5, 8 and 10 MHzclock frequencies. 4
  5. 5. 2.2 The 8086 Microprocessor The block diagram of 8086 can be represented asshown in Fig. 2.1 see next slide no.7. The 8086consists of two main functional unit/sections, namelythe BIS (Bus Interface Unit) and EU (Execution Unit).The major reason for this separation is to increasethe processing speed of the processor. These twounits are independent of each other and behave asseparate operational processors.The EU contains the ALU, flags and general purposeregisters. The EU carries out all the arithmetic andlogical operations. All the registers in the 8086 are16-bit wide, though 16 bit data registers can be usedas two 8-bit data registers. EU is responsible forexecuting the instructions of the programs and to 5carry out the required processing
  6. 6. 2.2 The 8086 MicroprocessorThe BIU has to interact with memory and input and output devices infetching the instructions and data required by the EU. The BIU controlsthe address, data and control buses. The instruction fetching andqueuing, operand fetch and store, and address relocation are theoperations performed by the BIU. When EU is decoding and instructionsor executing instructions inside the microprocessor, the BIU prefetchesinstructions from memory and stores them in the instructions queue forfaster processing. Upto 6 bytes of the instruction, stream can be queuedwhile waiting for decoding and execution. With the help of a queuingmechanism of instructions, stream increases the efficiency of memoryutility. Whenever there is room for at least 2 byts in the queue, the BIUwill fetch a word from memory and load it into the queue. Due to thisqueuing mechanism of instructions, stream greatly reduces dead-time onthe memory bus. The queue acts as a FIFO (first-in first-out) buffer btn.the BIU and EU. The EU takes out instruction bytes as and whenrequired. The first byte, into the queue, immediately goes to the EU whenthe queue is empty after the execution of a branch instruction. Also this isthe only occasion when the processor has to wait for instruction (i.e. whenthe queue is flushed after a control transfer instruction). Otherwise, all theother times the execution unit receives pre-fetched instructions from the 6BIU queue.
  7. 7. 2.2 The 8086 Microprocessor AX BX CX DX Figure 2.1 Block diagram of 8086 7
  8. 8. 2.2 The 8086 MicroprocessorArchitecture of 8086 The architecture of 8086 includes  Arithmetic Logic Unit (ALU)  Flags  General registers  Instruction byte queue  Segment registers 8
  9. 9. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU) The BIU has 1. Instruction stream byte queue 2. A set of segment registers 3. Instruction pointer 9
  10. 10. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU)Instruction stream byte queue: Microprocessor 8086 consists of a FIFO (first in first out) registers set arranged like a pipe and called queue. The BIU continuously fetch operations from the memory while the processor is executing the current instructions. BIU unit stores the fetched bytes in the queue and the EU will read these bytes from the queue as and when it requires. The memory interface is usually much slower than the processor execution time, so this decouples the memory cycle time from the execution time.Segment registers: The memory of 8086 is of 1 MB which is divided into segments or we can say that the memory of 8086 is segmentized. 10
  11. 11. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU)Segment registers:8086 consists of four 16-bit segment registers: the Code Segment (CS), Data Segment (DS), Stack Segment (SS) and Extra Segment (ES) and these registers are used with the 16-bit pointer, Index and Base registers to generate the 20-bit physical address required to allow the 8086 to address 1 MB memory. The segment registers point to the four immediately addressable segments. The Segmented architecture was used in the 8086 to keep compatibility with earlier processors such as the 8085. It is one of the most significant elements of the Intel Architecture. 11
  12. 12. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU)Segment registers: The memory of 8086 is divided into 4 segments registers namely (i) Code segment (program memory) (ii) Data segment (data memory) (iii) Stack memory (stack segment) and (iv) Extra memory (extra segment) and these registers are used with the 16-bit pointer, Index and Base registers to generate the 20-bit physical address required to allow the 8086 to address 1 MB memory. The segment registers point to the four immediately addressable segments. Program memory – Program can be located anywhere in memory Data memory – The processor can access data in any one out of 4 available segments Stack memory – A stack is a section of the memory set aside to store addresses and data while a subprogram executes Extra segment – This segment is also similar to data memory where additional data may be stored and maintained 12
  13. 13. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU) The Segmented architecture was used in the 8086 to keep compatibility with earlier processors such as the 8085. It is one of the most significant elements of the Intel Architecture. (a) Code Segment (CS): CS is a 16 – bit register which stores the based address of 64 KB segment and microprocessor instructions or programs. The instructions point is the by default register used by the microprocessor to access the instructions from the CS. Like any other segment registers, the code segment (CS) register cannot be changed directly. During the execution of the far jump, far call and far instructions, the CS register is automatically updated. (b) Stack Segment (SS): SS is also a 16 bit register containing offset address of the 64 KB segment. This segment is used for stack memory which operates on LIFO (last in first out). By default, the stack pointer (SP) and base pointer (BP) registers are the pointer registers. PUSH and POP are the main instructions to load and fetch a data from the stack segment (SS). This segment register (like other segment registers) cannot be initialized by loading the immediate value in the SS register. It 13 can be changed directly using POP instruction.
  14. 14. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU)(c) Data Segment (DS): The data segment (DS) register is also a 16 bit register which holds the logical address of the 64 KB long data segment. The data segment is used to store the data. The by default registers of this segment are AX, BX, CX , DS and index register (SI, DI). This segment register initialized by loading the immediate value in the DS register but can be changed directly using POP and LDS instructions. (d) Extra Segment (ES): This is similar to the CS, SS and DS, the extra segment (ES) is also a 16 bit register which contains the starting address of the 64 KB segment. The segment defined by the ES register is used to store data. The by default registers of this segment are AX, BX, CX , DS and index register (SI, DI). This segment by default, is the destination location for the string data which are always pointed by the DI register. We cannot initialized the ES register by loading immediate value in it. It can be changed using POP and LES instructions. All the above stated segments have their own by default pointers but it is possible to change default segments (except Instruction pointer (IP)) used by general and index registers by prefixing instructions with a CS, 14 SS, DS or ES prefix followed by a colon.
  15. 15. 2.2 The 8086 Microprocessor2.2.1 Bus Interface Unit (BIU)Instruction Point (IP) and address summationThe IP contains the offset or logical address of the next byte to be read from the code segment. In fact, it shows the distance of the current location, in bytes, from the base address given by the current code segment (CS) register. The contents of the CS shifted left by four bit 15 moves to the bit 19 position. The lowest four bits are filled with zeros or the CS register value is multiply by decimal 16 or hexa decimal 10 H. The resulting value is added to the instruction pointer contents to make up a 20 bit physical address. The CS makes up a 0 segment base address and the IP is looked as an offset into this segment. 15 Segment register CS Offset value (16 bits) X16 or x 10H IP Segment register (16 bits) |0|0|0|0 Add Adder 20 – bit address Physical address (20 bits) 20 – bit address 15 Fig.: Generation of 20 bit physical address
  16. 16. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU) The execution unit consists of four 16-bit general purpose data registers which can be used as eight 8 bit data registers, four 16 bit pointers and base registers and one 16 bit flag register. The Execution Unit (EU) has i. Control unit ii. Instruction decoder iii. Arithmetic and Logical Unit (ALU) iv. General registers v. Flag register 16
  17. 17. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)i. Control unit is responsible for the co- ordination of all other units of the processorii. The instruction decoder translates the instructions fetched from the memory into a series of actions that are carried out by the EUiii. ALU performs various arithmetic and logical operations over the data 17
  18. 18. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)The execution unit consists of four 16 bit general purpose data registers which can be used as eight 8 bit data registers, four 16 bit pointers and base registers and one 16 bit flag register.General purpose data- RegistersMicroprocessor 8086 consists of four 16 bit data regisers AX, BX, CX and DX and each of these registers can be divided into two parts as higher and lower part to store 8 bit data. These are shown in next Table the slide no. 19 18
  19. 19. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)General purpose data- Registers Table 2.1 Data Register of 8086 19
  20. 20. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)General purpose data- Registers General registers are used for temporary storage and manipulation of data and instructions Accumulator register (AX) consists of two 8-bit registers AH and AL each, which can be combined together and used as a 16-bit register AX Accumulator can be used for I/O operations and string manipulation 20
  21. 21. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)General purpose data- Registers Base register (BX) consists of two 8-bit registers BH and BL, which can be combined together and used as a 16-bit register BX BX register usually contains a data pointer used for based, based indexed or register indirect addressing Count register (CX) consists of two 8-bit registers CH and CL, which can be combined together and used as a 16-bit register CX Count register can be used as a counter in string manipulation and shift/rotate instructions 21
  22. 22. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)General purpose data- Registers Data register (DX) consists of two 8-bit registers DH and DL, which can be combined together and used as a 16-bit register DX Data register can be used as a port number in I/O operations In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number 22
  23. 23. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)Pointers and base registers: 23
  24. 24. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)Pointers and base registers: Stack Pointer (SP) is a 16-bit register pointing to program stack Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data addresses in string manipulation instructions. 24
  25. 25. Flag register 15 0 Carry flag Overflow Direction Parity flag Interrupt enable Auxiliary flag Trap Zero Sign Figure: Format of the flag registerMicroprocessor 8086 consist of 16 bit flag register. The flag register is a set of 16 independent flip-flops. Out ofthese 16 flip-flops, 6 flip-flops are used to indicate some data conditions and 3 flip-flops are used tocontrol some machine control operation and the remaining flip flops are reserved for future use/upcomingmicroprocessors.
  26. 26. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)(a) Status- Flags 1) Zero Flag (ZF) - set if the result is zero. 2) Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation 3) Sign Flag (SF) - set if the most significant bit of the result is set. 4) Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. 5) Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register. 6) Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand 26
  27. 27. 2.2 The 8086 Microprocessor2.2.2 Execution Unit (EU)(a) Control-Flags 1. Single-step Trap Flag (TF) - if set then single-step interrupt will occur after the execution of the next instruction. This flag is used for single step debugging. 2. Interrupt-enable Flag (IF) – This flag is used to mask/unmask the maskable interrupt. When this flag is set, maskable interrupts will cause the microprocessor to transfer its control to an interrupt vector specified location. 3. Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto- incremented. 27
  28. 28. OutlineChapter 4: Instructions Set of 8086 4.1 Introduction to instructions set of8086 4.2.1 Data Addressing Modes 4.3 Instruction Format 4.5. Instruction set of 8086 4.5.1 Data Transfer Instructions 4.5.2 Arithmetic Instructions 4.5.3 Logical Instructions
  29. 29. 4.1 Introduction to instructions set of 8086Program is a set of instructions written to solve a problem. Instructions arethe directions which a microprocessor follows to execute a task or part of atask. Broadly, computer language can be divided into two parts as high-levellanguage and low level language. Low level language are machine specific.Low level language can be further divided into machine language andassembly language.Machine language is the only language which a machine can understand.Instructions in this language are written in binary bits as a specific bit pattern.The computer interprets this bit pattern as an instruction to perform aparticular task. The entire program is a sequence of binary numbers. This isa machine-friendly language but not user friendly. Debugging is anotherproblem associated with machine language.To overcome these problems, programmers develop another way in whichinstructions are written in English alphabets. This new language is known asAssembly language. The instructions in this language are termed mnemonics.As microprocessor can only understand the machine language somnemonics are translated into machine language either manually or by aprogram known as assembler.Efficient software development for the microprocessor requires a complete familiaritywith the instruction set, their format and addressing modes. Here in this chapter, we willfocus on the addressing modes and instructions formats of microprocessor 8086.
  30. 30. 4.2.1 Data Addressing ModesThe 8086 microprocessor introduces many new technique to access thememory by introduction of many more types of addressing modes. Withthese new memory related addressing modes, it can access memory inmany different ways and these addressing mode provide flexibility to theprocessor to access memory, which in turn allows the user to accessvariables, array, records, pointers, and other complex data types in amore flexible manner.Microprocessor 8086 addressing modes is the first step towards theunderstanding of 8086 assembly language. Microprocessor 8086 has allthe five data addressing modes available in 8085 i.e. implied, register,immediate, direct and register indirect. The register indirect addressingmode in 8086 works with SI, DI, BX and BP registers.Apart from these, 8086 also have five more addressing modes andthese are1. Base addressing mode2. Index addressing mode3. Based index addressing mode4. Based indexed with displacement addressing mode5. String addressing mode
  31. 31. 4.2.1 Data Addressing ModesDifferent addressing modes may take different amounts of time to computethe effective address. Complex addressing modes take more time tocompute the effective address than the simpler addressing modes.Complexity of an addressing mode will go on increasing with the numberof terms in the addressing mode. e.g. [BX] [DI] is more complex than [DI]similarly disp [BX] [DI] is more complex than [BX] [DI].The displacement in all the memory-related addressing modes can be asigned 8 bit constant or a signed 16 bit constant. For 8 bit displacementthe offset is in the range of -128 .. + 127 and the instruction will be shorterand faster as compared to the instructions which uses the 16 bit signeddisplacement. Always preferable to use a small displacement (8 bit) and alarge number in the registers(s) instead of using large displacement (16bit) and small value in the registers(s) because the size of the value in theregister does not affect the execution time or size.
  32. 32. 4.2.1 Data Addressing ModesImmediate addressing mode: In immediate addressing mode the operands are specified within the instruction itself. The immediate operand can only be the source operand e.g. MOV AX, 2500H Here the immediate data is 2500H and the data itself is provided in the instructionRegister addressing mode: Most 8086 instructions can operate on the 8086s general purpose register set and the contents of a register can be accessed by specifying the name of the register as an operand to the instruction. e.g. the following MOV instructions copies the data from the source operand to the destination operand MOV AX, BX MOV DL, AL MOV SI, DX Pls. note that the 8 and 16 bit registers are the valid operands for this instruction. The only restriction is that both operands must be of the same size. The registers are the best place to keep often used variables. Instructions using the registers are shorter and faster than those that access memory. Segment register can never be used as data registers to hold arbitrary values. They should be only contain segment address.
  33. 33. 4.2.1 Data Addressing ModesDirect addressing mode /the displacement only addressing mode– Direct addressing mode displacement only addressing mode may be defined as the addressing mode in which the address of the memory is specified in the instruction itself. In this addressing mode the instruction consists of a 16 bit memory address or an 8 bit IO address. The 16 bit memory address is always written inside the square brackets. e.g. the instruction MOV BL, [2000H], transfers the content of the memory location 2000H in the BL register. Similarly the instruction MOV [1234H], DL transfers the content of the DL register in the memory location specified by 1234H. Fig. 4.1 shows the direct addressing mode. By default all the direct addressing mode point in the data segment. The segment override prefix is to be used before address if we have to point any other memory segment e.g. to access location 4321H in the extra segment ES the instruction will be of the form BL 2000H MOV AX, ES:[4321H] MOV BL, [2000H] DL 1234H MOV [1234H], DL
  34. 34. 4.2.1 Data Addressing ModesRegister indirect addressing mode: – The instruction specifies aregister containing an address, where data is located. This address is alsoused in concern with memory and IO. In this addressing mode the memoryaddress is specified by some pointer, index or base registers and theseregisters are written inside the square brackets. These are four forms ofaddressing mode on the 8086, best demonstrated by the followinginstructions:MOV DX, [BX]MOV DX, [BP]MOV DX, [SI]MOV DX, [DI]These four addressing modes refer the word at the offset found in the BX,BP, SI or DI registers, The [BX], [SI], [DI] modes use the DS segment bydefault. The [BP] addressing mode uses the stack segment (SS) by default.To access data from other than the default segment, the segment overrideprefix symbols are to be used. The following instructions demonstrate theuse of these overrides:MOV AX, CS:[BX]MOV AX, DS:[BP]MOV AX, SS:[SI]MOV AX, ES:[DI]
  35. 35. 4.2.1 Data Addressing ModesBase addressing mode: - 8-bit or 16-bit displacement instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. In this addressing mode, the memory location is calculated by adding the signed 8 bit or 16 bit displacement to either BX or BP register. Memory location =BX 8 bit displacement +- = BP 16 bit displacement e.g. If BX = 2000H, the instruction is MOV AL, [BX + 15] In this example, the contents of the memory location 200FH (2000H + 0FH (equivalent to decimal 15) is transferred to AL register. The maximum 8 bit displacement can be +-127 and the maximum 16 bit displacement can be +- 32767. These are four possible combinations of the base addressing modes ie. Memory location = BX +- 8 bit displacement = BX +- 16 bit displacement = BP +- 8 bit displacement = BP +- 16 bit displacementThe displacement can also be written asMOV AL, DISP [BX]The addressing modes involving BX, use the data segment, the addressing mode involving [BP] uses the stack segment by default.MOV AL, SS: DISP [BX]MOV AL, ES: DISP [BP]
  36. 36. 4.2.1 Data Addressing ModesIndexed addressing mode: This addressing mode is similar to the base addressing mode with the difference is that this mode is having 8-bit or 16-bit displacement instruction is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. In this addressing mode, the memory location is calculated by adding the signed 8 bit or 16 bit displacement to either SI or DI register.Memory location = SI 8 bit displacement +- = DI 16 bit displacement There are four possible combinations of the base addressing modes i.e. SI +- 8 bit displacement SI +- 16 bit displacement DI +- 8 bit displacement DI +- 16 bit displacementData segment is the default segment for this addressing mode. As with the register indirect and base addressing modes, the segment override prefixes can be used to specify a different segment. MOV AL, CS: DISP [SI] MOV AL, SS: DISP [DI]
  37. 37. 4.2.1 Data Addressing ModesBased Indexed addressing mode:The based indexed addressing modes are simply the combinations of the register indirect addressing modes. Here, the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data residesMemory location = SI BX + DI BPThe following forms for these addressing modes are: MOV AL, [BX] [SI] MOV AL, [BX] [DI] MOV AL, [BP] [SI] MOV AL, [BX] [DI] e.g., If BX = 2000H and SI = 5400H, the instruction is MOV AL, [BX + SI]In this example the contents of the memory location 7400H (2000H + 5400H) is transferred to AL register. The addressing modes that do not involve bp use the data segment by default. Those that have bp as an operand use the stack segment by default. There are four possible combinations of the base addressing modes, i.e.Memory location = SI + BX SI + BX DI + BP DI + BX
  38. 38. 4.2.1 Data Addressing ModesBased Indexed with displacement addressing mode:In this addressing mode, the offset address is generated by the sum of Base register and Index registers along with 8-bit or 16-bit displacement instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.Memory location = SI BX 8 bit displacement + +- DI BP 16 bit displacementIn this addressing mode the memory location is calculated by adding the signed 8 bit or 16 bit displacement to the sum of the content of SI + BIP or SI + BX or DI + BP or DI + BXConsidering the same example i.e. if BX = 2000H and SI = 5400H, the instruction isMOV AL, [BX + SI + 15]
  39. 39. 4.2.1 Data Addressing ModesIn this example, the contents of the memory location 740FH (2000H + 5400H +0FH i.e. equiv. to decimal 15) is transferred to AL register. Again the maximum 8-bit displacement can be +- 127 and the maximum 16 bit displacement can be +- 32767. There are eight possible combinations of the base index with displacement addressing mode i.e.SI +BP +- 8 bit displacementSI + BX +- 8 bit displacementDI + BP +- bit displacementMemory location = DI + BX +- 8 bit displacementSI + BP +- 16 bit displacementSI + BX +- 16 bit displacementDI + BP +- 16 bit displacementDI + BX +- 16 bit displacementFollowing are some of the examples of these addressing modes:MOV AL, DISP [BX] [SI]MOV AL DISP [BX + DI]MOV AL [BP + SI + DISP]MOV AL, [BP] [DI] [DISP]
  40. 40. 4.2.1 Data Addressing ModesString addressing modes:This mode uses index registers. The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand.The segment register for the source is DS and may be overridden. The segment register for the destination must be ES and cannot be overridden. The contest of SI and DI are automatically incremented by clearing DF (Direction Flag) to 0 by CLD instruction or automatically decremented by setting DF to 1 by STD instruction. Table 4.1. summarizes all the 32 possible data addressing modes of 8086(BX) + (SI) (BX) + (SI) + d8 (BX) + (SI) + d16 AL AX(BX) + (DI) (BX) + (DI) + d8 (BX) + (DI) + d16 CL CX(BP) + (SI) (BP) + (SI) + d8 (BP) + (SI) + d16 DL DX(BP) + (DI) (BP) + (DI) + d8 (BP) + (DI) + d 16 BL BX (SI) (SI) + d8 (SI) + d16 AH SP (DI) (DI) + d8 (DI) + d16 CH BP d16 (BP) +d8 (BP) +d16 AH SP (BX) (BX) +d8 (BX) +d16 BH DI
  41. 41. 4.3 Instruction FormatThe instructions of 8086 may be one to six byte long. These instructions have different formats and following figure shows some of the instruction formats. OPCODE OPCODE REG OPCODE REG MOD REG R/M OPCODE REG MOD REG R/M Lower Disp Higher Disp OPCODE REG MOD REG R/M Lower Disp Higher Disp Lower Data Higher data opcode (operation code) is the portion of a machine language instruction that specifies the operation to be performed. Their specification and format are laid out in the instruction set architecture of the processor. In assembly langage mnemonic form an opcode is command e.g. MOV, AL, 34h here the opcode is MOV instruction and other parts are operands. The first byte always consist of the opcode. The opcode may be of 8 bit or occupy MSB six bits (most significant bit) of the first bytes and it defined the operation to be carried out by the instruction and the remaining two bits are any of the following bits1. Direction bit (D) defines whether the register operand in byte 2 is the source or destination operand. D = 1 specifies that the register operand is the destination operand D = 0 indicates that the register is a source operand2. Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data W = 0 indicate 8 bit operation and W = 1 indicates 16 bit operation3. Sign bit (S) is used for sign extension of an 8 bit 2s compliment number to a 16 bit 2s compliment number. This is done by making all the bits in high order byte same as that of MSB in the lower order byte. This bit appears with the W bit in add, subtract and compare instructions. For 8 bit operation S:W bits are 00 and these bits are 01 for 16 bits operation with 16 bit immediate operand. S:W bits are 11 for 16 bit operation with a sign extended 8 bit immediate operand
  42. 42. 4.3 Instruction Format4. V bit is used in shift and roate instruction to determine the number of shifts V = 0 indicates that the shift count is 1 , V=1 indicate the CL register contains the shift count5. The Z bit is used in REP instruction. The Z bit is matched with the zero flag bit. The REP instruction goes on executing till the Z bit does not match with the zero flag. A summary of these bits encoding is shown in Table 4.2. below Field Value Function S 0 No sign extension 1 Sign extend 8 bit immediate data to 16 bits if W = 1 W 0 Instruction operates on byte data 1 Instruction operate on word data D 0 Instruction source is specified in REG field 1 Instruction destination is specified in REG field V 0 Shift/rotate count is one 1 Shift/rotate count is specified in CL register Z 0 Repeat/loop while zero flag is clear 1 Repeat/loop while zero flag is set As shown in the previous figure, depending on the instruction, the opcode byte may be the only byte in the instruction or may be followed by- One or two byte long immediate data- One or two byte long displacement- One or two byte long displacement and then ne or two byte long immediate data- Two byte long direct address- Two byte long displacement and then two byte long segment address
  43. 43. 4.5 Instruction set for 8086 microprocessors The instruction set of 8086 microprocessor can be broadly classified into eight group depending on the function these instruction perform1 Data Transfer Instruction : Use for transferring data from source location to destination2 Arithmetic Instruction : Use to perform arithmetic operations e.g addition subtraction ,multiplication and division3 Logical Instruction : Use to perform logical operation e.g CMP, AND,NOT, OR,EX-OR, operation4 Shift and rotate operation / Instructions: Use to perform the logical and arithmetic shift operations and left and right shifting5 String Instructions: Use to perform string related operations6 Data Adjust Instructions: Use to convert the binary data in ASCII or in BCD format7 The control Transfer Instructions: Use to transfer the control within the program or from main program to subroutine program or from subroutine program to main program8 Machine control instructions are used to perform the machine control operation like halt etc.
  44. 44. 4.5 Instruction set for 8086 microprocessors 4.5.1 Data Transfer Instructions MOV 4.5.2 Arithmetic Instructions ADD, SUB, MUL, DIV, INC, DEC, NEG 4.5.3 Logical Instructions CMP, AND, OR, NOT, XOR Let us now going to investigate these instructions in details.
  45. 45. 4.5 Instruction set for 8086 microprocessors 4.5.1 Data Transfer Instructions MOV destination, source The MOV instructions copies the second operand (source) to the first operand (destination) without modifying the contents of the source and pls. remembers this is not data transfer/move but data copy instructions. Here, the source operand can be general purpose register or memory locations and the destination register can be a general purpose register or memory location. Both operands must be of the same size which may be byte or word. Following type operands are supported MOV REG, Memory MOV Memory, REG MOV REG, REG MOV Memory, immediate MOV REG, Immediate Gen. purpose register AX, BX, CX, DX, AH, AL etc. and the memory may be specified by any othe memory related addressing mode.
  46. 46. 4.5 Instruction set for 8086 microprocessors 4.5.1 Data Transfer Instructions MOV destination, source For Segment registers only these type of MOV are supported MOV SREG Memory MOV Memory SREG MOV REG REG MOV SREG REG Pls. note that data can’t be transferred from one memory to another memory, from memory to an IO, from one IO to another IO and from IO to memory. IO can communicate with Accumulator only. The MOV instructions cannot set the value of CS and IP register, also it cannot copy value of one segment register to another segment register. e.g If we want to initiative the Data segment by memory location 02500H, then first we have to load, the values 2500H in AX register and then transferring the contents of AX to DS register with the help of the following instruction MOV AX, 2500H MOV DS, AX In MOV instructions the flag remain unchanged.
  47. 47. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions ADD, SUB, MUL, DIV, NEG, INC, DEC Microprocessor 8086 may perform the arithmetic operation on four types of data ie. Signed binary, Unsigned binary, Unsigned packed BCD (same number would fit into a single byte) and Unsigned Unpacked BCD. The binary no. of 8 bit/16 bit and the BCD number are always unsigned. ADD Add Operands REG, Memory Memory, REG REG, REG Memory, Immediate REG, Immediate These instructions add a data from the source operand to a data from the destination and save the result in the destination operand provided source and destination of the same size, same type i.e. byte/word. But pls. note that the Segment register can’t be use as an operand in ADD instruction. Memory to memory and IO to memory addition is also not allowed.
  48. 48. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions e.g. add instructions can be used to perform the operation F = X+Y+Z MOV AX, X ADD AX, Y ADD AX, Z MOV F, AX Flag bit are modified as per the result of the operations.
  49. 49. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions SUB Subtract Operands REG, Memory Memory, REG REG, REG Memory, Immediate REG, Immediate This instructions subtract the source operand from the destination operand store the result in the destination operand. Pls. note that the Segment register can’t be use as an operand. Memory to memory and IO to memory addition is also not allowed. Flag bits are modified as per the result of the operation e.g MOV AL, 05H SUB AL, 02H After the execution of the Sub instruction AL will contain 03H
  50. 50. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions MUL Multiplication Operands REG Memory This instructions multiply the contents of the AL or the AX by a specified source operand. The AL and AX are the destination operands for 8 bit and 16 bit multiplication, again both the implied operand and the source operand must be of the same size. For a 16 bit multiplication, the implied operand will be AX register. After the multiplication the product, ie. 32 bits, will be stored into the DX: AX register pair. AX AX x x 16 bit operand 8 bit operand DX AX AH AL e.g. MOV AL, 0FDH MOV CL, 05H MUL CL; AX = 04F1H CF =0F=0 when high section of the result is zero.
  51. 51. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions MUL Multiplication Operands REG Memory For an 8 bit multiplication, the implied operand will be the AL register. After the multiplication the product, which is of 16 bits, will be stored into the AX register. If after the multiplication the product, which is of 16 bits, will be stored into the AX register. If after the multiplication DX is not 0 for 16 bit operands or AH is not zero for 8 bit operands, then the carry and overflow flags will set. The A, P, S and Z flags are undefined, i.e. the value of these flag bits may be either 0 or 1. See the previous slide….
  52. 52. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions DIV division Operands REG Memory This instruction divides the contents of the AX or the DX: AX by a specified source operand. The AX and the DX:AX is the implied destination operands for 16 bit and 32 bit division. This is an unsigned operation and hence both operands are treated as unsigned operands. If the divisor is 16 bits wide, then the dividend is the DX: AX register pair. After the division the quotient will be stored into AX and the remainder into DX. When the divisor is of 8 bits the dividend is AX. And in this case the quotient will be stored in AL and the remainder in AH. Following Fig. shows the representation of DIV. All the flag bits are undefined ie. The value of all the flag bits may be either 0 or 1 AX DX AX ÷ ÷ 8 bit operand 16 bit operand AH AL DX AX Remainder Quotient Remainder Quotient e.G MOV AX, 00C8H MOV CL, 06H DIV CL After this program the result is available in AL (=21H) and the remainder is present in AH (=02H)
  53. 53. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions NEG Negate Operands REG Memory This instruction produces the two’s compliment of the specified operand and stored the result in the same operand. Microprocessor performs the negate (NEG) operation by subtracting the operand from 0. This is done to represent a negative number. All the flag bits are modified as per the result. The carry flag will be set for a non-zero operand and for a zero operand it will be reseted. If the operand contains the maximum possible negative value (-128 for 8 it operands or -32768 for 16 bit operands), the value does not change, but the overflow and carry flags are set. e.g MOV AL, 15H NEG AL; AL = 0EBH (2’s complement of 15 H)
  54. 54. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions INC Increment Operands REG Memory Increment the operand by 1. This instruction increment the destination operand by 1. This instruction differs with the ADD by 1 instruction in the way that the INC instruction does not affect the carry flag whereas the ADD instruction modifies the carry flag. The INC instruction is more compact and often faster than the comparable ADD instruction because it is a one byte instruction. In INC all flags, except the carry flag, changes as that of in ADD instructions
  55. 55. 4.5 Instruction set for 8086 microprocessors 4.5.2 Arithmetic Instructions DEC Increment Operands REG Memory Decrement the operand by 1. This instruction decrement the destination operand by 1. This instruction differs with the SUB by 1 instruction in the way that the DEC instruction does not affect the carry flag whereas the SUB instruction modifies the carry flag. The DEC instruction is more compact and often faster than the comparable ADD instruction because it is a one byte instruction. In DEC except the carry flags, all other flag changes as that of in SUB instructions
  56. 56. 4.5 Instruction set for 8086 microprocessors 4.5.3 Logical Instructions CMP, AND, NOT, OR, XOR The 8086 provides six logical instructions but above five(5) are in your course. These instruction can manipulate bits, convert values, do logical operations. CMP Compare Operands REG, memory memory, REG REG, REG memory, immediate REG, immediate This instruction compare the source operand with the destination operand. Microprocessor executes this CMP instruction by subtracting the source operand from the destination operand but none of the operands are modified. The result is reflected by the flag bits. Generally, the result (i.e. flag conditions) of this instruction is used for conditional control transfer instructions. The comparison may be a signed comparison or an unsigned comparison. For unsigned comparison, the result is reflected by the Carry and Zero flag bits whereas for signed comparison the result is reflected by the Zero, Sign and the Overflow flag.
  57. 57. 4.5 Instruction set for 8086 microprocessors 4.5.3 Logical Instructions For unsigned comparison operation, consider instruction CMP AX, BX , the microprocessor perform the AX-BX operation. Now if AX = BX, then the result will be zero and hence the zero flag will set. If AX is greater than BX, the result will be non-zero and positive and hence both the Zero and Carry are reset. Similarly, when BX is greater than AX, then to perform AX-BX we require to take borrow and hence the Zero flag is reset and the carry is set. For signed comparison if the EX-OR operation of the Sign and Overflow flag is 1, then the result is negative. It is to be noted that for signed comparisons, the sign flag doesnt show the proper status. e.g. Flag condition Result Sign flag Overflow flag 0 1 AX < BX 1 0 AX < BX 0 0 AX > BX 1 1 AX > BX The CMP instruction also affects the parity and auxiliary carry flags, but these two flag are rarely tested after a compare operation.
  58. 58. 4.5 Instruction set for 8086 microprocessors 4.5.3 Logical Instructions NOT Logically NOT Operands REG memory This instruction complements the individual bits of the operand and save the result in the same operand. We can say that it generates the 1’s complement or the NOT operation of the operand. After this instruction the flag register remain unmodified. MOV AL, 39H NOT AL; AL = C6H
  59. 59. 4.5 Instruction set for 8086 microprocessors 4.5.3 Logical Instructions OR Logically OR Operands REG, memory memory, REG REG, REG memory, immediate REG, immediate This instruction performs a bitwise logical OR operation between the source and destination operands. The result is stored in the destination operand. After the operation, the Z, S and P flag bits are modified whereas the carry and overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1).
  60. 60. 4.5 Instruction set for 8086 microprocessors 4.5.3 Logical Instructions XOR Logically EX-OR Operands REG, memory memory, REG REG, REG memory, immediate REG, immediate This instruction performs a bitwise logical exclusive OR operation between the source and destination operands. After the operation, the result is stored in the destination. The Z, S, and P bits of the flag register are modified as per the result whereas the carry and overflow flag bits are set to 0 and auxiliary carry is undefined (i.e. may be 0 or 1).
  61. 61. 4.5 Instruction set for 8086 microprocessors 4.5.3 Logical Instructions AND Logically AND Operands REG, memory memory, REG REG, REG memory, immediate REG, immediate This instruction performs a bitwise Logical AND of destination operand and the source operand. The result of the operation is stored in the destination operand. The AND operation is performed as per following table. The Z,S, and P flag bits are modified as per the result. The carry and overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1) AND OR EXCLUSIVE OR NOT A B A.B A B A-B A B A(-)B A /A 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 0 1 0 0 1 0 1 1 0 1 - - 1 1 1 1 1 1 1 1 0 - - e.g. MOV AL, 61H; AL = 01100001 AND AL, CFH; AL = 01000001

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