Intro to Micr0wind Sofware

227 views
145 views

Published on

VLSI

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
227
On SlideShare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
Downloads
8
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Intro to Micr0wind Sofware

  1. 1. Class No 03 & 09Lab No. 08 Introduction To Micro wind Software Or Introduction To Layout & FabricationAim:  Fabrication of nmos & pmos transistors.  Making 2 or 3 transistor (nmos or pmos) of different sizes & then define different rise/fall time and high/low for each of the transistor and analyze the transistor characteristics.  By considering high/low time limit the frequency.Software Background:The software includes the following portions:Main Menu: In Main menu we have From file menu we can select new file, insert layout, save as, colors etc From view menu we can select refresh, select all, zoom in , zoom out etc From view menu we can select copy, paste, protect all, unprotect all etc. From simulate menu we can select run simulation, simulation parameters etc From compile menu we can select compile one line, compile verilog file. From analysis menu we can select design rule checker, parametric analysis etc In help we can get help about rules, micro wind etc. File View Edit Simulate 1Micro-Electronics Technologies
  2. 2. Class No 03 & 09Icon Menu:In icon menu we have number of useful operations:Open file , Save , Draw Box , Delete , Copy , Paste , Zoom in , Zoomout , 2D view , 3D view etcLayout Window:Use to create layouts:Palette Bar:We have number of components for making the layouts:Metal Layers.Diffusion Layers.Polysilicon Layers.Connectors.Clock Signals.Vdd. 2Micro-Electronics Technologies
  3. 3. Class No 03 & 09Cmos Technology:In cmos technology the combination of P-mosfets & N-mosfets is used for the better results. Asit is understood that n-mosfets completely transmits logic 0 but partially logic 1 while p-mosfetscompletely transmits logic 1 but transmit logic 0 with error. So to overcome this problem p & nmosfets are used in combination called Complementary Mosfets (cmos)There are certain advantages of cmos technology. o High noise immunity property is possessed by cmos. o CMOS has relatively less number of transistors where as TTL has a number of transistors and a number of resistors to perform the same function. Therefore CMOS has low static power consumption. o Due to less number of components CMOS devices are also cheaper & affordable. o It enables chips that are small in size to have features like high operating speeds and efficient usage of energy.Apparatus:  Microwindv2-7 installed PC.Procedure:  First of all open the software by clicking on-to the icon .  For the specific gate select the required components by clicking the icon palette .  Microwind software includes a comprehensive library, from this library (palette), from palette we can select Metal Layers, Diffusion Layers, Polysilicon Layers, Connectors, Clock Signals, Vdd for making the device layouts.  Draw different layers by selecting the layer & then drawing by click & drag.  We can also see the 2D look & 3D look of the layout by clicking the required icon from icon menu.  The components attributes can be changed by double clicking on-to the component there by changing the required field.  After completing the circuit diagram simulate the circuit by clicking & the figures window will appear. 3Micro-Electronics Technologies
  4. 4. Class No 03 & 09Gate 1: nmosComponents:  Polysilicon layer for gate. o Gate Length = 2.100 um Gate Width = 0.300 um  Layer for nmos o N Layer Length = 1.500 um N+ Layer Width = 1.500 um +  Metal 1 for connections.  Connectors to connect N+ & metal 1  Clock Signal as gate signal & as input at source. o Clock Parameters For Gate:  Rise Time: 0.025 ns  Fall Time: 0.025 ns  Time Low: 0.225 ns  Time High: 0.225 ns o Clock Parameters For Input:  Rise Time: 0.025 ns  Fall Time: 0.025 ns  Time Low: 0.475ns  Time High: 0.475nsLayout Diagram: 4Micro-Electronics Technologies
  5. 5. Class No 03 & 09Analog Simulation Window: Fig (a): For gate1 (nmos) Simulation windowConclusion from the Figure (a):  As nmos is strong logic zero transmitters that is why in figure the zero is transmiting to output accurately but 1 is not transmitting accurately & providing some undetermined state.  As the gate on/off time is 0.225 ns so frequency will be .  So for this transistor the signal at source must have frequency less than or equal to . o Input frequency to transistor must be ≤ .  Any input to this transistor with frequency higher than this range will make the output faulty and cannot transfer to output exactly.Gate 2: nmosComponents:  Polysilicon layer for gate. o Gate Length = 2.940 um Gate Width = 0.300 um  Layer for nmos o N Layer Length = 2.400 um N+ Layer Width = 1.500 um +  Metal 1 for connections.  Connectors to connect N+ & metal 1 5Micro-Electronics Technologies
  6. 6. Class No 03 & 09  Clock Signal as gate signal & as input at source. o Clock Parameters For Gate:  Rise Time: 0.035 ns  Fall Time: 0.035 ns  Time Low: 0.442ns  Time High: 0.442ns o Clock Parameters For Input:  Rise Time: 0.025 ns  Fall Time: 0.025 ns  Time Low: 0.50ns  Time High: 0.50nsLayout Diagram: 6Micro-Electronics Technologies
  7. 7. Class No 03 & 09Analog Simulation Window: Fig (b): For gate2 (nmos) Simulation windowConclusion from the Figure (b):  Again nmos is strong logic zero transmitters that is why in figure the zero is transmitting to output accurately but 1 is not transmitting accurately & providing some undetermined state.  As the gate on/off time is 0.442 ns so frequency will be .  So for this transistor the signal at source must have frequency less than or equal to . o Input frequency to transistor must be ≤ .  Any input to this transistor with frequency higher than this range will make the output faulty and cannot transfer to output exactly.Gate 3: pmosComponents:  Polysilicon layer for gate. o Gate Length = 1.80 um Gate Width = 0.300 um  Layer for pmos o P Layer Length = 1.200 um P+ Layer Width = 0.900 um +  Metal 1 for connections.  Connectors to connect P+ & metal 1 7Micro-Electronics Technologies
  8. 8. Class No 03 & 09  Clock Signal as gate signal & as input at source. o Clock Parameters For Gate:  Rise Time: 0.225ns  Fall Time: 0.225ns  Time Low: 0.225ns  Time High: 0.225ns o Clock Parameters For Input:  Rise Time: 0.025 ns  Fall Time: 0.025 ns  Time Low 0.375ns  Time High: 0.375nsLayout Diagram: 8Micro-Electronics Technologies
  9. 9. Class No 03 & 09Analog Simulation Window: Fig (c): For gate3 (pmos) Simulation windowConclusion from the Figure ©:  As pmos is strong logic one transmitters that is why in figure the one(i-e 0.5 in this case) is transmitting to output accurately but 0 is not transmitting accurately & providing some undetermined state.  As the gate on/off time is 0.225 ns so frequency will be .  So for this transistor the signal at source must have frequency less than or equal to . o Input frequency to transistor must be ≤ .  Any input to this transistor with frequency higher than this range will make the output faulty and cannot transfer to output exactly. 9Micro-Electronics Technologies

×