Analog Approaches in Digital Receivers محمدرضا ذهابی هفته پژوهش و فناوری 18 آذر 1387

Target of the work Why Analog Realization? Set of Equations Circuit topology 

Target of the work General Communication System Channel Encoder Demodulation Digital Source Modulation Channel Filtering Decoder

Outline Introduction Coding Convolutional Codes Codes on Graphs Analog Implementation Simulation Results Decoding on Analog Graph

Introduction

Coding

Convolutional Codes

Codes on Graphs

Analog Implementation

Simulation Results

Introduction Maximum Likelihood Decoding Invalid Codeword Valid Codeword Observation k : information length Decoding Algorithm ~ k Exhaustive search 2 k comparisons Ĉ = argmin || Y - C ||² c Ĉ = argmax P( Y | C ) c ML Principle

Introduction Encoding and Decoding of CC. y n 2 u n y n 1 u n y n 2 y n 1 Recursive Systematic Encoder Feed Forward Encoder n -1 n n +1 n +2 Trellis of the code 2 m states Decoding Encoding

Outline Introduction Codes on Graphs Principles of Graph Log-Likelihood Ratio (LLR) Operations on LLRs convolutional code example Analog Implementation Simulation Results Decoding on Analog Graph

Introduction

Codes on Graphs

Principles of Graph

Log-Likelihood Ratio (LLR)

Operations on LLRs

convolutional code example

Analog Implementation

Simulation Results

b 1 Principles of Graph b o 1 o 2 Two obs. for a bit b 2 xor Decoding formulas b o 1 o 2 P  b  o   P  b   o   Codes on Graphs

Log-Likelihood Ratio ( LLR ) Codes on Graphs P  b  o  P  b  o  L  b  o  ln P  b  o    exp   L  b  o   P  b  o  exp   L  b  o    exp   L  b  o  

Operations on LLRs Codes on Graphs L  b  o 1 o 2  L  b  o 1  L  b  o 2  tanh  L  b  o 1 o 2  2  tanh  L  b 1  o 1  2  tanh  L  b 2  o 2  2  b o 1 o 2 b 1 b 2 xor b o 1 o 2

Messages in graphs Check node Codes on Graphs Symbol node L  b  o 1 o 2  L  b  o 1  L  b  o 2  tanh  L  b  o 1 o 2  2  tanh  L  b 1  o 1  2  tanh  L  b 2  o 2  2 

(7,5) convolutional code example y n u n Codes on Graphs I N  G D  I N G N U Y  X

Outline Introduction Codes on Graphs Analog Implementation Probability to LLR LLR to Probability Generic Variable Node Generic Function Node Schematic Diagram of Decoder Simulation Results Decoding on Analog Graph

Introduction

Codes on Graphs

Analog Implementation

Probability to LLR

LLR to Probability

Generic Variable Node

Generic Function Node

Schematic Diagram of Decoder

Simulation Results

Analog Implementation Probability to LLR P  b  o  P  b  o  L  b  o  ln v o  L  b  o  V T i 1  P  b  o  i 1  i 2 i 2  P  b  o  i 1  i 2 v o i 1  ln V T i 2

Analog Implementation LLR to Probability v o  L  b  o  V T i 1  P  b  o  i 1  i 2 i 2  P  b  o  i 1  i 2 i 1  i 1  i 2   exp   v/V T  i 2  i 1  i 2 exp   v/V T   exp   v/V T  P  b  o    exp   L  b  o   P  b  o  exp   L  b  o    exp   L  b  o  

Analog Implementation Generic Symbol node Tail current L  b  o 1 o 2  L  b  o 1  L  b  o 2  v z =v x  v y

Analog Implementation Generic check node Tail current tanh  L  b  o 1 o 2  2  tanh  L  b 1  o 1  2  tanh  L  b 2  o 2  2  tanh  v z  2  tanh  v x  2  tanh  v y  2 

Analog Implementation (7,5) RSC schematic diagram

Outline Introduction Codes on Graphs Analog Implementation Simulation Results Overview and setting up Time Response Speed and Performance versus a design parameter Overall Performance (BER) Decoding on Analog Graph

Introduction

Codes on Graphs

Analog Implementation

Simulation Results

Overview and setting up

Time Response

Speed and Performance versus a design parameter

Overall Performance (BER)

Overview and setting up Simulation Results Decoder 16 8 8 Channel output Decoded bits CMOS model : AMS0.35µm (Sub-threshold) Power supply : 5 V Power Consumption : 0.3 mW Decoder : (7,5) oct RSC or non-RSC Codes Codeword Length : 16 Code Rate : 0.5

Time response Simulation Results

Effect of tail current Simulation Results 10 nA 100 nA 1000 nA Time (µS) BER

Tail current: 10 nA Simulation Results Bit-Error-Rate and benchmark

Conclusions and Perspective Decoding on Analog Graph No need for input ADC No clock input Parallel structure Soft input (gain +3dB gain) Soft and hard outputs Very small transistor count

No need for input ADC

No clock input

Parallel structure

Soft input (gain +3dB gain)

Soft and hard outputs

Very small transistor count

Conclusions and Perspective Using current to represent the LLR may reduce the complexity of the summation blocks used in variable nodes. Designing competitive analog topologies for realization of graph’s nodes that cope with low consumption requirements. Finding other applications suitable for analog implementation. For example the issue of synchronization in MIMO receivers is under investigation. Systematic modeling of analog decoders that incorporates transient, mismatching and other secondary effects. Extending the idea to non-binary cases such as joint channel equalization and decoding problem. Decoding on Analog Graph

Using current to represent the LLR may reduce the complexity of the summation blocks used in variable nodes.

Designing competitive analog topologies for realization of graph’s nodes that cope with low consumption requirements.

Finding other applications suitable for analog implementation. For example the issue of synchronization in MIMO receivers is under investigation.

Systematic modeling of analog decoders that incorporates transient, mismatching and other secondary effects.

Extending the idea to non-binary cases such as joint channel equalization and decoding problem.

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