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CENG04:  Microprocessor Systems Midterm Lecture 2 & 3
Introduction Intel µP Instruction Encoding and Decoding <ul><li>Machine Language </li></ul><ul><ul><li>It is the native bi...
<ul><li>Figure 1  – The format of the 8086 – 80486 Instruction a) 16-bit instruction, b) 32-bit instruction  </li></ul>808...
<ul><li>Figure 2  – 8088/8086 Instruction Format </li></ul>8088/8086 Instruction Format Intel µP Instruction Encoding and ...
<ul><li>Instructions  consist of:  </li></ul><ul><ul><li>operation (opcode) e.g. MOV  </li></ul></ul><ul><ul><li>operands ...
<ul><li>Encoding  of instruction must includes: </li></ul><ul><ul><li>Opcode </li></ul></ul><ul><ul><li>Operands </li></ul...
<ul><li>Override Prefixes </li></ul><ul><ul><li>It is the first 2 bytes of a 32-bit instruction format </li></ul></ul><ul>...
<ul><ul><ul><li>Operand Size  -  modifies the size of the register. </li></ul></ul></ul><ul><ul><ul><ul><li>If the 80386/8...
<ul><li>First byte:  Opcode, Direction, & Word bits </li></ul><ul><ul><li>Opcode  – select the operation performed by the ...
<ul><li>Second Byte:  Mode, Register, & Register/Memory </li></ul><ul><ul><li>Mode  field </li></ul></ul><ul><ul><ul><li>T...
<ul><li>Figure 3  – Table for MOD field a) 16-bit, b) 32-bit </li></ul>Instruction Encoding Intel µP Instruction Encoding ...
<ul><li>Figure 4  – REG field for w=0 & w=1 </li></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
<ul><li>Figure 5  – 16- and 32-bit R/M field, segment register field, and scaled factor. </li></ul>How to Encode Instructi...
<ul><li>Register Addressing </li></ul><ul><ul><li>It uses the R/M field to specify a register instead of memory location <...
<ul><li>Determine the equivalent machine code of the following assembly code: </li></ul><ul><ul><li>MOV DX, AX </li></ul><...
<ul><li>Given the following machine code (hex code), determine the equivalent assembly instruction for each. </li></ul><ul...
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Intel µp instruction encoding and decoding

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Intel uP Instruction decoding and encoding

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  • Transcript of "Intel µp instruction encoding and decoding"

    1. 1. CENG04: Microprocessor Systems Midterm Lecture 2 & 3
    2. 2. Introduction Intel µP Instruction Encoding and Decoding <ul><li>Machine Language </li></ul><ul><ul><li>It is the native binary code that the microprocessor understand. </li></ul></ul><ul><li>Assembler </li></ul><ul><ul><li>It is use to translate assembly instruction to a machine code. </li></ul></ul><ul><li>Opcode (Operation Code) </li></ul><ul><ul><li>Selects the operation performed by the microprocessor such as MOV, ADD, INC, JMP, & etc. </li></ul></ul><ul><ul><li>It is either one or two byte in length for most machine language instruction. </li></ul></ul><ul><li>Encoding </li></ul><ul><ul><li>It is a processes representing entire assembly instruction as a binary value or hexadecimal format (human perspective) </li></ul></ul><ul><li>Decoding </li></ul><ul><ul><li>It is the process of converting hexadecimal format to assembly language (machine perspective) </li></ul></ul>
    3. 3. <ul><li>Figure 1 – The format of the 8086 – 80486 Instruction a) 16-bit instruction, b) 32-bit instruction </li></ul>8086 – 80486 Instruction Format Intel µP Instruction Encoding and Decoding
    4. 4. <ul><li>Figure 2 – 8088/8086 Instruction Format </li></ul>8088/8086 Instruction Format Intel µP Instruction Encoding and Decoding
    5. 5. <ul><li>Instructions consist of: </li></ul><ul><ul><li>operation (opcode) e.g. MOV </li></ul></ul><ul><ul><li>operands (number depends on operation) </li></ul></ul><ul><li>Operands specified using addressing modes </li></ul><ul><li>Addressing mode may include addressing information </li></ul><ul><ul><li>Registers </li></ul></ul><ul><ul><li>Constant values </li></ul></ul><ul><ul><li>Variable </li></ul></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    6. 6. <ul><li>Encoding of instruction must includes: </li></ul><ul><ul><li>Opcode </li></ul></ul><ul><ul><li>Operands </li></ul></ul><ul><ul><li>Addressing information </li></ul></ul><ul><li>Encoding is process representing entire instruction as a binary value </li></ul><ul><ul><li>Number of bytes needed depends on how much information must be encoded . </li></ul></ul><ul><li>Instructions are encoded by assembler: </li></ul><ul><ul><li>.OBJ file (link, then loaded by loader) </li></ul></ul><ul><li>Instructions are decoded by processor during execution cycle </li></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    7. 7. <ul><li>Override Prefixes </li></ul><ul><ul><li>It is the first 2 bytes of a 32-bit instruction format </li></ul></ul><ul><ul><li>These bytes are not always used </li></ul></ul><ul><ul><li>Divided in Two Parts: </li></ul></ul><ul><ul><ul><li>Address Size – modifies the size of the address used the instruction and this byte is equal to 67h if in used. </li></ul></ul></ul><ul><ul><ul><ul><li>If the 80386/80486 is operating as 16-bit instruction mode machine (real or protected mode) and 32-bit instruction, byte is equal to 67h </li></ul></ul></ul></ul><ul><ul><ul><ul><li>If the 80386/80486 is operating as 32-bit instruction mode machine (real or protected mode) and 32-bit instruction, byte is removed. </li></ul></ul></ul></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    8. 8. <ul><ul><ul><li>Operand Size - modifies the size of the register. </li></ul></ul></ul><ul><ul><ul><ul><li>If the 80386/80486 is operating as 16-bit instruction mode machine (real or protected mode) and 32-bit instruction, byte is equal to 66h </li></ul></ul></ul></ul><ul><ul><ul><ul><li>If the 80386/80486 is operating as 32-bit instruction mode machine (real or protected mode) and 32-bit instruction, byte is removed. </li></ul></ul></ul></ul><ul><ul><li>These toggle the size of the register and operand address from 16-bit to 32-bit or vice versa. </li></ul></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    9. 9. <ul><li>First byte: Opcode, Direction, & Word bits </li></ul><ul><ul><li>Opcode – select the operation performed by the microprocessor (use the lists of opcodes) </li></ul></ul><ul><ul><li>Direction (D) – indicates the flow of data </li></ul></ul><ul><ul><ul><li>D = 1, data flow from (R/M) field to REG field </li></ul></ul></ul><ul><ul><ul><li>D = 0, if data flow from REG field to R/M field. </li></ul></ul></ul><ul><ul><li>Word (W) – determine the size of data or register </li></ul></ul><ul><ul><ul><li>W = 1, 16- or 32-bit data width (word or dword) </li></ul></ul></ul><ul><ul><ul><li>W = 0, 8-bit data width (byte) </li></ul></ul></ul><ul><li>Note: W bit appear in most of the instruction but D bit mainly appears with MOV and some other instructions. </li></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    10. 10. <ul><li>Second Byte: Mode, Register, & Register/Memory </li></ul><ul><ul><li>Mode field </li></ul></ul><ul><ul><ul><li>This field specifies the addressing modes for selected instruction. </li></ul></ul></ul><ul><ul><ul><li>This selects the type of addressing and whether a displacement is present or with the selected instruction. </li></ul></ul></ul><ul><ul><ul><ul><li>MOD = 11, selects data addressing modes </li></ul></ul></ul></ul><ul><ul><ul><ul><li>MOD = 00, 01, or 10, selects memory addressing modes </li></ul></ul></ul></ul><ul><ul><li>REG field </li></ul></ul><ul><ul><ul><li>Field for register assignment </li></ul></ul></ul><ul><ul><li>R/M (Register or Memory) </li></ul></ul><ul><ul><ul><li>Field for register act as a memory or memory location assignment. </li></ul></ul></ul>How to Encode Instructions as Binary Values? Intel µP Instruction Encoding and Decoding
    11. 11. <ul><li>Figure 3 – Table for MOD field a) 16-bit, b) 32-bit </li></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    12. 12. <ul><li>Figure 4 – REG field for w=0 & w=1 </li></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    13. 13. <ul><li>Figure 5 – 16- and 32-bit R/M field, segment register field, and scaled factor. </li></ul>How to Encode Instructions as Binary Values? Intel µP Instruction Encoding and Decoding
    14. 14. <ul><li>Register Addressing </li></ul><ul><ul><li>It uses the R/M field to specify a register instead of memory location </li></ul></ul><ul><li>Special addressing modes </li></ul><ul><ul><li>This addressing modes occurs whenever memory data are referenced by only the displacement mode of addressing for 16-bit instructions. </li></ul></ul><ul><ul><ul><li>MOV [1000h], DL </li></ul></ul></ul><ul><ul><ul><li>MOV NUMB, DL </li></ul></ul></ul><ul><ul><li>MOD = 00 and R/M =110 </li></ul></ul><ul><ul><li>Scaled-Index Byte </li></ul></ul><ul><ul><ul><li>Indicates the additional forms of scaled-index addressing. </li></ul></ul></ul><ul><ul><ul><li>Occurs when R/M = 100 </li></ul></ul></ul>Instruction Encoding Intel µP Instruction Encoding and Decoding
    15. 15. <ul><li>Determine the equivalent machine code of the following assembly code: </li></ul><ul><ul><li>MOV DX, AX </li></ul></ul><ul><ul><li>MOV DX, [BX + DI + 1234h] </li></ul></ul><ul><ul><li>ADD AX, 1023 </li></ul></ul><ul><ul><li>SUB DX, 1234h </li></ul></ul><ul><ul><li>AND [BX + 12h], AX </li></ul></ul><ul><ul><li>MOV EAX, [EBX + 4*ECX] </li></ul></ul><ul><ul><li>MOV [5267h], DH </li></ul></ul><ul><ul><li>MOV CS, AX </li></ul></ul><ul><ul><li>MOV DS, AX </li></ul></ul><ul><ul><li>MOV AX, [BX] </li></ul></ul>Examples (Encoding) Intel µP Instruction Encoding and Decoding
    16. 16. <ul><li>Given the following machine code (hex code), determine the equivalent assembly instruction for each. </li></ul><ul><ul><li>8B923412h </li></ul></ul><ul><ul><li>81C17856h </li></ul></ul><ul><ul><li>2C26h </li></ul></ul><ul><ul><li>8B163412h </li></ul></ul><ul><ul><li>20D8h </li></ul></ul>Examples (Decoding) Intel µP Instruction Encoding and Decoding
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