UNIT-I DIGITAL SYSTEM DESIGN
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UNIT-I DIGITAL SYSTEM DESIGN

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This class notes is meant for First semester M.Tech VLSI Students of SKUCET ,Anantapur and others.

This class notes is meant for First semester M.Tech VLSI Students of SKUCET ,Anantapur and others.

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    UNIT-I DIGITAL SYSTEM DESIGN UNIT-I DIGITAL SYSTEM DESIGN Document Transcript

    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com UNIT-I : DIGITAL SYSTEM DESIGN Introduction : As flowcharts are useful in software design , in the same way ASM Charts or State Machine charts are useful in the hardware design of digital systems. This SM chart is a special type of state machine flowchart, or SM chart for short. SM charts are also called ASM (algorithmic state machine) charts. These SM Charts have many advantages. It is easier to understand the operation of a digital system by inspection of the SM chart instead of the equivalent state graph. A given SM chart can be converted into several equivalent forms, and each form leads directly to a hardware realization. State diagram State diagram is a pictorial representation of a behavior of a sequential circuit. The state is represented by the circle, and the transition between states is indicated by directed lines connecting the circles. A directed line connecting a circle with itself indicates that next state is same as present state. State table : The information of the state diagram represented in a tabular form is known as state synthesis table or simply state table. Transition table. A transition table is the next step to state table. The state diagram and state table represent state using symbols or names. In the transition table specific state variable values are assigned to each state. Assignment of values to state variables is called state assignment. ASM Charts : A State Machine chart or Algorithmic State Machine(ASM) ,which is similar to a flow-chart is used to describe the behavior of a digital system or state machine. Algorithmic State Machine charts are also known as State Machine (SM) Chart. The basic difference between an ordinary flow chart and SM chart is that ,certain specific rules must be followed in the construction of SM chart ,but no such specific rules are to be followed in the case of flow-chart.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com An Algorithmic system. State Machine Chart can be constructed from the State Graph of a Digital ASM CHART –COMPONENTS: There are three important components in an ASM Chart. They are (i)State Box (ii) Decision Box and (iii) Conditional output Box . State Box: The state box contains a state name followed by a slash (/) and an optional output list. After the state assignment ,a state code must be placed outside the box at the top. Decision Box: A decision box is represented by the diamond shape symbol with true and False branches. The condition placed in the box is a Boolean expression that is evaluated to determine which branch is true. (a).State box (b).Decision box Conditional output Box: The conditional output box (c).Conditional Output box , which has curved ends contains a conditional output list. The conditional outputs depend on both the state of the system and inputs. Specific Rules for constructing ASM Chart: Certain rules must be followed while constructing an SM block. For every valid combination of input variables , there must be exactly one exit path defined .This is necessary because ,each allowable input combination must lead to a single next state. The second rule is no internal feedback within an SM block is allowed. This is shown in the diagram below.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Wrong feedback Correct feedback Conversion of State graph into Equivalent ASM Chart: Let us consider a state graph with three states S0, S1 and S2 as shown below.Here Za,Zb and Zc are the Moore outputs. And Z1 ,Z2 are the Mealy outputs which change after a state change or input change. The Moore outputs change only after a state change. The equivalent state chart is shown below.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Derivation of ASM Charts: To derive the ASM chart for any digital system ,first its block diagram must be drawn. Next ,the required input,output signals must be defined .Then the ASM Chart must be constructed ,that tests the input signals and generates the proper sequence of the output signals. Let us consider the case of a binary Multiplier .In the binary Multiplier ,there will be a add shift controller which generates required sequence of add and shift signals.The counter counts the number of shifts and outputs K=1 ,just before the last shift occurs. The block diagram and ASM Chart for Binary Multiplier is shown below.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Figure: ASM chart In the ASM chart ,in the state S0,where the start signal St is 1 ,the registers are loaded.In S1,the Multiplier bit M is tested. If M=1, an add signal is generated and the shift signal is generated and
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com K is tested. If K=1 ,this will be the last shift and the next state is S3. In S2, a shift signal is generated , since a shift must always follow and add . If K=1 ,the network goes to S 3 at the time of the last shift, otherwise ,the next state is S1. In S3 ,the Done signal is turned ON. ASM Chart for Dice Game: Let us derive the SM chart for the electronic dice game. Figure below shows the block diagram for the dice game. Here two counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2, . . . . Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through 12. The two important rules of the game are as follows: 1. After the first roll of the dice, the player wins if the sum is 7 or 11. He loses if the sum is 2, 3, or 12. Otherwise, the sum which he obtained on the first roll is referred to as his point, and he must roll the dice again. 2. On the second or subsequent roll of the dice, he wins if the sum equals his point, and he loses if the sum is 7. Otherwise, he must roll again until he finally wins or loses.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The inputs to the dice game come from two push buttons, Rb (roll button) and Reset. Reset is used to initiate a new game. When the roll button is pushed, the dice counters count at a high speed, so the values cannot be read on the display. When the roll button is released, the values in the two counters are displayed and the game can proceed. Because the button is released at a random time, this simulates a random roll of the dice. If the Win light or Lose light is not on, the player must push the roll button again. The components for the dice game shown in the block diagram include an adder which adds the two counter outputs, a register to store the point, test logic to determine conditions for win or lose, and a control circuit. The input signals to the control circuit are defined as follows: D7 = 1 if the sum of the dice is 7 D711 = 1 if the sum of the dice is 7 or 11 The ASM Chart for Dice game is shown below.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com D2312 = 1 if the sum of the dice is 2, 3, or 12 Eq = 1 if the sum of the dice equals the number stored in the point register Rb = 1 when the roll button is pressed Reset = 1 when the reset button is pressed The outputs from the control circuit are defined as follows: Roll = 1 enables the dice counters Sp = 1 causes the sum to be stored in the point register Win = 1 turns on the win light Lose = 1 turns on the lose light. In the ASM Chart control circuit waits in state S0 until the roll button is pressed (Rb = 1). Then, it goes to state S1, and the roll counters are enabled as long as Rb = 1. As soon as the roll button
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com is released (Rb = 0), D711 is tested. If the sum is 7 or 11, the circuit goes to state S2 and turns on the Win light; otherwise, D2312 is tested. If the sum is 2, 3, or 12, it goes to state S3 and turns on the Lose light; otherwise, the signal Sp becomes 1, and the sum is stored in the point register. It then enters S4 and waits for the player to “roll the dice” again. In S5, after the roll button is released, if Eq = 1, the sum equals the point and state S2 is entered to indicate a win. If D7 = 1, the sum is 7 and S3 is entered to indicate a loss. Otherwise, the control returns to S4 so that the player can roll again. When in S2 or S3, the game is reset to S0 when the Reset button is pressed. Hardware description language : Though the ASM chart methodology is very useful in the digital design process ,its main disadvantage is that it is time consuming to draw the charts for large systems and also become cumbersome. So, hardware oriented features of programming languages are used to express specific the design are used. These hardware description languages also provide the schematic of the corresponding digital system or even obtain the layout of an integrated circuit to realize it. There are two important popular Hardware Description Languages, VHDL and VeriLog Though these languages are complex, they have the features to declare flip-flops, registers, counters etc., which are the building blocks of any digital system. A state machine can be modeled in VHDL as a structural description, dataflow description, or a behavioral description. In this text, the behavioral description is considered. The structure of the behavioral description is based here on two processes within the architecture of the design . (i). The first process describes the transition from the current state to the next state. (ii). The second process describes the output values for the current state and describes the next state. The behavioral description uses the If-then-else and Case-when statements to achieve the required state machine behavior. VHDL Code For Multiplier: Let us write a behavioral VHDL model for the multiplier based on the block diagram shown below figure (i) and the state graph of figure (ii). As the control circuit has ten states, it is declared an integer in the range 0 to 9 for the state signal . The signal ACC represents the 9-bit accumulator output .
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com As indicated in figure (i) above , 4 bits from the accumulator (ACC) and 4 bits from the multiplicand register are connected to the adder inputs ; the 4 sum bits and the carry output from the adder are connected back to the accumulator. When an add signal (Ad ) occurs, the adder outputs are loaded into the accumulator by the next clock pulse, thus, causing the multiplicand to be added to the accumulator. An extra bit at the left end of the product register temporarily
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com stores any carry which is generated when the multiplicand is added to the accumulator. When a shift signal (Sh) occurs , all 9 bits of ACC are shifted right by the next clock pulse. The following Behavioral code is written for the 4-bit Multiplier based on the above block diagram and state graph. Behavioral Code: library IEEE; use IEEE.STD_LOGIC_1164. ALL; use IEEE.STD_LOGIC_ARITH. ALL; use IEEE.STD_LOGIC_UNSIGNED. ALL; entity mult4X4 is port (Clk, St: in std_logic; Mplier, Mcand : in std_logic_vector(3 downto 0); Done: out std_logic; Product: out std_logic_vector (7 downto 0)); end mult4X4 ; architecture behave1 of mult4X4 is signal State: integer range 0 to 9; signal ACC: std_logic_vector(8 downto 0) ; alias M: std_logic is ACC(0) ; -- accumulator -- M is bit 0 of ACC begin Product <= ACC (7 downto 0); process (Clk) begin if Clk‟event and Clk = „1‟ then case State is when 0 => --initial State if St = „1‟ then ACC(8 downto 4) <= “00000”; -- clear upper ACC ACC(3 downto 0) <= Mplier; -- load the multiplier State <= 1; end if; when 1 | 3 | 5 | 7 => -- “add/shift” State -- executes on rising edge of clock
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com if M = „1‟ then -- Add multiplicand to ACC ACC(8 downto 4) <= („0‟& ACC(7 downto 4)) + Mcand; State <= State + 1; else ACC <= „0‟ & ACC(8 downto 1); -- Shift accumulator right State <= State + 2; end if; when 2 | 4 | 6 | 8 => -- “shift” State ACC <= „0‟ & ACC(8 downto 1); -- Right shift State <= State + 1; when 9 => -- end of cycle State <= 0; end case; end if; end process; Done <= „1‟ when State = 9 else „0‟; end behave1 Explanation of the Code: The signals ACC, Mcand, and Mplier are declared as type std_logic_vector so that the over loaded “+” operator can be used for addition. The statement “alias M:std_logic is ACC(0);” allows to use the name M in place of ACC(0). The product is set equal to the lower 8 bits of ACC in a concurrent statement (line 16). Because all register operations and state changes occur on the rising edge of the clock, here process is used that executes when Clk changes. The case statement specifies the actions to be taken in each state. In state 0, if St = '1' the multiplier is loaded into the accumulator at the same time the state changes to 1 (lines 21–26). It is clear from the state graph, that the same operations occur in states 1, 3, 5, and 7.The notation “when 1 | 3 | 5 | 7 =>” means when state is 1 or 3 or 5 or 7, the statements that follow will execute. When M = '1', the expression '0' & ACC(7 downto 4) + Mcand
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Computes the adder output, which is loaded into ACC (lines 28–29). At the same time, the circuit goes to the next state in sequence (2, 4, 6, or 8). If M = '0', ACC is shifted to the right by loading ACC with '0' concatenated with the upper 8 bits of ACC (line 31). At the same time the state changes to 3, 5, 7, or 9 (the present state + 2). In states 2, 4, 6, or 8 ACC is shifted to the right, and state changes to the next state in sequence (lines 34–36). Example 2-VHDL Code for a Serial Adder: Let us consider the VHDL code for the serial adder with accumulator shown in figure(i) below. In figure (i) below, if Sh = 1, the carry from the full adder is stored in the flip-flop at the same time the registers are shifted on the falling edge of the clock.The VHDL code is based on the state graph for the controller shown in figure(ii). In the present VHDL program two processes are used to represent the state machine.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com VHDL Behavioral Code: library IEEE; use IEEE.STD_LOGIC_1164.all ; entity serial is Port (St: in std_logic; Clk: in std_logic; Xout: out std_logic_vector(3 downto 0)); end serial; architecture Behavioral of serial is signal X, Y: std_logic_vector(3 downto 0); signal Sh: std_logic; signal Ci, Ciplus: std_logic; signal Sumi: std_logic; signal State, NextState: integer range 0 to 3; -- 4 states begin Sumi <= X(0) xor Y(0) xor Ci ; Ciplus <= (Ci and X(0)) or (Ci and Y(0)) or (X(0) and Y(0)) ; Xout <= X ; process (State, St) begin case State is when 0 => if St = „1‟ then Sh <= „1‟; NextState <= 1 ; else Sh <= „0‟; NextState <= 0; end if ; -- full adder
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com when 1 => Sh <= „1‟; NextState <= 2 ; when 2 => Sh <= „1‟; NextState <= 3 ; when 3 => Sh <= „1‟; NextState <= 0 ; end case; end process; process (clk) begin if clk‟event and clk = „0‟ then State <= Next State; -- update state register if Sh = „1‟ then X <= Sumi & X(3 downto 1); -- shift Sumi into X register Y <= Y (0) & Y(3 downto 1); -- rotate right Y register Ci <= Ciplus; end if; -- store next carry end if; end process; end Behavioral Explanation of the Code: The first process executes whenever state or St changes, and it generates the Next State and Sh signals. The second process updates the state after the falling edge of the clock. At the same time, if Sh = '1' the registers are shifted, and the carry is stored in the flip-flop.The full adder is implemented using concurrent statements for the sum and carry. This is appropriate because the full adder uses combinational logic that does not require a clock. Because std_logic and std_logic vectors are used in the code, the library and use statements are required. These statements need not be used if bits and bit_vectors were used in the program. State Reduction: The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem. State-reduction algorithms are concerned with procedures for reducing the number of states in a state table, while keeping the external input–output requirements unchanged. State reduction is the elimination of states which are equivalent within the state machine and state assignment is the method of assigning a binary value to a state name that will create a reduced logic equation.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Since m flip-flops produce 2m states, a reduction in the number of states may (or may not) result in a reduction in the number of flip-flops. . For example, if a table with nine states is reduced to eight states, the number of flip-flops required is reduced from four to three, with a possible corresponding reduction in the amount of input logic for the flip-flops. If the table is further reduced to six states, three flip-flops are still required, but the presence of more don‟t-cares in the flip-flop input equations will probably further reduce the required logic. Given the reduced state table, the next step in synthesizing the circuit is to assign binary flipflop states to correspond to the circuit states. The way in which this assignment is made will determine the amount of logic required for the circuit. There are three important methods of State reduction.(i) Row matching, Implication Charts, and Successive partitioning. Among the three methods the row matching is the simplest method that gives reasonably good results. The Implication Chart uses a graphical grid to find any implications or equivalences and is a systematic approach to reducing state machines.Successive partitioning is a blend between row matching and implication chart where both a graphical table and equivalent matching is used. I. Row Matching : This is explained by the following simple steps. Step 1 : Start with state transition table Step 2 : Identify states with the same output Step 3 : If such states transition to the same next state, they are equivalent Step 4: Combine the equivalent states into a single new renamed state Step 4: Repeat until no new states are combined Example: Let us consider a state table shown below to which the method is to be applied.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com From the observation of the table ,it is clear that there is no way of telling states H and I apart. That is, if we start in state H, the next state is A and the output is 0; similarly, if we start in state I, the next state is A and the output is 0. Hence, the states H and I are not apart(different), and I can be replaced with H. After this, there is no way to reach state I ,so row I can be removed from the table. We say that H is equivalent to I (H ≡ I).Similarly, rows K, M, N, and P have the same next state and output as H, so K, M, N, and P can be replaced by H, and these rows can be deleted. Also, the next states and outputs are the same for rows J and L, so J ≡ L. Thus, L can be replaced with J and eliminated from the table. The result is shown in table (ii) below.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com After these changes in the table, rows D and G are identical and so are rows E and F. Therefore, D ≡ G, and E ≡ F, so states F and G can be eliminated. Figure (i) shows a state diagram for the final reduced table. In general ,row matching is not sufficient to find all equivalent states, except in the special case where the circuit resets to the starting state after receiving a fixed number of inputs.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Fig.Reduced State Table and Graph. II.Implication Table Method : In this method all of the equivalent states in a state table are found. If the equivalent states found by this procedure are eliminated, then the table can be reduced to a minimum number of states. This implication table or pair chart method is used to check each pair of states for possible equivalence. The nonequivalent pairs are systematically eliminated until only the equivalent pairs remain. The first step in this procedure is a chart is constructed as shown in figure (i) below. This chart has a square for every possible pair of states. A square in column i and row j corresponds to state pair i-j. Thus, the squares in the first column correspond to state pairs a-b, a-c, etc. The squares above the diagonal are not included in the chart because if i ≡ j, j ≡ i, and only one of the state pairs i-j and j-i is needed. Also, squares corresponding to pairs a-a, b-b, etc., are omitted. To fill in the first column of the chart, row a of table(i) is compared with each of the other rows. Because the output for row a is different than the output for row c, an X is placed in a-c square of the chart to indicate that. a ≢ C. Similarly, X‟s are placed in squares a-e, a-f , and a-h to indicate that a ≢ e , a ≢ f , and a ≢ h because of output differences. States a and b have the same outputs, so, a ≡ b iff d ≡ f and c ≡ h.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com To indicate this, the implied pairs, d-f and c-h, are placed in the a-b square . Similarly, because a and d have the same outputs, a-d and c-e are placed in the a-d square to indicate that a ≡ d iff a ≡ d and c ≡ e . Figure(i) The entries b-d and c-h in the a-g square indicate that a ≡ g iff b ≡ d and c ≡ h Next, row b of the state table is compared with each of the remaining rows of the table, and column b of the implication chart is filled in. Similarly, the remaining columns in the chart are filled in to complete above figure(i). Selfimplied pairs are redundant, so a-d can be eliminated from square a-d, and c-e from square c-e. At this point, each square in the implication table has either been filled in with an X to indicate that the corresponding state pair is not equivalent (because the outputs are different) or filled in with implied pairs. Let us now check each implied pair. If one of the implied pairs in square i-j is not equivalent, then i ≢ j. The a-b square of figure (i) contains two implied pairs (d-f and c-h). Because d ≢f . (the d-f square has an X in it), a ≢ b and an X is placed in the a-b square, as shown in figure (ii) below. Continuing to check the first column, it can be found that the a-d square contains the implied pair c-e.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Because square c-e does not contain an X, we cannot determine whether or not a ≢ d.similarly, because neither square b-d nor c-h contains an X, it is not possible to determine immediately whether a ≢g. or not. Moving to the second column, an X‟s are placed in squares b-d and b-g because we have already shown a ≢ f and b ≢ f. In the same way, each of the remaining columns is checked and X out squares c-f, d-g, e-f , and f-h. The resulting chart is shown below in figure (ii) above. In the process of simplification,certain non-equivalent state pairs are not considered. So, consider the above chart again to check if the added X‟s make any other pairs nonequivalent. Rechecking column a, it can be found that an X can be placed in square a-g because square b-d has an X. Checking the remaining columns, we X out squares c-h and e-h because d-g and a-g have X‟s. This completes the second pass through the implication table and it is shown in figure (iii) below. As some X‟s are added on the second pass, a third pass is required.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com In third pass no new X‟s are added through the table, so all squares which correspond to nonequivalent state pairs have been Xed out. The coordinates of the remaining squares then correspond to equivalent state pairs. Because square a-d (in column a, row d ) does not contain an X, it can be concluded that a ≡ d. Similarly, square c-e does not contain an X, so c ≡ e. All other squares contain X‟s, so there are no other equivalent state pairs. It is clear that equivalent states are determined from the column-row coordinates of the squares without X‟s, not by reading the implied pairs contained within the squares. If d is replaced with a and e with c in table (i) above, rows d and e, can be eliminated and the table reduces to six rows, as shown in table (ii) below. So,the conclusion is that finding the equivalent states within a single state table reduces the number of rows in the table and reduction in the number of rows leads to a sequential circuit with fewer gates and flip-flops.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com III. Partitioning Method : The partitioning method is a blend of s row matching and implication chart in that it uses a visual detection for equivalences as well as a chart to organize the process. Partitioning provides a straightforward procedure for determining equivalency for any amount of complexity. Successive partitioning steps produce smaller partitions. If the next step does not yield any smaller partitions no further steps will yield any smaller partitions and, hence, the partitioning process is then complete. All states that are in the same partition after k steps are k equivalent. All states that are in the same partition when no further partitioning can be accomplished are equivalent. States that are not in the same final partition are not equivalent.This type of partition method gives fewer states finally and helps in the reduction of Flip-Flops in the design. State Assignments : In synthesizing digital circuit ,after reducing the state table, the next step is to assign binary flip-flop states to the corresponding circuit states. This methodology is known as state assignment. The way in which this assignment is made will determine the amount of logic required for the circuit. The problem of finding a good state assignment which leads to an economical circuit is always an important and difficult task. The cost of the logic required to realize the sequential circuit is strongly dependent on the way the state assignment is made. There are many methods for the state assignment. They are Trial & Error method and Guidelines based method etc. The trial and error method is useful for only circuits having small number of states . The guidelines based method is based on certain pre-defined guide lines. Assignments for two states are said to be adjacent if they differ in only one variable. Thus, 010 and 011 are adjacent, but 010 and 001 are not. The following guidelines are useful in making assignments which will place 1‟s together (or 0‟s together) on the next-state maps: (a). States which have the same next state for a given input should be given adjacent assignments. (b). States which are the next states of the same state should be given adjacent assignments. (c). States which have the same output for a given input should be given adjacent assignments.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The application of Guideline (c) will place 1‟s together on the output maps. The first step is to write down all of the sets of states which should be given adjacent assignments according to the guidelines. Then, using a Karnaugh map, try to satisfy as many of these adjacencies as possible. A fair amount of trial and error is needed to fill in the map so that the maximum number of desired state adjacencies is obtained. But , the limitation of this methods is the method work well for D-Flip-flops and JK-Flip-flops. They do not work well for T and RS flip-flops. So, another method called One-hot encoding is widely used for state assignment problem. One-Hot Encoding: In the one-hot encoding (OHE) only one bit of the state variable is “1” or “hot” for any given state. All other state bits are zero. Therefore, one flip-flop (register) is used for every state in the machine i.e. n states uses n flip-flops. Using one-hot encoding, the next-state equations can be derived easily from state diagrams. State decoding is simplified, since the state bits themselves can be used directly to indicate whether the machine is in a particular state. In addition, with a one-hot encoded state machine, the inputs to the state bits are often simply the functions of other state bits FPGAs are programmable logic devices that are rich in flip-flops and poor in combo logic. OneHot state machines use one flip-flop per state and thus need much less decode logic. This makes one-hot encoding more efficient for FPGAs. One-hot state machines use one flop per state. The One-Hot encoding for a 5 state variables is shown below in table. State State Variables One-Hot Code S0 S1 S2 S3 S4 00001 00010 00100 01000 10000 Binary Code 000 001 010 011 100 Gray Code 000 001 011 010 110 One-hot encoding (OHE) is better suited for use with the fan-in limited and flip-flop-rich architectures of the higher gate count filed-programmable gate arrays (FPGAs), such as offered by Xilinx, Actel, and others. OHE maps very easily in these architectures. One-hot state
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com machines are typically faster. Speed is independent of the number of states, and instead depends only on the number of transitions into a particular state. FPGA have plenty of registers but the LUTs are limited to few bits wide. One-hot increases the flip-flop usage (one per state) and decreases the width of combinatorial logic. It makes it easy to decode the next state, resulting in large FSMs. And finally, since one hot code state assignment reduces the area (area optimization) by using less logic gates, it consumes less power. There are numerous advantages to using the one hot design methodology : • Maps easily into register-rich FPGA architectures such as QuickLogic and Xilinx. • One-hot state machines are typically faster. Speed is independent of the number of states, and instead depends only on the number of transitions into a particular state. A highly-encoded machine may slow dramatically as more states are added. • Don‟t have to worry about finding an "optimal" state encoding. This is particularly beneficial as the machine design is modified, for what is "optimal"for one design may no longer be best if you add afew states and change some others. One-hot is equally "optimal" for all machines. • One-hot machines are easy to design. Schematics can be captured and HDL code can be written directly from the state diagram without coding a state table. • Modifications are straightforward. Adding and deleting states, or changing excitation equations, can be implemented easily without affecting the rest of the machine. • Easily synthesized from VHDL or Verilog. • There is typically no area penalty over highly encoded machines. • Critical paths are easy to find using static timing analysis. • Easy to debug. Bogus state transitions are obvious, and current state display is trivial. Using a One-Hot State Assignment : In designing with sequential CPLDs and FPGAs , it is considered that each logic cell contains one or more flip-flops. These flip-flops are there whether we use them or not. This means that it may not be important to minimize the number of flip-flops used in the design. Instead, we should try to reduce the total number of logic cells used and try to reduce the interconnections between cells. When several cells are cascaded to realize a function the propagation delay is increased and the logic runs slower. In order to design faster logic, we should try to reduce the number of cells required to realize each equation. The one-hot state assignment help to solve this.
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The one-hot assignment uses one flip-flop for each state, so a state machine with N states requires N flip-flops. Exactly one of the flip-flops is set to one (Hot) in each state and all others are reset.(cold or zero). Foe example let us consider the implementation of an LUT in FPGA device . The output of the LUT can be written as F= a‟b‟c‟d‟ + a‟b‟c‟d + a‟bcd + ab‟c‟d + ab‟cd‟ +----------------------+ abcd Here each one of the term requires one function generator. If we use one-Hot assignment , the system with four states a,b,c,d (S0, S1, S2, and S3) could use four flip-flops (Q0, Q1, Q2, and Q3) with the following state assignment . S0 : Q0 Q1 Q2 Q3 = 1000 , S1: Q0 Q1 Q2 Q3 = 0100 , S2 : Q0 Q1 Q2 Q3 = 0010 and , S3 : Q0 Q1 Q2 Q3 = 0001 the remaining 12 combinations are not considered. The next-state and output equations are written by inspecting the state graph. Consider the partial state graph given in Figure below. In the graph all the four arcs lead into S3, so,there are four conditions under which the next state is S3. These conditions are Present state (PS) = S0 and X1 = 1, PS = S1 and X2 = 1, PS = S2 and X3 = 1, PS = S3 and X4 = 1. The next state of flip-flop Q3 is 1 under these four conditions (and 0 otherwise).
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Therefore, the next-state equation for Q3 can be written as Q+3 = X1 (Q0 Q1′ Q2′ Q3′ ) + X2 (Q0′ Q1 Q2′ Q3′) +X3 (Q0 ′ Q1′ Q2 Q3′ ) + X4 (Q0′ Q1′ Q2′ Q3 ) Here as Q0 = 1 means Q1 = Q2 = Q3 = 0, and the Q1 ′ Q2′ Q3′ term is redundant and so it can be eliminated. Similarly, all of the primed state variables can be eliminated from the other terms, so the next-state equation reduces to Q+3 = X1Q0 + X2Q1 + X3Q2 + X4Q3 In general, when a one-hot state assignment is used, each term in the next-state equation for each flip-flop contains exactly one state variable, and the reduced equation can be written by inspecting the state graph. Similarly, each term in each reduced output equation contains exactly one state variable. Because Z1 = 1 when PS = S0 and X1 = 1, and also when PS = S2 and X3 = 1, we can write that Z1 = X1Q0 + X3Q2. By inspecting the state graph, we can also write that Z2 = X2Q1 + X4Q3 When a one-hot assignment is used, resetting the system requires that one flip flop be set to 1 instead of resetting all flip-flops to 0. If the flip-flops used do not have a preset input, then we can modify the one-hot assignment by replacing Q0 with Q0′ throughout. The assignments for this are S0 : Q0 Q1 Q2 Q3 = 0000, S1 : Q0 Q1 Q2 Q3 = 1100, S2: Q0 Q1 Q2 Q3 = 1010, S3: Q0 Q1 Q2 Q3 = 1001 And the modified equations are Q3+ = X1Q0′ + X2Q1 + X3Q2 + X4Q3 Z1 = X1Q0′ + X3Q2, Z2 = X2Q1 + X4Q3 While designing with CPLDs or FPGAs, one should try both an assignment with a minimum number of state variables and a one-hot assignment to check which one leads to a design with
    • Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com the smallest number of logic cells. Alternatively, if the speed of operation is important, the design which leads to the fastest logic should be chosen. When a one-hot assignment is used, more next-state equations are required, but for some state graphs both the next-state and output equations may contain fewer variables. An equation with fewer variables may require fewer logic cells to realize. The more cells which are cascaded, the longer the propagation delay, and the slower the operation. -----------xxxxxxxx--------- References: (i). Fundamentals of Logic design – Charles H.Roth Jr. (ii). Engineering Digital Design, 2/e, Richard F Tinder