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Special Devices
 

Special Devices

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This class notes is useful for M.Sc Electronics students of SKU & RU and other ECE students

This class notes is useful for M.Sc Electronics students of SKU & RU and other ECE students

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    Special Devices Special Devices Document Transcript

    • 1 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com SPECIAL DEVICESUniversal Active Filter : The rapid developments in integrated circuit technology ,paved the way to designing filter circuits on a single chip which can simultaneously give Low-pass , High-pass, Band-pass output responses . These filter circuits are known as Universalfilters. Using the Universal filters , Notch and all-pass filter response can also be obtained .Thechip has the features of easy control gain and Q-factor .This universal filter is also commonlyknown as state variable filter.Commercially the universal filter is available as a 16-pin DIP IC (FLT-U2) from Datel company.The important characteristics are :The filter has a frequency range of 0.001 Hz to 200KHz.The figure of Merit is (Q):0.1 to 100.Frequency stability is 0.001% per 0CVoltage gain is : 0.1 to 1000Input impedance is 5Mohms.Unity gain bandwidth is 3M.Hz and the Slew rate is 1V/uS.
    • 2 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comWorking: The Datel’s FLT-U2 is the best example of a universal filter that uses the state statevariable active filter principle to implement second order low-pass, high-pass and band – passfunctions. The filter consists of four op-amps in which three are connected for filter action andthe fourth unconnected op-amp is used as a gain stage or buffer amplifier or used to raise theorder of the filter.Two–pole (second order) low-pass ,high-pass and band-pass filter functions are obtainedsimultaneously from three different outputs ,and notch and all-pass functions are available bycombining these outputs in the uncommitted operational amplifier.To realize higher order filtersseveral FLT-U2s can be cascaded.Frequency tuning is done by using two external resistors and the Q-tuning is done by a thirdresistor. By using suitable components externally any of the filter types like Butterworth,Chebyshev or Bessel may also be implemented using this universal filter.
    • 3 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comTIMER IC 555 :Due to the inherent limitations of mechanical and electro mechanical timers, solid state timers inIC form gained momentum. The most popular integrated circuit timer is 555 , first introduced bySignetics corporation in the year 1971 and later National Semiconductor corporation asSE555/555NE. It is a low cost, easy to use versatile IC which can operate from supply voltagesof +5V to +18V.The 555 timer is available in two packages. T0-99 circular metal Can andDIP.This DIP is available as 8 pin and 14 pins also.Description of Functional Diagram:The 555 timer consists of two op-amp comparators, one flip- flop and two transistors. The o/p ofthe comparators set and reset the flip-flop. The F/F in turn controls the o/p level and theconduction of two control transistors T1 and T2. A voltage divider network between VCC andGround provides 2/3 VCC to the inverting terminal of threshold comparator and 1/3 Vcc to thenon-inverting input of Trigger comparator.When the voltage at threshold terminal greater than or equal to 2/3VCC, the O/P of thresholdcomparator goes HI and Flip-Flop is reset. Q¯= 1 . This turns T1 on and drives the o/p to low.
    • 4 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comWhen the voltage at the trigger input is less than 1/3 VCC , its O/P goes high. Which makes Q¯=0 .AS a result T1 is cutoff and the output goes high. Once the circuit is triggered, it remains inthat state until the set time is elapsed (i.e. voltage at the threshold terminals reaches 2/3VCC) .Thecircuit do not change for further triggering during this period. However application of varyingDC voltage to the pin 5 (Control voltage) alters the timing cycle. The output can be pulse widthmodulated by applying a sinusoidal voltage to this terminal.The 555 timer has two basic operational modes : (i) one shot and (ii) Astable . In the one-shotmode, the 555 acts like a mono-stable multivibrator. A monostable has a single stable state--thatis the off state. Whenever it is triggered by an input pulse, the monostable switches to itstemporary state. It remains in that state for a period of time determined by an RC network. It thenreturns to its stable state. In other words, the mono-stable circuit generates a single pulse of afixed time duration each time it receives an input trigger pulse. Hence the name one-shot. One-shot multivibrators are used for turning some circuit or external component on or off for aspecific length of time. It is also used to generate delays. When multiple one-shots are cascaded,
    • 5 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.coma variety of sequential timing pulses can be generated. Those pulses will allow you to time andsequence a number of related operations.The other operational mode of 555 is an astable multivibrator. An astable multivibrator issimplly an oscillator. The astable multivibrator generates a continuous stream of rectangular off-on pulses that switch between two voltage levels. The frequency of the pulses and their dutycycles depend on the values of RC network .The XR-2240 Programmable Timer/Counter :The XR-2240, programmable timer/counter is a monolithic controller capable of producingultra long time delays without the loss of accuracy. It can generate accurate time delays fromseconds to days. Two such timing circuits can be cascaded to generate time delays of up to threeyears. The XR-2240 consists of one modified 555 timer(Time base circuit), one8-bit programmable binary counter and control circuit (Flip-Flop). All these contained in asingle 16-pin DIP chip. The time delay is set by an external R-C network and can beprogrammed to any value from IRC to 255RC. In astable operation ,the circuit can generate 256separate frequencies from a single RC setting and can be synchronized with external clocksignals.Both the control inputs and outputs are compatible with TTL and DTL logic levels.Thetime base works as an astable multivibrator with a period equal to RC .The eight bit binarycounter can divide the time base output by any integer value from 1 to 255.The counter mayoperate independently of the time base.Features: Generate time delays from microseconds to days Programmable delays: 1 RC to 255 RC Voltage Supply Range: 4V to 15V. TTL and DTL compatible outputs. Accuracy : 0.5%
    • 6 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comWorking of XR-2240 : The timing cycle for the XR-2240 is initiated by applying a positivegoing trigger pulse to the input (pin 11).So, it starts the 555 time base oscillator and enables thecounter section and sets all the counter outputs to low state.The time base oscillator generates timingpulses with a period of RC .These clock pulses are counted by the binary counter. A positive going pulseon reset pin (10) stops the 555 timer base oscillator. The threshold voltage for both trigger and resetterminals is about 1.4V.The Time base period T for one Cycle of 555 oscillators is set by an external RC network connected tothe timing pin 13. Therefore T=RC ; R: Range from 1KΩ to 10MΩ; C; Ranges from 0.05 to 1000 μFThe binary counter outputs are open collector outputs .So, they are shorted together to a common pull-up resistor to form a wired-or connection.The combined output will be low as long as any one of the
    • 7 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comoutputs is low. So,the delays associated with each counter output can be summed by simply shortingthem together to a common output bus as shown in the figure. Suppose ,the pin 6 alone is connected tothe output and rest are left open,the total time delay would be equal to 32T.In the same way if pins 1,4and 8 are shorted to the output bus ,the total time delay would be (1+ 8+128) RC= 137RC .So,by properchoice of counter terminals connected to the output bus ,we can achieve the required timing cycledefined by 1T≤ Delay time ≤ 255 T.In the above circuit when the switch S is closed the circuit operates in monostable mode of operationand when it is open it works in astable mode of operation.Applications: XR-2240 has many applications and widely used in generating accurate delays andfrequency synthesis circuits. Some of the applications include (i) Precision Timing (ii) Long delay generation (iii) Digital sample and hold (iv) Pulse counting/summing (v) Frequency synthesis .
    • 8 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comFunction Generator IC 8038: The ICL8038 is a monolithic precision waveform generatorIC manufactured by Intersil and capable of producing sine, square and triangular outputwaveforms, simultaneously with a minimum number of external components or adjustments. Itsoperating frequency range is from 0.001Hz to 300kHz. There is an option to control theparameters like frequency,duty cycle and distortion of these functions.It is highly stable over awide range of temperatures and supply voltages .It can be operated using either a single powersupply (10-30V) or a dual supply also. The 8038 IC is available as a14 pin DIP chip as shownin the diagram.Pin 1 and Pin12: Sine wave adjusts. The external resistor connections to these pins decide the accuracy of sine waves. For distortionless than 1% we have to connect 100KΩ potentiometer between pin 12 and ground or –VEE. To get adistortion less than 0.5%, we have to connect two 100KΩ potentiometers between VCC and ground. Withone of the wipers to pin 1 and other to pin 12.Pin 2 Sine wave output: The sine wave output of amplitude 0.22 Vi is available at this pin.Pin 3: Triangular wave O/P: A Triangular wave of 0.33 Vi is available at this pin.Pin 4 and 5: Duty cycle/Frequency adjust :The frequency of the o/p signal is promotional to thecharging and discharging currents and duty cycle can be adjusted by selecting proper values of R1 and
    • 9 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comR2 between pins 4 and 5 and a capacitor connected at pin 10. The range of the values varies from 1KΩto 1MΩ.Principle: The working principle of 8038 can be understood from the block diagram. Theoperation is based on the charging and discharging a grounded capacitor(C) whose charging anddischarging rates are controlled by programmable current sources I1 and I2. When the switch isat the position A the capacitor charges at rate determined by current sources I1. Once thecapacitor voltage reaches Vu, the upper comparator (comp1) triggers and reset the FF o/p. Thiscauses the switch position to change from position 1 to 2. Now, the capacitor starts dischargingat the rates determined by the current source I2.Once the capacitor reaches VL, the lower comparator (comp2) triggers and sets the FF o/p. Thischanges the switch position from to position 1. This process repeats. So, we get a square wave atthe output of the flip-flop and triangular wave across the capacitor. The triangular wave is thenpassed thorough an on chip wave shaper (sine converter) , which generates a sine wave.To allow automatic frequency control currents I1 and I2 are made programmable by an externalcontrol voltage Vi. For equal magnitudes of I1 and I2, the output wave forms are symmetrical;conversely when two currents are unequal, output wave forms are asymmetrical. By making oneof the currents much larger than the other we can get saw tooth waveforms across the capacitor andrectangular wave at the o/p of the flip-flop.
    • 10 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comXR-2206- Function generator: The XR-2206 is a monolithic function generator capableof producing high quality sine , Sqare, triangular, ramp and pulse wave forms of high stabilityand frequency modulated by an external voltage. Frequency of operation can be selected over arange of 0.01Hz to more than 1 MHz.The circuit is ideally suited for communications, instrumentation, and function generatorapplications requiring sinusoidal tone, AM, FM, or FSK generation. It has a typical driftspecification of 20ppm/°C. The oscillator frequency can be linearly swept over a 2000:1frequency range with an external control voltage, while maintaining low distortion.Functional Block Diagram: The XR-2206 monolithic circuit consists of four major blocks.They areVoltage Controlled Oscillator(VCO) 1. An analog multiplier and sine shaper. 2. A unit gain buffer amplifier and 3. A set of current switches as shown below.
    • 11 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comThe VCO produces an output frequency proportional to an input current, which is set by aresistor from the timing terminals to ground. With two timing pins, two discrete outputfrequencies can be Independently produced for FSK generation applications by using the FSKinput control pin. This input controls the current switches which select one of the timing resistorcurrents, and routes it to the VCO.The XR-2206 can be operated with two separate timing resistors, R1 and R2, connected to thetiming Pin 7 and 8, respectively,Depending on the polarity of the logic signal at Pin 9, either oneor the other of these timing resistors is activated. If Pin 9 is open-circuited or connected to a biasvoltage 2V, only R1 is activated. Similarly, if the voltage level at Pin 9 is 1V, only R2 isactivated. Thus, the output frequency canbe keyed between two levels. f1 and f2, as : f1 = 1/R1C and f2 = 1/R2CFor split-supply operation, the keying voltage at Pin 9 is referenced to V-.Frequency of OperationThe frequency of oscillation, fo, is determined by the external timing capacitor, C, across Pin 5and 6, and by the timing resistor, R, connected to either Pin 7 or 8. The frequency is given as: f0 = 1 / RC Hzand can be adjusted by varying either R or C. The recommended values of R, for a givenfrequency rangeSine wave generation: XR-2206 can be used as a sine wave generator. The necessary circuitdiagram is shown below. The Potentiometer R1 at pin 7 provides the required frequency tuning.The pin 3 is biased such that output DC level is approximately V+/2.For sine wave generation, the switch S1 is closed. The pins 15 and 16 are used for additionaladjustments to get low sine wave distortion.The Resistance R1 and R2 can be used to reduce the distortion to about the resistance R2 providesthe fine adjustment for the wave form symmetry.The frequency of the sine wave is f = 1/RC
    • 12 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comTriangular wave generation: The same circuit used for sine wave can be used for triangularwave by opening the switch S1. The amplitude of the triangular wave is twice to that of sinewave output obtained with switch S1 closed.The amplitude is controlled by resistance R3.Aapplications of XR-2206 :S Wave form generation. Sweep generator. FSK generator. Phase locked loop. Voltage to Frequency conversion. Tone generation.
    • 13 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comPhase Locked Loop (565):A phase locked loop is basically a closed loop system designed to lock the O/P frequency andphase to the frequency and phase of an input signal.The PLL can be used as a modulator, demodulators, oscillator, synthesizer, clock signalrecovery circuit and so on. It was introduced by a French Scientist de Bellescize in 1832 as a technique forstabilizing an oscillator frequency .The first PLLs were analog but, since the 70’s integratedcircuits have been available to perform the same function on an IC . These are called digitalPLLs. The Phase Locked Loop acts similar to op-amp in the frequency domain. The op amp hastwo voltage inputs inverting and non-inverting. The inverting input is normally used for feedback from the output. Similarly, the PLL has two inputs. One is the input signal and the other isthe feed back signal from VCO. The op amp changes its output voltage depending on thedifference in voltage between the two input voltages. Similarly, the PLL changes its output phaseand frequency depending on the frequency difference between two input signals.There are basically there types of PLLs. (i) The linear(Analog) PLL (LPPL) (ii)The Digital PLL(DPLL) (iii). All-digital PLL (ADPLL)Block Diagram-Operation: The PLL consists of four important blocks. They are 1. Phase detector , 2. Low pass filter 3. Error Amplifier and 4. Voltage Controlled Oscillator(VCO) .All these parts are connected to form a closed-loop frequency feedback system.
    • 14 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comWorking:.When no input signal is applied to the PLL, the error voltage at the output of thephase detector is zero. The voltage Vd(t) from the LPF is also zero, which causes the VCO tooperate at a set frequency(fo) called the center frequency.Now, If an input signal is applied to the PLL, The phase detector compares the phase andfrequency of the input signal with the VCO frequency and generates an error voltageproportional to the phase and frequency difference of the input signal and VCO. The errorvoltage Ve(t) is filtered . It will remove high frequency signal (fi+f0) and allows only (fi-f0).Theerror voltage is Ve(t) filtered applied to the control input of the VCO. Vd(t) varies in a directionthat reduces the frequency difference between the VCO and signal-input frequency. When theinput frequency is sufficiently close to the VCO frequency, the closed loop nature of the PLLforces the VCO to lock in frequency with signal input . i.e when the PLL is in lock , the VCOfrequency is identical to the input signal frequency, except for a finite phase difference . Therange of frequencies over which the PLL can maintain this locked condition is known as the lockrange of the system. Once locked, PLL goes through three stages(i). Free running (ii) Capture and (iii). Locked or tracking.IC PLL 565: The IC 565 is a very widely used PLL and Its operating frequency range is 0.001Hz to 500 K Hz. PLL is available as a 14-pin DIP package and as 10-pin metal can package.
    • 15 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comThe input signals are fed to the phase detector through pins 2 and 3 in differential mode. Theinput signals can be direct-coupled provided that the dc level at these two pins is made same anddc resistances seen from pins 2 and 3 are equal. By shorting pins 4 and 5 output of VCO issupplied back to the phase detector(PD) . The output of PD is internally connected to amplifier,the output of which is available at pins 6 and 7 through a resistor of 3.6 k ( connected internally).A capacitor C connected between pins 7 and 10 forms a low-pass filter with 3.6 k resistor. Thefilter capacitor C should be large enough so as to eliminate the variations in demodulated outputand stabilize the VCO frequency. Voltage available at pin 7 is connected internally to VCO as acontrol signal. At pin 6 a reference voltage nominally equal to voltage at pin 7 is availableallowing both the differential stages to be biased. Pins 1 and 10 are supply pins.The output frequency of the VCO is given by f0= 0.25/ RTCTWhere RT and CT are external resistor and capacitors connected to pin 8 and 9. A valuebetween 2KΩ and 20KΩ is recommended for RT . The VCO free running frequency is adjustedwith RT and CT to be at the center of the input frequency range. A short circuit between pins 4and 5 connects the VCO o/p to the phase comparator so as to compare fo with input signal fs.The centre frequency of the PLL is determined by the free-running frequency of the VCO.
    • 16 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comCD 4046-PLL :This is a CMOS micro power Phase Locked Loop. It consists of a low power, linear voltagecontrolled oscillator(VCO) and two different phase comparators having a common signal inputamplifier and a common comparator input. If , necessary a 5.2V Zener diode is provided forsupply regulation. The VCO is connected either directly or through frequency dividers to thecomparator input of the phase comparators. The LPF is implemented through external parts assome components can not be integrated and also the configuration changes from application toapplication.The CD4046 is available as 16 pin IC in different packages.Features: Its power consumption is very low(~70 μw) Operating frequency range upto 1.4 MHz. Very low frequency drift 0,04% /0 C. Choices of two comparators High VCO Linearity. Zener diode provision for supply regulation. Standardized symmetrical output characteristicsBlock Diagram:The PLL 4046 consists of a linear voltage controlled oscillator and two different phasecomparators. The VCO requires one external capacitor C1 and one or two external resistors(R1or R1 &R2). The resistor R1 and capacitor C1 decides the frequency range of VCO and resistor R2enables the VCO to have a frequency offset if required. The high input impedance of the VCOsimplifies the design of LPF by permitting the designer a wide choice of resistor to capacitorratios.
    • 17 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comIn order not to load the LPF, a source follower O/P voltage is provided at pin 10. If this terminalis used, a load resistor RS of 10KΩ or more should be connected from this terminal to Vss,Otherwise it must be left open. The VCO can be connected either directly or through frequencydividers to the comparator input of the phase comparators.Logic 0 on the Inhibit input enables the VCO and the source follower while a logic 1 turns offboth to minimize stand by power consumption.Phase comparator 1 is an exclusive-OR network to maximize the lock range, the signal and thecomparator input frequencies must have 50% duty cycle. With no signal or noise on the signalinput, this phase comparator has an average output voltage equal to VDD /2. The low pass filterconnected to the output of phase comparator1 supplies the average voltage to the VCO input andcauses the VCO to oscillate at the corner frequency f0.
    • 18 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comImportant feature of this type of phase comparator is that it may lock onto input frequencies thatare close to harmonic of the VCO center frequency.Phase comparator II is an edge controlleddigital memory network. It consists of four Flip Flop stages, control gating and a three stateoutput circuit comprising P and n typedrivers having a common output node.This type of phasecomparator acts only on the positive edge of the signal and comparator inputs.Applications: 1. FM modulator and demodulator 2. Frequency synthesis and multiplication 3. Frequency discriminator 4. Voltage to frequency converter 5. Tone Decoding 6. FSK modulation 7. Signal Conditionings. LM 380 Audio Power Amplifier: It is an audio power amplifier widely used for consumerapplications. The output is short circuit proof with internal thermal limiting. In order to holdsystem cost to a minimum, gain is internally fixed at 34 Db . It is a 40 PIN, DIP chip with thefollowing featuresFeatures: Wide supply voltage range Low quiescent power drain Voltage gain fixed at 50. High peak current capabilities. Input reference to ground High input impedance Low distortion Quiescent output voltage at one half of the supply voltage Standard dual in line package.Circuit Description: The input stage of LM380 is PNP emitter follower driving a PNP differential pairwith a slave current source load.
    • 19 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The second stage is a common emitter voltage gain amplifier with a current-source load.Internal compensation is provided by the polar-splitting capacitor . This pole splitting compensation isused to preserve the wide power band width.(100KHz at 2W,8Ω). The amplifier gain is internally fixed to50 or 34dB. This is achieved by the internal feed back network. The LM 380 is internally biased with the150 KΩ resistance to ground. This enables input transducers to be direct coupled to either inverting ornon-inverting inputs of the amplifier. In most applications where the non-inverting input is used , Theinverting input is left floating.Audio Power Amplifier : The circuit shows simple audio amplifier built using the IC LM380.This amplifier requires very few external components. Although the gain of the LM380 isinternally fixed at 50, it can be changed with the use of external components. In the above
    • 20 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comcircuit , the gain is varied up to 50 with the use of the potentiometer across the two inputterminals. The wattage of IC LM380 is around 2.5 W.Applications of LM380 :It is used in intercoms, line drivers, alarms, ultrasonic drivers, TV sound system, AM/FM radio,power converters, small servo drivers etc…Data Converters : The unprecedented growth and development in digital technology has revolutionized thecomputational and processing techniques. Now a days computers are inseparable components indata-acquisition systems. So, the microprocessors (micro computers) are used not only forcomputations but also for measurement and processing of physical quantities like temperature,pressure, displacement etc. But the microprocessor which is a logic device can process onlydigital signals. The physical quantities like temperature, pressure etc., are analog quantities. So,to process the quantities using microprocessors, it is necessary to convert analog signals intoequivalent digital signals using certain circuitry. The electronic circuit which converts an analog signal into equivalent digital signal (bothin magnitude and sign) is called analog to digital converter. This is popularly known as ADC. The output of a microprocessor will be in digital form, which is not easy for the users tounderstand. So, the digital data must be again converted into analog data. The electronic circuitwhich converts the binary data into equivalent analog data is known as digital to analogconverter. More popularly known as DAC.Digital to Analog Converter : Based on the principle of working there are two types of DACs.(i) Binary weighted Resistor DAC (ii) R-2R ladder DAC(i).Weighted Resister D/A Converter : This technique is also called variable resister divider network because the resistor used for MSB is R/2N and the resistor used for LSB is R/20 in an N-bit DAC. So, it can be easily understood that for an 8-bit DAC, resister for MSB is R/27 =R/128 and the resister for LSB is R/20 =R. This means that the resister used for MSB handles a high current as compared to the LSB resister. As the resistors are chosen according to the weightage of the binary bits, this technique is called binary weighted resister technique.
    • 21 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The circuit diagram for weighted resistor N-bit DAC is shown below.Here digitally controlled electronic switches are used. These switches can produce a current Icorresponding to logic 1 at the MSB, I/2 corresponding to the logic 1 at the next lower bit andI/22 for logic 1 at the next lower bit and so on… and I/2N-1 for logic 1 at the LSB. The totalcurrent thus produced will be propositional to the digital input.The output current is converted into corresponding voltage by using an op-amp circuit. This willgive us voltage output propositional to the digital input. Suppose V(0) and V(1) are the voltagesapplied to the resistor network for 0 and 1 respectively, the output voltage of DAC is given by Here RF is the feedback resistance. As the output changes in only one direction, this DAC is a unipolar DAC.
    • 22 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comLimitations :1.In this method , each resistor required in the network is of different value, like R/128, R/64.R/32, R/16………R .So ,we have to choose from a wide range of values, which is practicallyand economically not feasible many times. This will also affect the accuracy and stability of thecircuit.2. When the number of input bits is large, the resistor used for LSB will be very high value,which may sometimes be nearly equal to input resistance of the amplifier. This will affect theresult.3.If each higher bit resistor is not exactly half of the previous resistor value, the next step sizewill be change. So, to overcome all these limitations, we use R-2R binary ladder network techniquewhich uses resistors having only two values .(ii).R-2R Ladder Network D/A Converter :This is a better type of D/A converter which eliminates the drawbacks suffered by weightedresister D/A converter. It is also a resistive network, whose output voltage is properly weightedsum of digital inputs. The salient features of this converter are It is constructed using the resistors of two values (R and 2R) only. These binary ladder networks are available on monolithic integrated chips thus giving a high degree of precision. The only disadvantage is that one additional resistor is required for each bit as compared to the weighted resistor network, where only one resistor is needed for each bit.Functioning: The circuit diagram of a 4-bit D/A converter using R-2R ladder network is shown in fig1.below. The binary inputs are applied by switches b0 through b3 and the output is proportional tothe binary inputs. The binary inputs can be either high (+5V) or low(0V). Let us assume that theMSB switch b3 is connected to +5V and other switches are connected to ground. LetR=RL=10KΩ and RF =2R.
    • 23 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comApplying Thevenin’s theorem to the left side of the switch b3, the equivalent Thevenin’sresistance is RTh = [ {[(2R║2R +R) ║2R] ║2R]+R}║2R]+R RTh = 2RThe resultant circuit is as shown in fig.2 below. In the circuit, the non-inverting input is at virtualground .So V2 = 0 , and the current through RTh is zero. However current through the resistor 2Rconnected to +5V is I = 5V/20 KΩ = 0.25mA.The same current flows through the feedback resistor RF. So, the output voltage V0= RF .I
    • 24 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com V0 = - (20KΩ) (0.25mA) = - 5VUsing the same theory the output voltage corresponding to all the possible combinations ofbinary input can be determined. The maximum or full scale output of -9.375 V is obtained whenall the binary inputs are high.The output voltage equation can be written as V0= - RF (b3/2R + b2/4R+ b1/8R+b0 /16R)where each of the bits b3 , b2 ,b1 and b0 may be either +5V or 0 V.The only drawback of this R-2R ladder circuit is, as the number of binary inputs increasesbeyond 4, the circuit becomes complex and accuracy decreases.Analog to Digital Converter: The Analog to Digital conversion is a quantizing process, in which ananalog signal is converted in to its equivalent binary (digital) value. This process is opposite toD/A conversion process.Based on the conversion technique the ADCs are classified into two categories. The firsttechnique involves comparing a given analog signal with the internally generated equivalentsignal. This category includes, Successive approximation Counter type and Flash type ADCsThe second type involves changing an analog signal into time or frequency and comparing thesenew parameters to known values. This group includes (a) Dual slope ADCs. and (ii) Voltage to frequency converters.
    • 25 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The successive approximation and Flash ADCs are faster but less accurate than the integrator and voltage to frequency type converters. Also, the flash type are expensive and also difficult to design, for high accuracy.Principle of Successive Approximation : It is the most popular method of A/D conversion. Ithas also excellent compromise between accuracy and speed. Here, the principle is ,an unknownvoltage Vin is compared with the fraction of the reference voltage (Vr). For n-bit digital output,comparison is made for n times with different fractions of Vr. The value of the particular bit isset to 1, if Vin is greater than the set fraction of Vr. The value of the particular bit is set to 0 , ifVin is less than the set fraction of Vr.Successive Approximation A/D Converter: The heart of the circuit is a successiveapproximation register(SAR). If the output of ADC is to be 8-bit, we use an 8-bit successiveApproximation Register . The output of SAR is applied to an 8-bit D/A converter. The analogoutput of the D/A converter is given to the inverting terminal of the comparator. A referencevoltage is applied to the non-inverting terminal. An 8-bit latch is used to store the digital outputafter complete conversion. As shown in fig.below.
    • 26 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comThe operation of the circuit is as follows : At the start of conversion cycle, the SAR is reset byholding the start signal(S) high. On the first clock pulse Low-to-High transition, the mostsignificant bit Q7 of the SAR is Set(HIGH). The D/A converter give out an analog equivalent toQ7 bit, which is compared with the analog input Vi . If the DAC o/p V0 is greater than Vi, thecomparator output is low and the SAR will clear (Reset) its MSB Q7. On other hand, if the D/Aoutput is less than Vin, the SAR will keep the MSB Q7 set. On the next clock pulse, Low to Hightransition, the SAR will set the next MSB Q6. Depending on the output of the comparator, theSAR will either set or reset the bit Q6.This process is continued until the SAR completes all the 8-bits. At the end of the LSB Q0, theSAR sends out a conversion complete signal (High) to indicate that the parallel output linescontain valid digital data. This conversion complete signal enables an 8-bit latch and the digitaldata appear at the output of the latch. The entire process is completed only in 8-clock pulses.To repeat this process continuously the conversion complete signal is connected to the start ofconversion input. The advantage of successive approximation A/D converter is its high speedand good resolution.Dual slope ADC :Dual slope conversion is an indirect method for A/D conversion where an analog voltage andreference voltage are converted into time periods by an integrator and then measured by acounter. The speed of conversion is slow,but the accuracy is high.The block diagram of the Dualslope ADC is shown below. A dual slope converter consists of an integrator (Ramp generator), comparator,binary counter, reference voltage. and a control Flip-Flop. The ramp generator input is switchedbetween the analog input voltages Vi and negative reference voltage, -VREF . The analog switch iscontrolled by the MSB of the counter. When MSB is logic 0, the voltage being measured isconnected to the ramp generator input. Similarly when MSB is logic 1, the negative referencevoltage is connected to the ramp generator.
    • 27 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comAt time t=0, analog switch’S’ is connected to the analog input voltage Vi , So that the analoginput voltage is integrated by the op-amp integrator.The output voltage of the integrator is given by Voi = -1/RC ∫ Vi dt. = - [Vi / RC].tHere RC is the integrator time constant and Vi is assumed constant over the integration timeperiod. This makes the output of the comparator Vc ,to go High.Under these conditions ,theAND gate is enabled and the clock pulses are counted by the counter. Since the circuit uses an n-stage ripple counter ,it resets to zero after counting 2N pulses. The analog voltage is integratedfor a fixed number of 2N clock pulses after which the counter resets to zero.s
    • 28 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com If the clock period is Tc , the integration occurs for a time T1 = 2NTcand the output is a ramp going downwards. At the end of the time interval T1 ,the counter resetsand the reference voltage –Vref is connected to the integrator input.The integrator produces aramp voltage in the positive going direction .The counter continuous to count as long as Vo<0.When Vo goes positive at t=T2 ,then the comparator outputgoes low and disables the ANDgate. Then the counter stops counting. The time interval T1 = 2NxTime period of the clock pulse. = 2N.TcWhen the integrator is fed with negative reference voltage(-Vref) Vo = -(Vi/RC) T1 +Vref/RC (t-T1) Since the voltage Vo= 0 at t=T2 0 = -(Vi/RC) +Vref/RC (T2-T1) Therefore (T2 –T1) = (Vi/Vref )T1 = Vi/Vref.2N.TcIf n is the count recorded by the counter at t=T2, (T2-T1) = nTc = Vi/Vref.2N.Tc Or n = (Vi /Vref).2N
    • 29 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comSo,the output of the counter is proportional to Vi. If Vref is is constant , Vi α nThe advantages of dual slope ADC are 1. It is low cost technique 2. it is a highly accurate 3. It is immune to variations In R and C due to temperature the only disadvantage is it is relatively slow.FLASH CONVERTER : It is the fastest ADC when compared to the other techniques. Theseare also known as parallel ADCs . Flash ADCs are suitable for very large bandwidthapplications. Typical examples include data acquisition, satellite communication, radarprocessing, sampling oscilloscopes, and high-density disk drives. But the disadvantages are ,these converters consume considerable power, have relatively low resolution, and can be quiteexpensive. Flash ADCs are made by cascading high-speed comparators. For an N-bit converter,the circuit employs 2N-1 comparators. A resistive-divider with 2N resistors provides the referencevoltage. Each comparator produces a 1 when its analog input voltage is higher than thereference voltage applied to it. Otherwise, the comparator output is 0.The analog input and the corresponding digital outputs are given in the table. S.No Analog input(Volts) Digital output D2 D1 D0 1 0—0.5 0 0 0 2 0.5—1.5 0 0 1 3 1.5—2.5 0 1 0 4 2.5—3.5 0 1 1 5 3.5—4.5 1 0 0 6 4.5—5.5 1 0 1 7 5.5—6.5 1 1 0 8 >6.5 1 1 1
    • 30 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comLet us consider a 3-bit flash converter. It require 23-1= 7 comparators as shown in the diagram.The analog input Vi is applied to all the non-inverting inputs of the comparators as shown in thediagram. The other input to each comparator is a Dc from a regulated supply.The comparatorsare op-amp circuits without feedback. For a given analog input voltage ,all the comparatorsbelow a certain voltage in the ladder, will have one particular state and those above that pointwill have the opposite state. This pattern of states is applied to a decoder circuit which producesa digital output. For example when input voltage is 5V, the outputs of comparators 1 to 5 wouldgo high and 6 and 7 go low. So, the corresponding digital output would be 101.
    • 31 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comThe conversion time of the flash converter is limited only by the response times of comparatorsand logic gates. The cost of the Flash converters increases as the resolution is increased.Sample and Hold circuits - LF 398 :Need of sampling and Hold circuit: The signal that is applied to an A/D Converter should bemaintained constant during the conversion period. The sampled signal must be maintained atconstant level, until the earlier sample is converted into digital quantity. Otherwise the finalresult will be erroneous. So, we need a circuit which samples the input analog signal and holds asample at the sample level till the earlier sample is completely converted. This type of circuit isknown as sample and hold circuit.Principle of working : In S/H circuits, a JFET is used as a switch. During the sampling time theJFET is switched ON and the holding capacitor charges upto the level of the analog inputvoltage. At the end of this short sampling period the JFET is switched off. This isolates theholding capacitor CH and hence output voltage will remain constant at the value of the inputvoltage at the end of sampling time. However due to leakage in the capacitor there will be asmall voltage drop. To avoid this voltage follower circuits are used. Sampled output voltage = Input voltage x(1+ RF/Ri )LF 398 IC :
    • 32 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comThe LF398 is a monolithic sample-and-hold circuit which utilizes high-voltage ion-implant JFETtechnology to obtain ultra-high DC accuracy with fast acquisition of signal and low droop rate.Operating as a unity gain follower, DC gain accuracy is 0.002% typical and acquisition time is aslow as 6 ms to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offsetdrift. The wide bandwidth allows theLF398 to be included inside the feedback loop of 1 MHz opamps without having stability problems. Input impedance of 1010 Ω allows high sourceimpedances to be used without degrading accuracy. The salient features of this IC are givenbelow.Features: (a) Can operate from ±5V to ±18V (b) Acquisition time is less than 10μs. (c) It has TTL, PMOS, and CMOS compatibility logic input. (d) Low input offset (e) Wide band width (f) Input chrematistics do not change during hold mode (g) Low output noise in hold mode. (h) High supply rejection ratio in sample or hold.Circuit Details: A bipolar input stage is used to achieve low offset voltage and wide band width.In the output amplifier P- channel junction FET s are combined with bipolar devices to give verylow droop rate. The droop rate is the rate at which the output of the S/H circuit decreases. Anexternal capacitor, known as hold capacitor is used with LF 398 to hold the voltage applied to it .A 1μF capacitor can give a droop rate of 5mv/min. JFETs have much lower noise than MOSdevices. The schematic of LF 398 is shown below.
    • 33 Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comCH is a hold capacitor connected externally at the pin6. A logic pulse of 5V is applied at the pin 8The width of the pulse should be equal to acquisition time which depends on hold capacitor.When the logic becomes high, the input voltage is applied to the hold capacitor. This capacitor ischarged to the instantaneous value of the input voltage. The input voltage is switched off whenthe logic goes low. The hold capacitor is isolated from any load through an op amp included inS/H circuit for this purpose. So, the hold capacitor holds the instantaneous value of the inputvoltage applied it.NOTE: The hold capacitor should be made of dielectrics having low hysteresis such aspolystyrene , polypropylene and Teflon etc…The acquisition time mainly depends on the valueof hold capacitor.