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Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
Interfacing of data converters & io devices
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Interfacing of data converters & io devices

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Its the class notes meant for especially for M.Sc electronics students of SKU & RU and also for ECE students

Its the class notes meant for especially for M.Sc electronics students of SKU & RU and also for ECE students

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  • 1. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Interfacing of Data Converters and I/O DevicesIntroduction : In any microprocessor /microcontroller system, peripherals can not bedirectly connected to the processor with out using cetain logic devices. In bus-oriented systemswe need various logic devices like buffers,drivers,encoders ,decoders ,multiplexers and de-multiplexers etc..Especially ,tri-state logic devices are very much required for the properfunctioning of multiplexed bus sytems. For example in a microprocessor or microcontroller wefind the data and address busses are multiplexed . So , there is a need of these logic devices inevery microprocessor based system.Tri-state Devices : A logic device which has three states, logic 0,logic 1 and and highimpedance state is known as a tri-state device. The term tri-state is a trade mark of ―NationalSemiconductors‖ and is used to represent three logic states. The third state is also calledEnable.When this line is activated the tristate device functions same way as ordinary logicdevice. Similarly when the third line is disabled the logic device goes to the high impedancestate-as if it were disconnected from the system.In microprocessor or microcontroller based systems ,peripherals are connected in parallelbetween the address bus and data bus. But they can’t load the system because of these tristatedevices .The microprocessor communicates with one device at a time by enabling the tri-stateline of that interfacing device. Tri-state logic prevents a bus conflict where one device is drivinga signal to 1 and another device is driving it to 0 at the same time,which may generate highcurrent through wires.Buffer : A buffer is a logic circuit that increases or amplifies or boosts the current or power of alogic circuit or device. As it increases the driving capability of a circuit it is also known as aDriver.When the output current of a device is insufficient to drive another device ,a buffer isused to increase the current rating.Tri-State Buffer : A tri-state buffer has a third line called Enable in addition to In and Out linesThere are two types of buffers (i) Unidirectional Buffer and (ii) Bi-directional Buffer
  • 2. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comUnidirectional Buffers: In cases where the receiver current requirements exceed the driver’scapability, we must use buffers/drivers such as the 74LS244 is used for unidirectional addressbuses. This device transfers the data only in one direction,by increasing the driving capability ofthe Bus.For Ex: 74LS244 is a unidirectional Octal buffer. The 74LS244has simply 8 tri-statebuffers in a single chip. These buffers are divided into two groups. The enabling and disablingof these groups are controlled by 1G and 2G lines, until these lines are enabled ,the output of thedrivers remains in the high impedance state. It is also known as line driver or line receiver.The address bus is unidirectional buffer,74LS244 is used to buffer higher order address bus. Itconsists of 8-non inverting buffers with try state outputs. Each one can sink 24 mA and source15 mA of current.Bi-directional Buffer : This bidirectional buffer is used to increase the driving capability of thedata bus. It consists 16 non-inverting buffers, eight for each direction,with tri-state output. Thedirection of data flow is controlled by the pin DIR. When DIR is high, the data flow from the busA to the bus B ,when it is low data flows from B to A. The active low enable signal and the DIRsignal are ANDed to activate the bus lines. Each buffer in device can sink 24 mA and 15 mAsource of current.The IC 74LS245 is a bidirectional buffer, which is also called Octal bus transreceivers.Thedirection of the data flow is controlled by the pin DIR .When DIR is high ,the data flows from
  • 3. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comBus A to Bus B and when it is low data flows from B to A.The active low enable signal and theDIR signal are ANDed to activitate the bus lines.Each buffer in this chip can sink a current of24mA and source a current of 15mA.The logic diagram and the functionl table of LS74245 isshown below.This bidirectional buffer is widely used with data bus in the microprocessor/ microcontrollerbased systems.Decoder : A decoder is mainly used in interfacing I/O peripherals and memory elements to themicroprocessor or microcontroller systems.The decoder is used to decode an address bus toidentify an output device. Decoders are also built internal to a memory chip to identify individualmemory registers.The decoder is a logic device that identifies each combination of the signals present at its input.Ifthe input to a decoder has two binary lines ,the decoder will have four output lines. Commonlyavailable decoders are 3-to-8 ,4- to- 16 and 4-to-10(to decode BCD input).Also some decodershave active low output lines as well as Enable lines.74LS138 is a 3 –to-8 decoder and some times it is also called 1-out-of 8 binary decoder ordemultiplexer. The 74LS138 decodes one-of-eight lines, based upon the conditions at the threebinary select inputs and the three enable inputs. Two active-low and one active-high enableinputs reduce the need for external gates or inverters when expanding.
  • 4. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comTo enable the device to function as decoder all the three enable lines should be activated.Encoder : The encoder is a logic circuit that provides a code (Binary or BCD) at the output forevery input signal applied to it. This is the reverse process of the Decoding.Normally digitalencoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data inputlines. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types thatinclude 4-to-2, 8-to-3 and 16-to-4 line configurations. The output lines of a digital encodergenerate the binary equivalent of the input line whose value is equal to "1" and are available toencode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code.
  • 5. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comOne of the disadvantages of the encoders is that they can generate the wrong output code whenthere is more than one input present at logic level "1". For example, if we make inputs D1 andD2 HIGH at logic "1" both at the same time, the resulting output is neither at "01" or at "10" butwill be at "11" which is an output binary number that is different to the actual input present.Also, an output code of all logic "0"s can be generated when all of its inputs are at "0" OR wheninput D0 is equal to one.A simple method to overcome this problem is to "Prioritize" the level of each input pin and ifthere was more than one input at logic level "1" the actual output code would only correspond tothe input with the highest designated priority. Then this type of digital encoder is knowncommonly as a Priority Encoder or P-encoder .The TTL 74LS148 is an 8-to-3 bit priority encoderwhich has eight active LOW (logic "0") inputs andprovides a 3-bit code of the highest ranked input atits output. Priority encoders output the highestorder input first for example, if input lines "D2","D3" and "D5" are applied simultaneously theoutput code would be for input "D5" ("101") as thishas the highest order out of the 3 inputs. Once input"D5" had been removed the next highest outputcode would be for input "D3" ("011"), and so on.The Encoder chip has five output lines.Three areencoding lines and two are output enable indicators.The output lines GS and EO can be used to encode more than eight inputs by cascading thesedevices.When the encoder is enabled and two or more input signals are activated simultaneously,it ignores the low priority inputs and encodes the highest priority inputs.Encoders are commonly used with keyboards .For each key pressed the corresponding binarycode is Placed on the data bus.Latches-DFlip-Flops : The simplest form of a Latch is a D-flip-flop.It is also called atransparent latch. The 74LS75 is an example for D flip-flop.The output changes according to
  • 6. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.cominput ,only when the Enable pin is High. The 7475 is a positive edge triggered flip-flopwhich isshown below..A typical example for transparent Latch is 74LS373 chip. When the microprocessor sends theoutput data , the data is available on the data bus only for few micro seconds, there after a Latchis used to hold the data for display.The logic diagram of the IC 74LS373 is shown below.The IC 74LS 373 is an octal buffer latch which consists of eight D latches with tri-state buffersand require two input signals. Enable (G) and output control(OC) The enable is an active highsignal connected to the clock input of the flip-flop. When this signal goes low,data is latchedfrom the data bus.the output control signal is active low and it enables the tri-state buffer tooutput data to the display device.
  • 7. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comMultiplexer (Data Selector)A multiplexer selects one out of N inputs and makes it available at the output terminal.So, aMultiplexer has N-inputs and one output only.This is also known as Data selector or simplyMUX.For Ex: 74LS151 is a digital multiplexer with 8-input lines, three select lines and onestrobe line and one output. The logical diagram is shown below.In the diagram A,B and C are the select lines.Based on the value on select lines thecorresponding input is selected.For 000 input D0 is selected. Similarly for 111 input D7 isselected..The strobe line enables the output.When it is High ,the output is enabled.Multiplexerare used to give multiple inputs to a processor or Microcontroller.De Multiplexer : A De-Multiplexer accepts a single input and sends it to 1 out of N outputlines.,which is selected by the select lines.It performs the reverse operation of a Mux.In a demux,the input data can be made available at any one of the output lines. This de mux is also known asDecoder.Ex: The chip 74LS 154 is a 1 to 16 lines de-multiplexer and 4 to 16 line decoder. Thebasic
  • 8. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comdifference between the two is that the de-Mux has Data input where as the decoder has no Datainput.Interfacing a Octal Driver and a D-Latch to The Microprocessor :Generally the system Bus of the Microprocessors can source only 400 microamperes and sinkabout 2 mA of current.So, the bus can drive only one TTL load.Hence it is always necessary toincrease the driving capability of the busses by using the Drivers or Buffers.For this reason inany microprocessor or microcontroller based systems the IC 74LS244 is interfaced with the
  • 9. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comhigher order address bus to improve its driving capacity as shown in the diagram.Similarly ,in microprocessor /microcontrollers the address/data bus lines are multiplexed.Thelatching of lower order address bus is done by using the ALE signal from the microprocessor.Fordemultiplexing the bus , the IC 74LS373 which is transparent 8-bit Latch is used. This ICconsists of 8 D flip-flops.The ALE signal is connected to clock through the Enable pin .So,when this ALE is high,the clock will allow any data at its input to the output.[This is thereason for calling it as transparent Latch]. So , 74LS373 8-bit (octal) D latch latches the addressbits A0-A7 when ALE is HIGH, and keeps them available when ALE is LOW.Interfacing a bi-directional bus Driver and a Decoder to the Microprocessor :To work effectively with data bus and control bus of the microprocessor .a bi-directional busdriver and one 3-to-8 decoder are required.
  • 10. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comBi-directional bus transceivers are required on the data bus, since data can travel not only fromthe CPU to the peripheral device, but also in the opposite direction. Transceivers are required atboth the CPU and peripheral device ends.So, to increase the driving capacity of the Data bus ,theIC 74LS245 octal bidirectional bus driver is interfaced to the microprocessor as shown above.The IC 74LS245 is a bidirectional buffer, which is also called Octal bus transreceivers.Thedirection of the data flow is controlled by the pin DIR .When DIR is high ,the data flows fromBus A to Bus B and when it is low data flows from B to A.The active low enable signal and theDIR signal are ANDed to activitate the bus lines.Each buffer in this chip can sink a current of24mA and source a current of 15Ma.Also to generate the control signals like I/O read , I/O write ,Memory Read and Memory writethe chip 74LS138 a 3- to -8 decoder is also interfaced to the microprocessor. This decoder chipwill provide the control signals as shown in the diagram.For example, the RD signal has togenerate two different read signals,one for memory and the other for input.Similarly two separate
  • 11. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comwrite signals must be generated.These four signals are generated by the Decoder by combiningthe RD,WR and IO/M signals .When the signal IO/M goes low ,the control signals for memoryoperations are generated. Similarly when IO/M goes High , the signals corresponding to I/O aregenerated.Interfacing data convertors (DAC and ADC) :Introduction : Data converter is a device which converts one form of data into its anotherequivalent form .There are two types of data converters .They arei. Analog to Digital Converter-(ADC)ii. Digital to Analog converter-(DAC)These converters are very important elements in every data acquisition system .Because thenaturally available data is always analog and all the processing devices like Microprocessors orMicrocontrollers or Digital signal processors etc.. are digital devices. So,this analog data must befirst converted into equivalent digital data before it is applied to the Microprocessor orMicrocontroller. Similarly the output of the processors is always in digital form and it will notbe convenient for common man. So,again this digital data must be converted into equivalentanalog data using a DAC. Hence without the use of data converters it is not possible to designany Data acquisition system.INTERFACING DAC - 8051 MICROCONTROLLERThe DAC 0800 is a simple monolithic 8-bit Digital to Analog converter. It has fast settling time of 100ns.It can be directly interfaced to TTL, CMOS, PMOS and othersdevices. It operates at 4.5V to +18V supply.The number of data bit inputs decides the resolution of the DAC since the number of analog outputlevels is equal to 2″, where n is the number of data bit inputs. Therefore, an 8-input DAC such as theDAC0808 provides 256 discrete voltage (or current) levels of output.The interfacing circuit is shown below. The port 1(8 bits of the microcontroller) is connected tothe input data lines of DAC-0800 and the input is applied through this port1.The referencecurrent is determined by the resistor R1 and the reference voltage Vref. The resistor R2 isgenerally equal to R1 to match the input impedance of reference source. The output is normallyin current form. So, to convert this current into equivalent voltage ,an op-amp circuit is used at
  • 12. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comthe output. This is a voltage to current converter and the output of the op-amp can be measuredeither with a multimeter or using a cathode ray oscilloscope. The output current Io is calculated as follows: Io = Vref / R1[Ao/2 + A1/4 + A2/8 + … +A7/256]A simple assembly language Program is given below. MOV A, #DATA* ; (A) = #Data START : MOV 90H, A ; (port -1) = (A) INC A LJMP START ; RepeatInterfacing of ADC 0804 to 8051 Microcontroller :ADC 0804 is a single channel analog to digital converter It is a single channel ADC. i.e. it cantake only one analog signal and convert it into equivalent digital value. ADC 0804 has 8 bitresolution. The higher resolution ADC gives smaller step size. Step size is smallest change that
  • 13. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comcan be measured by an ADC. For an ADC with resolution of 8 bits, the step size is 19.53mV(5V/255). The time taken by the ADC to convert analog data into digital form depends on thefrequency of clock source. The conversion time of ADC 0804 is around 110us. To use theinternal clock a capacitor and resistor are used as shown in the circuit. The input to the ADC isgiven from a regulated power supply and a 10K potentiometer.The 8051 Microcontroller is used to provide the control signals to the ADC. The pins P1.1, P1.0and P1.2 are connected to the pin WR, RD and INTR of the ADC respectively. CS(chip select)pin of ADC is directly connected to ground. When the input voltage from the preset is varied theoutput of ADC also varies.From the circuit it is clear that the ADC interfaced directly to the microcontroller. The Port1 isused as an input port which receives the digital data from the ADC. Port pins P2.5 and P2.6 areused for SOC and ALE operation (RD and WR).When the conversion is over the ADC will sendan interrupt signal to the microcontroller through the pin P2.7 .Now the Microcontroller receivesdigital data through the Port1.This data after conversion to decimal data is displayed on the LCDmodule.
  • 14. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comThe assembly language program for ADC is given below . MOV P1 , 0FF H ; Make the port1 high and configure port1 as Input portBACK: CLR P2.6 ; Generation of SOC pulse SETB P2.5 ;LOOP JB P2.7 , LOOP ; Wait for conversion, Is conversion over? CLR P2.5 ; Enable Read the digital data MOV A ,P1 ; Read digital data through Port1 SETB P2.5 ; Disable read after read operation CALL DISPLAY ; Display the data on LCD module SJMP BACK ; Continue the conversion processDirect Memory Access (DMA) Data Transfer :When large amount of data is to be transferred between microprocessor and I/O device it is avery time consuming operation and the precious time of CPU is wasted. If the I/O port candirectly access memory for data transfer, without CPU intervention, that will be more efficient.So, in any microprocessor system, if the data transfer takes place without the intervention of theCPU, that method is known as Direct Memory Access data transfer technique (DMA). The data transfer between a floppy disk or CD ROM and a R/W memory in a system isan example for DMA data transfer. To perform this DMA transfer in microprocessor basedsystems two signals HOLD and HLDA (Hold Acknowledge) are used. An I/O device whichwish to transfer data using DMA scheme, sends the HOLD signal to the CPU. On receiving theHOLD signal from an I/O device, the CPU sends a hold acknowledge signal (HLDA) to the I/Odevice to indicate that it has received the HOLD request and it will giveup the buses in the nextmachine cycle. The I/O device takes over the control of buses and directly transfer data to thememory or reads data from the memory. There are two types of DMA schemes. They are
  • 15. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com a) Burst mode DMA b) Cycle stealing DMABurst Mode DMA This method is used when a large data block is to be transferred between a I/O device andmain memory. In each DMA cycle one byte will be transferred and the DMA controller gives upcontrol of system buses only after all the data has been transferred. The DMA controllerinterrupts the microprocessor and HOLD request is withdrawn. This technique was widely used by magnetic disk drives. In case of magnetic disks datatransfer can not be stopped or slowed down without loss of data. Hence burst mode datatransfer scheme is useful.Cycle Stealing DMA This method is used when the I/O device is relatively slow. After a DMA cycle whichresults in a byte of data transfer, the I/O device withdraws the DMA request. So, the DMAcontroller withdraws the Hold request by making it low. So, the CPU comes out of HOLD modeand continues to execute the main program. After some time when the I/O device is again ready,it once again activates the data request I/P of DMA controller. So, DMA again activates theHOLD pin and waits for HLDA. Now the data transfer is performed again. In this way thecomplete data is transferred. As the data transfer occurs during certain cycles of CPU, it is calledcycle stealing DMA.DMA Controller - Intel 8257 : Intel 8257 is a programmable, 4-channel direct memoryaccess controller i.e., four peripheral devices can request data transfer at any instant. The requestpriorities are decided internally. Each channel has two signals, DRQ (DMA Request) and (DMAacknowledge). Each channel has two 16 bit registers. One for the memory address where thedata transfer should being and the second for a 14-bit count. There are also two 8-bit registersone is the mode set register and the other is status register. It can operate both in slave andmaster mode. It is a totally TTL compatible chip.Interfacing of 8257 to Microprocessor- 8086 : Interfacing of DMA controller to themicroprocessor is shown below.
  • 16. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comTo interface the DMA controller chip to any microprocessor or microcontroller, first the addressdata bus must be demultiplexed and the control lines must be generated and the drivingcapability of the data bus and the address busses must be increased using suitable logic ICs. TheIC 74LS244 octal buffer is used to increase the driving capability of the address lines A 16-A19and the IC 74LS373 is a latch which demultiplexes the AD7-AD0 bus in to lower order addressbus and data bus. When the ALE pin is high it generates the address lines and when ALE is lowit generates the data bus .The address bus can source only about 400 uA of current only.So,toincrease the driving capability of the address lines A8-A15 the chip 74LS373 buffer is used. TheDecoder 74LS138 which is a 3 to 8 decoder will generate the control signals to read or writethe I/O or memory devices .To increase the driving capability of the data bus a bidirectional octalbus trans-receiver 74LS245 can also be used in the circuit .
  • 17. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comSERIAL DATA TRANSFER: Data transfer between two electronic devices (Ex Between amicroprocessor and computer or a microcontroller or a peripheral device) is generally occursin two ways(i).Serial data Transfer and(ii).Parallel data TransferSerial data transfer uses only one or two data lines to transfer data and is generally used for longdistance communication. In serial communication the data is sent as one bit at a time in a timedsequence on a single wire. Serial transfer takes place in two methods, Asynchronous dataTransfer and Synchronous data Transfer.Asynchronous data transfer allows data to be transmitted without the sender having to send aclock signal to the receiver. Instead, special bits will be added to each word in order tosynchronize the sending and receiving of the data. When a word is given to the UART forAsynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each wordthat is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about tobe sent, and to force the clock in the receiver into synchronization with the clock in thetransmitter.
  • 18. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Serial Data transferAfter the Start Bit, the individual bits of the word of data are sent .Here each bit in the word istransmitted for exactly the same amount of time as all of the other bits. When the entire dataword has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Paritybit may be used by the receiver to perform simple error checking. Then at least one Stop Bit issent by the transmitter. If the Stop Bit does not appear when it is supposed to, the UARTconsiders the entire word to be corrupted and will report a Framing Error.Baud rate is a measurement of transmission speed in asynchronous communication, it representsthe number of bits/sec that are actually being sent over the serial link. The Baud count includesthe overhead bits Start, Stop and Parity that are generated by the sending UART and removed bythe receiving UART.In the Synchronous data transfer method the receiver knows when to ―read‖ the next bitcoming from the sender. This is achieved by sharing a clock between sender and receiver. Inmost forms of serial Synchronous communication, if there is no data available at a given time totransmit, a fill character will be sent instead so that data is always being transmitted.Synchronous communication is usually more efficient because only data bits are transmittedbetween sender and receiver , however it will be more costly because extra wiring and controlcircuits are required to share a clock signal between the sender and receiver.Devices that use serial cables for their communication are divided into two categories.1. DTE (Data Terminal Equipment). Examples of DTE are computers, printers & terminals.2. DCE (Data Communication Equipment). Example of DCE is modems.Parallel Data Transfer :Parallel communication uses multiple wires (bus) running parallel to each other, and cantransmit data on all the wires simultaneously. i.e all the bits of the byte are transmitted at a time.So, speed of the parallel data transfer is extremely high compared to serial data transfer. An 8-bitparallel data transfer is 8-times faster than serial data transfer. Hence with in the computer alldata transfer is mainly based on Parallel data transfer. But only limitation is due to the high cost,this method is limited to only short distance communications.
  • 19. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com S.No Serial Communication Parallel Communication 1 Data is transmitted bit after the bit in a Data is transmitted simultaneously single line through group of lines(Bus) 2 Data congestion takes place No, Data congestion 3 Low speed transmission High speed transmission 4 Implementation of serial links is not an Parallel data links are easily easy task. implemented in hardware 5. In terms of transmission channel costs It is more expensive such as data bus cable length, data bus buffers, interface connectors, it is less expensive. 6 No , crosstalk problem Crosstalk creates interference between the parallel lines. 7 No effect of inter symbol interference and Parallel ports suffer extremely from noise inter-symbol interference (ISI) and noise, and therefore the data can be corrupted over long distances. 8 The bandwidth of serial wires is much The bandwidth of parallel wires is much higher. lower. 9 Serial interface is more flexible to Parallel data transfer mechanism rely on upgrade , without changing the hardware hardware resources and hence not flexible to upgrade. 10 Serial communication work effectively Parallel buses are hard to run at high even at high frequencies. frequencies.Memory and I/O Interfacing :(i) Memory interfacing : Memory is an important and inseparable part of any microprocessorsystem. During the execution of a program, the microprocessor will be frequently accerssing thismemory either for instruction codes (ROM) or data (RAM). In order to communicate withmemory, an interface is necessary between RAM and ROM memories, the address bus, the databus and the control bus from the microprocessor.
  • 20. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com The address bus interface is necessary in order to send the address of the memorylocation that is to be read or written to the memory. The data bus interface is required in order to send the data from memory to themicroprocessor. The control bus interface is necessary to enable the memory chips, so that the memorychips knows whether the address on the address bus is a memory read or memory writeoperation. So, the basic functions of memory interfacing are: a) To identify the memory register using required number of address lines. b) To decode the remaining address lines of the address bus to generate chip select signal and c) Generate control signals and by combining RD and WR signals with IO /M and use them to enable appropriate buffers. The general interfacing circuit of microprocessor with RAM and ROM is shown in Fig below. Both RAM and ROM have an interface with the address bus, the data bus and control bus. The address decoder determines which memory chip is to be enabled, based upon the memory address that comes over the address bus. In most microprocessor systems, the ROM address are the lower bits in the address map and the RAM addresses are the higher ones.
  • 21. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comInterfacing of RAM and EPROM to 8086 Microprocessor :Let us assume that we have to interface a RAM and one EPROM (2764) to the 8086microprocessor .The important ICs required are one Decoder which decodes the addresses andone latch/ buffer as shown in the diagram. A Latch 74LS373 is used to demultiplex the addressand data lines.The Decoder will generate the necessary control signals for Memory read andmemory write operation. The memory capacity decides the number of address and datalines.The necessary decoder circuit is used to decode the address lines and to generate chip selectand output enable signals as shown in the diagram. Both the EPROM and RAM requires 8-datalines and 13 address lines. The remaining address lines are used in association with decoder togenerate CS signal.
  • 22. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comInterfacing of RAM and EPROM to 8051 Microcontroller : The interfacing ofEPROM 2764 to 8051 Microcontroller is shown below.This memory element stores the programcode.To access this external memory ,the PSEN pin (program Store enable )is a very importantpin.This pin is connected to the output enable pin of the EPROM. Similarly the ExternalAccess(EA) pin should always connected to ground to access the external memory. A 74LS373LATCH chip is used to demultiplex the address and data lines of the microcontroller.The addresslatch enable pin is connected to the Clk ,to enable the Latch. When ALE is high means,the Port0has the address on its lines otherwise the port0 has Dta on its lines. We can also use one bi-directional transreceiver chip for the data bus .This will increase the driving capabilities of thedata bus.In 8051 microcontroller ,the Port 0 has the dual application of AD bus as well as I/O port. Hencethe port pins are connected to the Latch. Similarly the Port 2 has the dual application of higherorder address bus and also I/O port. These address lines can be given to any bus driver or bufferIC to increase its driving capability. Since the EPROM is only of 8K X 8 chip, it requires only 13address lines to decode the address of the memory chip.
  • 23. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.comI/O Interfacing : Now a days microprocessor and microcontroller based systems are verywidely used in instrumentation or automatic control applications. In such cases it is necessarythat the microprocessor reads the input devices (switches, sensors) and activate some outputdevices (motors, heaters, lights). So, the I/O interface is required to enable the interface betweenthe microprocessor and the peripheral devices. These peripheral devices are connected on amicroprocessor system through the Input/Output ports.The I/O interface provides the following :(a) Isolation between the buses and the peripheral devices.(b) Address decoding. and (c) Synchronization/Latching.The I/O interfacing is normally done in two ways. Either by Isolated I/O scheme or Memorymapped I/O scheme. In isolated I/O scheme the I/O locations are separate from memorylocations and special I/O instructions (Like IN and OUT ..) are used but the disadvantage isadditional control signals like (IO/M) and the complexity in instructions increases.Ex : IN AL , 30H ; OUT 30H,ALBut in Memory mapped I/O scheme the same address is used for both I/O devices and memorylocations in the memory map. Simple instructions like MOV , LDR ,STR are used. Theadvantage is simpler decoding circuitry and no special instructions are required.Examples for I/O interfacing are , LED interfacing ,Stepper motor Interfacing ,LCD interfacing .To implement the Input ports a simple octal bus driver/buffer like 74LS244 or 74LS245 are used.Interfacing of I/O devices to 8086 Microprocessor : The interface diagram is shown below.The 8288 bus controller produces the control signals for the I/O subsystem.The 8288 generatesthe I/O read command output (IOR) and for I/O read cycle it generates I/O command outputsIOW and AIOW . The 8288 also produces the control signals ALE, DT/R & and DEN .Asshown in the diagram the MN/MX is grounded which indicates that the processor is in maximummode. The complete AD—AD15 bus is used for input and output data transfers and M/IO’ signalis made high to indicate that the device is an IO device. The various IO devices connected to the
  • 24. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.cominterface circuit may be seven segment display or Stepper motor or any keyboard or displaydevice.The IO devices amy be connected in minimum mode also.In such case the MN/MX pinmust be made High (Vcc).In such a case status signal SSO pin is used instead of BHE signal. ---------------xxx------------------

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