8096 microcontrollers notes
Upcoming SlideShare
Loading in...5
×
 

8096 microcontrollers notes

on

  • 9,016 views

 

Statistics

Views

Total Views
9,016
Views on SlideShare
9,015
Embed Views
1

Actions

Likes
1
Downloads
332
Comments
0

1 Embed 1

http://www.linkedin.com 1

Accessibility

Categories

Upload Details

Uploaded via as Microsoft Word

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

8096 microcontrollers notes 8096 microcontrollers notes Document Transcript

  • INTRODUCTION TO 8096 MICROCONTROLLERSSALIENT FEATURES : INTEL 8096 , a second generation processor belongs to MCS 96 family. This is a highperformance 16 bit microcontroller with register to register architecture. This is designed tohandle high speed calculations and fast input/output operations which is preferred in high speedmodern control applications. The 8096 with 16-bit CPU horse power ,high speed mathprocessing and high speed I/O is ideal for complex motor control and axis control systems.Hence it is used in 3 phase large horse power AC motors and robotics The 10-bit ADC optionmakes it most suitable candidate for data acquisition systems and closed loop analog controllers. 8096 can be configured in two modes . ( i ) Single chip mode and (ii) Expanded mode.In the single chip mode the internal ROM or EPROM is accessed by making the pin EA (Activelow) HIGH. For ROM less chip to access the external memory the pin EA is made low. In theexpanded mode both internal and external (OFF CHIP) memory can be accessed using themultiplexed bus architecture.It has nearly 230 bytes of on-chip RAM and one 10-bit A/Dconverter with sample hold circuit. There are five on chip I/O ports each of 8-bit width The 8096bit microcontroller has a complete set of 16-bit arithmetic instructions including multiply anddivide operations. It has Pulse Width Modulation Output with dedicated Baud Rate Generator Ithas one on chip Full Duplex Serial Port There are 20 interrupt sources and 8 interrupt vectors on8096. It has two 16-bit Timers Timer 1 and Timer 2 and one 16 bit watch dog timer This 8096 isavailable as 48 pin DIP(Dual In-line Package) and 68 pin PLCC and also 68 pin leadless chipcarrier IC. It is also available as a 68 pin PGA(Pin Grid Array) package .ARCHITECTURE : 8096 is a 16-bit microcontroller in which the data path for operands is 16 bits wide i.e when datais transferred between RAM or ROM and the CPU, it is transferred 16 bits per internal memorycycle. The 8096 has an internal 8-bit address bus and can access 2 8 addresses.The 8096 performsmost of the calculations in RALU. The RALU contains A 17 bit ALU One 16 bit program statusword (PSW) One program counter(PC) A loop counter and 3 temporary registers. All registersare 16 bit or 17 bit wide. A separate incrementor is used for the Program Counter .PSW Register :PSW Register IS A 16 bit Register, whose lower byte can act as INT_MASK register . Z is thezero flag N is the negative flag V is the overflow flag VT is the overflow Trap flag C is the carryflag I is the global interrupt enable flag ST is the sticky bit, it is set during a right shift
  • Two of the temporary registers have their own shift logic. The addressable memory space on the 8096is 64 kB , most of which are available to the user for program or data memory .The locations which havespecial purpose are 0000H through 00FFH and 1FFFH through 2010H.All other locations can be usedeither for program or for data storage or for memory mapped peripherals.Memory Mapping: The 64kB memory space mapping is shown in the diagram Fig.1 Memory MappingThe 8096 has been designed for high speed /high performance control applications. Because the8096 architecture is different from that of the 8048 or 8051 The architecture of 8096 has twomajor sections one is the CPU section and the other is the I/O section.The block diagram isshown in the figure 2
  • Fig.2.Block diagram of 8096 MicrocontrollerCPU OF 8096: The 8096 CPU has a 16-bit ALU which operates on a 256-byte register file instead of anaccumulator. Any of the locations in the register file can be used for sources or destinations formost of the instructions. Hence this is called a register to register architecture. Many of theinstructions can also use bytes or words from anywhere in the 64K byte address space asoperands. Locations 00h through 17H are the I/O control registers or special functionregisters(SFRs) Locations 18H and 19H contain the stack pointer which serves as generalpurpose RAM when not performing the stack operations. The remaining bytes of the register fileserves as general purpose RAM ,accessible as bytes,words or double-words. Calculationsperformed by the CPU takes place in the RALU .This RALU contains a 17 bit ALU ,the programstatus word (PSW),the program Counter(PC),a loop counter and three temporary registers. The
  • RALU operates directly on the register files, thus eliminating the problem with Accumulator andproviding direct control of I/O operations through the SFRs.I/O FEATURES : Most of the I/O features on the 8096 are designed to operate with little CPU intervention. TheWatchdog Timer is an internal timer which can be used to reset the system if the software fails tooperate properly. The Pulse-Width-Modulation (PWM) output can be used as a rough D to A, amotor driver, or for many other purposes. . The A to D converter (ADC) has 8 multiplexed inputsand 10-bit resolution. The serial port has several modes and its own baud rate generator. TheHigh Speed I/O section includes a 16-bit timer, a 16-bit counter, a 4-input programmable edgedetector, 4 software timers, and a 6-output programmable event generatorPWM OUTPUT:Analog outputs are just as important as analog inputs when connecting to a peripheral device.True digital to analog converters are difficult to make on a microcontroller because of all of thedigital noise and the necessity of providing an on chip, relatively high current, rail to rail driver.They also take up a fair amount of silicon area which can be better used for other features. The Ato D converter does use a D to A, but the currents involved are very small. The PWM signal is avariable duty cycle, fixed frequency waveform that can be integrated to provide anapproximation to an analog output. The frequency is fixed at a period of 64 microseconds for a12 MHz clock speed. Controlling the PWM simply requires writing the desired duty cycle value(an 8-bit value) to the PWM Register.General Purpose I/O PORTS :There are five 8-bit I/O Ports namely Port 0, Port 1, Port 2, Port 3 and Port 4 .PORT 0Port 0 is only an Input port which is also used as the analog input port for the on chip ADC. So,if the analog input features are not used ,the Port 0 Can be used as input port only .Port 0 isshown in Fig 3PORT 1: This is a quasi bidirectional port which can be used either as input or as the out port. It ismapped It is mapped at the memory address 0FH. If any of the port 1 pin is to be used as inputport the corresponding pin must be made high by writing the data 1. The weak internal pullup isdesigned to be overridden by the external device which drives the line. When the output drivecapability is sufficient to drive a 74LSxx Input a CMOS device driven by port1 will require apullup resistor of around 10K to +5V in order to bring the output up well above the normal
  • CMOS threshold voltage of 2.5 volts.Port1 inputs can be driven by either CMOS or TTL deviceswith no extra parts. Port 1 is shown in Fig 4 ., Fig 3 . PORT 0 Fig 4.Port 1PORT 2:The Port 2 has four input lines, two output lines andtwoquasi bidirectional I/O lines as shown in the Fig.One or more of these six lines can be used f or alternate purpose of PWM ,RXD,TXD, Timer 2 Inputs etc..
  • PORT3 & PORT 4:The Port3 & Port4 are similar in use.Both of them have open drain outputs. By writing 1 to anyline it can be used as an input and other lines can serve as output lines. Each output line require apullup resistor of about 15K.In the expansion mode ,the bus lines can gain the ability to driveboth high and low ,forming the expansion bus without the need of pullup resistors.RESETS AND SELFPROTECTION OPTIONS:RESETS AND SELFPROTECTION OPTIONS When the reset pin is driven to low the 8096,regardless of what it is doing will reset and start executing from the address 2080H.The reset pinis a bidirectional line with a strong internal pullup.T his line may also be driven by internalwatchdog timer also.The INTEL 8096 microcontroller is provided with on chip self protectioncircuitary , to protect the chip from large currents. The chip is automatically reset when the Vdd
  • deviates from the prescribed levels. Diode circuits are provided on the chip itself ,which givesself protection.HIGH SPEED INPUT UNIT:HIGH SPEED INPUT UNIT This unit is used to record the time at which an external eventoccurs with respect to timer 1. It can monitor four independently configurable HSI lines andcapture the value of Timer 1 when an event takes place. There are 4 lines (HIS.0-HIS.3)availablein this unit .The HIS unit can store upto 8 entries(Timer 1 values) . The HSI unit can generate aninterrupt when loading an entry into the HIS holding register or loading the sixth entry into theFIFO. The four types of events that can trigger captures include “rising edges only”, ”fallingedges only”,”rising or falling edges” or every eighth rising edge.HIGH SPEED OUTPUT UNIT:This HSO unit is used to trigger events at specified times based on Timer 1 or Timer 2 withminimal CPU over-head. The 4 events are Starting an A/D conversion Resetting of Timer2Setting four software flags Switching six output lines (HSO.0-HSO.5). The HSO unit storespending events and the specified time s in a Content Addressable Memory(CAM) file. ThisCAM file stores up to 8 commands. Each command specifies the action time,the nature of theaction ,whether an interrupt is to occur and whether Timer 1 or Timer 2 is the reference Timer.For every 8 state times the HSO compares the CAM locations for the time matches. The HSO unitcan generate two types of interrupts ( i ) HSO execution interrupt (Vector = 2006H) (ii) Software Timerinterrupt(Vector =200BH )TIMERS: INTEL 8096 controller has two on chip 16-bit timers TIMER 1 & TIMER 2 TIMER 1 can act asa 16-bit counter also and can be clocked at every 2 ms. i.e for every 8-internal clock cycles. ThisTimer is used in conjunction with high speed I/O system. When Timer 1 is over flown ,theinterrupt bit is enabled or disabled .. TIMER 2 can be used as a 16-bit even counter which isclocked by a signal coming into the chip on either of the two pinsPort2.3 or HIS.1 The choicebetween the two clock sources is made by setting or clearing bit 7 of the IOC.0 Timer 2 iscounted on both the rising edges and falling edges of the input signal and the minimum timebetween edges is 2 micro seconds.WATCH DOG TIMER: An on chip 16-bit watch dog timer is available in 8096 which helps to recover the controllerfrom the software upsets. This 16-bit WDT is a counter which is incremented every state time.This counter is cleared by program after periodic interval and not allowed to overflow . However, if the program does not progress properly by any reason such as Electrostatic Discharge(ESD) or due
  • to any hardware related problems ,the overflow occurs. And the hardware reset is initiated torestart the microcontroller . This process avoids the system from having a malfunction for longerthan 16mS under 12MHz frequency operation When the WDT overflows ,it pulls down theRESET pin for at least two state times resetting 8096 and also any other devices connected to theRESET line.INTERRUPT STRUCTURE: There are 20 different interrupt sources that can be used on the 8096. The 20 sources vectorthrough 8 locations or interrupt vectors. All these interrupts are enabled or disabled using the 9 thbit of PSW register. If this bit is set to 1 all the interrupts are enabled and disabled when reset tozero.Control of the interrupts is handled through the Interrupt Pending Register(INT_PENDING), the Interrupt Mask Register (INT_MASK), and the I bit in the PSW (PSW.9).The content of the interrupt mask register determine whether the pending interrupt is serviced ornot. If it is to be serviced , the CPU pushes the contents of the program counter on to the stackand reloads it with the vector corresponding to the desired interrupt. When the hardware detectsone of the 8 interrupts , it sets the corresponding bit in the interrupt pending register .Thisregister can be read or modified as a byte register. Individual interrupts can be enabled ordisabled by setting or clearing the bits in the Interrupt mask register. The INT_MASK registercan be accessed as the lower bits of the PSW register.SERIAL PORT: The 8096 has an on-chip full duplex serial port to reduce the total number of chips required inthe system.The serial port is similar to that on the 8051 controller. . It has one synchronous andthree asynchronous modes. In the asynchronous modes baud rates of up to 187.5 K baud can beused, while in the synchronous mode rates up to 1.5 M baud are available. The chip has a baudrate generator which is independent of Timer 1 and Timer 2, so using the serial port does nottake away any of the HSI, HSO or timer flexibility or functionality. Control of the serial port isprovided through the SPCON/SPSTAT (Serial Port CONtrol /Serial Port STATus ) register. Theserial port is configured in four modes. The four modes of the serial port are referred to as modes0, 1, 2 and 3. Mode 0 is the synchronous mode, and is commonly used to interface to shiftregisters for I/O expansion. In this mode the port outputs a pulse train on the TXD pin and eithertransmits or receives data on the RXD pin. Mode 1 is the standard asynchronous mode, 8 bitsplus a stop and start bit are sent or received.. Modes 2 and 3 handle 9 bits plus a stop and startbit. The difference between the two is, that in Mode 2 the serial port interrupt will not beactivated unless the ninth data bit is a one; in Mode 3 the interrupt is activated whenever a byte isreceived. These two modes are commonly used for interprocessor communication. Baud ratesfor all of the modes are controlled through the Baud Rate register. This is a byte wide registerwhich is loaded sequentially with two bytes, and internally stores the value as a word. The least
  • significant byte is loaded to the register followed by the most significant. The most significant bitof the baud value determines the clock source for the baud rate generator. Ifthe bit is a one, theXTAL1 pin is used as the source, if it is a zero, the T2 CLK pin is used .ADDRESSING MODES:The 8096 instruction set supports six addressing modes. They areImmediate addressing modeRegister direct addressing modeIndirect addressing modeIndirect with auto increment modeShort indexed mode andLong indexed mode.These addressing modes increase the flexibility and overall execution speed of 8096 controller.Each instruction uses at least one of the addressing modes. The register , direct and immediateaddressing modes execute faster than the other addressing modes. Both of the indirect addressingmodes use the value in a word register as the address of the operand. The indirect auto incrementmode ,increments a word address by one after a byte operation and two after a word operation.A to D CONVERTER: Analog inputs are frequently required in every microcontroller application . The 8096 controllerhas one 10 bit on chip A/D converter that can use any one of eight input channels. Theconversions are done using the successive approximation method, and require 168 state times (42microseconds with a 12 MHz clock.). The main components of the A/D converter are 8-analoginput channels One 8 to 1 multiplexer. A sample and hold capacitor and Resistor ladder The A/Dconverter performs a conversion in 88 time states .Upon the completion of each conversion theconverter can generate a conversion complete interrupt .REFERENCES:1. Design with Microcontrollers –John . B. Peatman – Mc.Graw -Hill International Ed.2.Intel Application note & data sheet .