Rapport : Contrôleur d’affichage vidéo VGARéaliser par :AYARI YAHIA & DAHMANI MOHAMED2010/2011SommaireBut :Introduction :D...
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
Realisation de controlleur VGA(VHDL)
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Realisation de controlleur VGA(VHDL)

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this is my first step of realisation of one VHDL design project (VGA )

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Transcript of "Realisation de controlleur VGA(VHDL)"

  1. 1. Rapport : Contrôleur d’affichage vidéo VGARéaliser par :AYARI YAHIA & DAHMANI MOHAMED2010/2011SommaireBut :Introduction :Description des machines à état :Décoder :Générateur de synchronisation :Synchro ligne :Synchro trame :Afficher :Description matérielle :Schéma RTL :Description en VHDL (code source) :MUX1 :ROM :RAM :MUX2 :Séquenceurs :Générateur de décodage :Gestionnaire d’affichage :Générateur de synchronisation :Générateur trameGénérateur ligne :Top module VGA :Les scenarios de test (TEST BENCH):Test MUXTest ROM:Test decoder:Test afficher :Test ligne :Test trame :Test VGA:Simulation:Fichier texte:Exemple de simulation:Rapport technique :Outils de développement :Conclusion : <br />BUT :<br />Notre projet sert à réaliser une propriété intellectuelle d’affichage vidéo VGA destiné au débogage hardware en environnement FPGA. Dans ce TP on va se familiariser avec un outil de développement hard trop connu XILINX, puis on va implémenter notre application sur une FPGA adéquate.<br />Introduction :<br />Il existe plusieurs modes pour la norme VGA, et nous allons utiliser celle dont la définition de l’image est de 640×480 dont les informations sont codées chacune sur un ensemble de bit.<br />Le protocole VGA consiste à utiliser deux signaux de synchronisation horizontale <br />SL et verticale ST pour pouvoir guider la manière d’afficher. Pour une qui parvient à tous les pixels de l’écran à une fréquence de 25 MHz (soit à une période de 40 ns). <br />Le module d’affichage VGA lit une image à partir d’une mémoire et l’affiche sur un écran. Les contraintes à prendre en compte sont les contraintes de temps d’accès aux données des pixels et leur transmission sur un câble VGA dans les délais requis. D’autres difficultés se présentent aussi, surtout lorsque l’image en question stockée dans la mémoire est lue à partir d’un PC à travers un câble série. <br />Dans ce cas, il faut gérer et organiser l’accès en lecture et en écriture à la mémoire par les différentes unités et en utilisant des autres modules de traitement et de gestion qui seront des extensions pour notre application et notre IP ;<br />Cette IP étant intégré dans des applications matérielles sur FPGA permet de visualiser sur écran SVGA une ligne de 8 caractère des valeurs hexadécimaux à partir de 8 signaux en entré U0-U7 codés sur 4 bits.<br />ST Module d’affichage de 16 Mots binaires à 4 bits<br />SL25MHZ<br />SPU<0><br />RVBU<7><br /> SPECIFICATION EXTERNE D’IP<br />En sortie : cette IP fournira des signaux de contrôle d’affichage vidéo :<br />ST : Synchronisation de début d’une image (trame) affichée en temps réels.<br />SL : Synchronisation de début d’une ligne.<br />SP : Synchronisation de Transfer d’un pixel<<point image>>.<br />RVB(Final) : signal résultat validé à chaque front montant d’horloge.<br />La fréquence de rafraichissement doit être suffisante pour tromper la persistance de l’œil humaine, les pixels sont affichés séquentiellement par succession de lignes horizontaux de haut en bas, le balayage de ligne s’effectue de droite à gauche.<br />Pour cette IP on choisie l’affichage SVGA SP=25 MHZ, SL=31.25 KHZ, ST=62. HZ<br />On distingue les modules suivants :<br />Chemin de données :<br />Mux1 : multiplexeur des signaux Ui.<br />ROM : permet de garder la police des caractères en mémorisant les fonts de ces caractères hexadécimaux de 0 à F.<br />RAM : une mémoire en double port pour mémoriser le plan image dit bitmap.<br />Mux2 : pour la sérialisation des mots binaire vers les signaux d’affichage.<br />Séquenceurs :<br /> Gestion de décodage binaire : ce module ce module séquentielle à chaque début de trame il sert à indexer la Rom et la Ram pour pouvoir savoir d’où et où en va écrire.<br /> Gestion d’affichage : ce module génère le signal sortie et gère le nombre de colonne et de ligne de la trame lors de la l’écriture il est dirigé par le générateur de synchronisation.<br />Gestion de synchronisation : ce module génère les synchro trame ST et les synchro ligne SL. C’est lui qui indique le début d’une trame ou celle d’une ligne. <br />Description des machines à états :<br />Décoder : <br />Générateur de synchronisation :<br />Synchro ligne : <br />Synchro trame : <br />Afficher : <br />Description matérielle:<br />Schema RTL<br />Description en VHDL (code source):<br />MUX1<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />entity MUX_8_1 is port(<br /> u0 : in STD_LOGIC_vector(3 downto 0); ----les données à afficher----<br /> u1 : in STD_LOGIC_vector(3 downto 0);<br /> u2 : in STD_LOGIC_vector(3 downto 0);<br /> u3 : in STD_LOGIC_vector(3 downto 0);<br /> u4 : in STD_LOGIC_vector(3 downto 0);<br /> u5 : in STD_LOGIC_vector(3 downto 0);<br /> u6 : in STD_LOGIC_vector(3 downto 0);<br /> u7 : in STD_LOGIC_vector(3 downto 0);<br /> se : in STD_LOGIC_vector(2 downto 0); -----entrée selective----- <br /> ds : out STD_LOGIC_vector(3 downto 0)); -----sortie de MUX------<br />end MUX_8_1;<br />architecture MUX_8_1 of MUX_8_1 is<br />begin<br /> process(se,u0,u1,u2,u3,u4,u5,u6,u7) <br /> begin <br /> <br />Case se is<br />when "000" => ds <= u0;<br />when "001" => ds <= u1;<br />when "010" => ds <= u2;<br />when "011" => ds <= u3;<br />when "100" => ds <= u4;<br />when "101" => ds <= u5;<br />when "110" => ds <= u6;<br />when "111" => ds <= u7;<br /> when others => ds <= "0000" ;<br /> end case ;<br />end process;<br />end MUX_8_1;<br />ROM<br />----------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer: <br />-- <br />-- Create Date: 15:43:06 03/14/2011 <br />-- Design Name: <br />-- Module Name: ROM - Behavioral <br />-- Project Name: <br />-- Target Devices: <br />-- Tool versions: <br />-- Description: <br />--<br />-- Dependencies: <br />--<br />-- Revision: <br />-- Revision 0.01 - File Created<br />-- Additional Comments: <br />--<br />----------------------------------------------------------------------------------<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity ROM is port(<br />A: in std_logic_vector(9 downto 0);<br />data:out std_logic);<br />end ROM;<br />architecture Behavioral of ROM is<br />signal inter :std_logic_vector(63 downto 0):=(others => '0');<br />signal i:integer range 127 downto 0 :=0;<br />signal j:integer range 63 downto 0 :=0;<br />type police is array(127 downto 0) of std_logic_vector(7 downto 0);<br />constant D : police := (<br /> 0 => "01110000", --0--<br /> 1 => "10001000",<br /> 2 => "10001000",<br /> 3 => "10001000",<br /> 4 => "10001000",<br /> 5 => "10001000",<br /> 6 => "10001000",<br /> 7 => "01110000",<br /> 8 => "00100000", --1--<br /> 9 => "01100000",<br /> 10 => "10100000",<br /> 11 => "00100000",<br /> 12 => "00100000",<br /> 13 => "00100000",<br /> 14 => "00100000",<br /> 15 => "11111000",<br />16 => "01110000", --2--<br /> 17 => "10001000",<br /> 18 => "10001000",<br /> 19 => "00010000",<br /> 20 => "00100000",<br /> 21 => "01000000",<br /> 22 => "11111000",<br /> 23 => "11111000", --3--<br /> 24 => "00001000",<br /> 25 => "00001000",<br /> 26 => "01111000",<br /> 27 => "01111000",<br /> 28 => "00001000",<br /> 29 => "00001000",<br /> 30 => "11111000",<br /> 31 => "10000000", --4--<br />32 => "10000000",<br /> 33 => "10010000",<br /> 34 => "10010000",<br /> 35 => "11111000",<br /> 36 => "00010000",<br /> 37 => "00010000",<br /> 38 => "00010000", <br /> 39 => "11111000", --5--<br /> 40 => "10000000", <br /> 41 => "10000000",<br /> 42 => "10000000",<br /> 43 => "11111000",<br /> 44 => "00001000",<br /> 45 => "00001000",<br /> 46 => "11111000",<br /> 47 => "11111000", --6--<br />48 => "00001000",<br /> 49 => "00001000",<br /> 50 => "11111000",<br /> 51 => "10001000",<br /> 52 => "10001000",<br /> 53 => "10001000",<br /> 54 => "11111000",<br /> 55 => "11111000", --7--<br /> 56 => "10001000",<br />57 => "00001000",<br />58 => "00001000",<br />59 => "00010000",<br /> 60 => "00100000",<br /> 61 => "01000000",<br /> 62 => "10000000",<br /> 63 => "11111000", --8--<br /> 64 => "10001000",<br /> 65 => "10001000",<br /> 66 => "11111000",<br />67 => "10001000",<br /> 68 => "10001000",<br /> 69 => "10001000",<br /> 70 => "11111000",<br /> 71 => "11111000", --9--<br /> 72 => "10001000",<br /> 73 => "10001000",<br /> 74 => "11111000",<br /> 75 => "00001000",<br /> 76 => "00001000",<br /> 77 => "10001000",<br /> 78 => "11111000",<br /> 79 => "01110000", --A--<br /> 80 => "10001000",<br /> 81 => "10001000",<br /> 82 => "10001000",<br />83 => "11111000",<br /> 84 => "10001000",<br /> 85 => "10001000",<br /> 86 => "10001000",<br /> 87 => "11111000", --B--<br /> 88 => "10001000",<br /> 89 => "10001000",<br /> 90 => "11111000",<br /> 91 => "10001000",<br /> 92 => "10001000",<br /> 93 => "10001000",<br /> 94 => "11111000",<br /> 95 => "11111000", --C--<br /> 96 => "10001000",<br /> 97 => "10000000",<br /> 98 => "10000000",<br />99 => "10000000",<br /> 100=> "10000000",<br /> 101=> "10000000",<br /> 102=> "10000000",<br /> 103=> "11111000",<br /> 104=> "11110000", --D--<br /> 105=> "10001000",<br /> 106=> "10001000",<br /> 107=> "10001000",<br /> 108=> "10001000",<br /> 109=> "10001000",<br /> 110=> "10001000",<br /> 111=> "11110000",<br /> 112=> "11111000", --E--<br /> 113=> "10001000",<br /> 114=> "10000000",<br />115=> "10000000",<br /> 116=> "11110000",<br /> 117=> "10000000",<br /> 118=> "10001000",<br /> 119=> "11111000",<br /> 120=> "11111000", --F--<br /> 121=> "10001000",<br /> 122=> "10000000",<br /> 123=> "11110000",<br /> 124=> "10000000",<br /> 125=> "10000000",<br /> 126=> "10000000",<br /> 127=> "10000000");<br /> <br />begin<br />i <= 8*(to_integer ( unsigned (A(3 downto 0))));<br />j <= (to_integer ( unsigned (A(9 downto 4)))); <br />inter(7 downto 0) <= D(i); inter(39 downto 32) <= D(i+4); <br />inter(15 downto 8) <= D(i+1); inter(47 downto 40) <= D(i+5); <br />inter(23 downto 16) <= D(i+2); inter(55 downto 48) <= D(i+6); <br />inter(31 downto 24) <= D(i+3); inter(63 downto 56) <= D(i+7); <br />data <= inter(j);<br />end Behavioral;<br />RAM<br />----------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer: <br />-- <br />-- Create Date: 14:40:18 03/15/2011 <br />-- Design Name: <br />-- Module Name: RAM - Behavioral <br />-- Project Name: <br />-- Target Devices: <br />-- Tool versions: <br />-- Description: <br />--<br />-- Dependencies: <br />--<br />-- Revision: <br />-- Revision 0.01 - File Created<br />-- Additional Comments: <br />--<br />----------------------------------------------------------------------------------<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity RAM_VGA is port(<br />A: in std_logic_vector(8 downto 0);<br />R: in std_logic_vector(8 downto 0);<br />Din,clk,WR:in std_logic;<br />Dout:out std_logic);<br />end RAM_VGA;<br />architecture Behavioral of RAM_VGA is<br />signal RAM_MEM:std_logic_vector(511 downto 0);<br />begin<br />write_process: Process(clk,WR)<br />begin<br />if(clk' event and clk='1') then<br />if WR='1' then<br /> (RAM_MEM(to_integer(unsigned(A)))) <= Din;<br />end if;<br />end if;<br />end process;<br />read_process: process(R,wr,RAM_MEM)<br />begin<br />if(wr='0')then<br />Dout <= (RAM_MEM(to_integer(unsigned(R))));<br />end if;<br />end process;<br />end Behavioral;<br />MUX2<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />entity MUX_2_1 is port(<br /> enter : in STD_LOGIC; ----les données à afficher----<br /> mass : in STD_LOGIC;<br /> <br /> se : in std_logic; -----entrée selective-----<br /> <br /> final : out STD_LOGIC); -----sortie de MUX------<br />end MUX_2_1;<br />architecture Behavioral of MUX_2_1 is<br />begin<br /> process (se,enter,mass)<br /> begin<br /> Case se is<br /> <br /> when '0' => final <= mass;<br /> when '1' => final <= enter;<br /> when others => final <= '0' ;<br />end case ;<br /> end process;<br />end Behavioral;<br />Sequenceurs<br />Gestionneur de decodage<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity decoder is port(<br />st,clk:in std_logic;<br />wr:out std_logic;<br />sortie:out std_logic_vector(8 downto 0));<br />end decoder;<br />architecture Behavioral of decoder is<br />type state is(repot,copier,fin_t);<br />signal etat:state;<br />signal inter:std_logic_vector(8 downto 0):=(others => '0');<br />begin<br />process(clk)<br />begin<br /> if(clk'event and clk='1') then<br /> <br /> case etat is<br /> when repot => ---repot--<br /> <br /> inter<="000000000";<br /> wr<='0';<br />if st='0' then<br /> etat<= copier;<br />end if;<br /> when copier => <br /> sortie<=inter; ---copier --<br /> inter<=inter+"000000001";<br /> <br /> wr<='1';<br />if inter="111111111" then<br /> etat<= fin_t;<br />end if;<br /> when fin_t => ---fin_t--<br /> <br /> wr<='0';<br />if st='1' then<br /> etat<= repot;<br />end if;<br />end case;<br />end if;<br />end process;<br />end Behavioral;<br />Gestionnaire d’affichage<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity affichage is port(<br />clk,ft,fl:in std_logic;<br />nl:out std_logic_vector( 2 downto 0);<br />nc:out std_logic_vector( 5 downto 0);<br />noir:out std_logic);<br />end affichage;<br />architecture Behavioral of affichage is<br />type state is(repot,attendre_fl,ligne,incrementation,fin_ligne,fin_trame);<br />signal etat:state;<br />signal nc1:std_logic_vector( 5 downto 0):=(others => '0');<br />signal nl1:std_logic_vector( 3 downto 0):=(others => '0');<br />begin<br />process(clk)<br />begin<br /> if (clk' event and clk='1') then<br /> case etat is<br /> when repot => ---repot--<br /> noir<='0';<br /> nc1<="000000";<br /> nl1<="0000";<br />if ft='1' then<br /> etat<= attendre_fl;<br />end if; <br /> when attendre_fl => ---attendre fenetre ligne--<br /> noir<='0'; <br /> nc1<="000000";<br /> <br /> if fl='1' then<br /> etat<= ligne;<br /> end if;<br /> when ligne =><br /> ---affichage d'une ligne---<br /> noir<='1';<br /> nc<=nc1;<br /> nc1<=nc1+"000001";<br /> <br /> <br /> if nc1="111111" then<br /> etat<= incrementation;<br /> end if;<br /> <br /> when incrementation => ---incrementation de nombre de ligne----<br /> <br /> noir<='0';<br /> nc1<="000000";<br /> nl1<=nl1+"0001";<br /> nl<=nl1(2 downto 0);<br /> if nl1="1000" then<br /> --etat<=fin_ligne;<br /> etat<=fin_trame;<br /> end if;<br /> if nl1/="1000" then<br /> etat<= fin_ligne;<br /> end if;<br /> when fin_ligne => ----fin ligne-------------<br /> <br /> noir<='0';<br /> <br /> if fl='0' then<br /> etat<= attendre_fl;<br />end if;<br /> when fin_trame => ----fin trame----<br /> noir<='0';<br /> <br /> if ft='0' then<br /> etat<= repot;<br />end if;<br />end case;<br /> end if;<br /> end process;<br />end Behavioral;<br />Générateur de synchronisation<br />Générateur ligne <br />----------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer: <br />-- <br />-- Create Date: 19:32:25 03/17/2011 <br />-- Design Name: <br />-- Module Name: generateur_ligne - Behavioral <br />-- Project Name: <br />-- Target Devices: <br />-- Tool versions: <br />-- Description: <br />--<br />-- Dependencies: <br />--<br />-- Revision: <br />-- Revision 0.01 - File Created<br />-- Additional Comments: <br />--<br />----------------------------------------------------------------------------------<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity generateur_ligne is port(<br />clk: in std_logic;<br />sl,fl:out std_logic );<br />end generateur_ligne;<br />architecture Behavioral of generateur_ligne is<br />type state is(deb,tsl,gap1,gap2,ligne);<br />signal etat : state;<br />signal n : integer range 0 to 800;<br />begin<br />process(clk)<br />begin<br /> if (clk' event and clk='1') then<br /> case etat is<br /> when deb => ---debut--<br /> n<= 800;<br /> sl<='1';<br /> fl<='0';<br /> etat<= tsl;<br /> <br /> when tsl => ---retour en ligne--<br /> n<= n-1; <br /> sl<='0';<br /> fl<='0';<br /> if n=740 then<br /> etat<= gap1;<br />end if;<br /> when gap1 => ---debut d'une fenetre ligne---<br /> n<=n-1;<br /> sl<='1';<br /> fl<='0';<br /> if n=690 then<br /> etat<= ligne;<br />end if;<br /> when ligne => ---ligne à écrire ----<br /> n<=n-1;<br /> sl<='1';<br /> fl<='1';<br /> if n=50 then<br /> etat<= gap2;<br />end if;<br /> when gap2 => ----fenetre ligne (blanc aprés ligne)----<br /> n<=n-1;<br /> sl<='0';<br /> fl<='0';<br /> if n=0 then<br /> <br /> etat<= deb;<br />end if;<br />end case;<br /> end if;<br /> end process;<br />end Behavioral;<br />Générateur trame<br />----------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer: <br />-- <br />-- Create Date: 13:11:39 03/29/2011 <br />-- Design Name: <br />-- Module Name: generateur_trame - Behavioral <br />-- Project Name: <br />-- Target Devices: <br />-- Tool versions: <br />-- Description: <br />--<br />-- Dependencies: <br />--<br />-- Revision: <br />-- Revision 0.01 - File Created<br />-- Additional Comments: <br />--<br />----------------------------------------------------------------------------------<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity generateur_trame is port(<br />sl:in std_logic;<br />st,ft:out std_logic);<br />end generateur_trame;<br />architecture Behavioral of generateur_trame is<br />type state is(deb,tst,gapt1,page,gapt2);<br />signal etat:state;<br />signal n : integer range 0 to 503;<br />begin<br />process(sl)<br />begin<br /> if (sl='0') then<br /> case etat is<br /> when deb => ---debut----- <br /> n<=503;<br /> st<='1';<br /> ft<='0'; <br /> etat<= tst;<br /> when tst => ---nouvelle trame--<br /> n<= n-1; <br /> st<='0';<br /> ft<='0';<br /> if n=495 then<br /> etat<= gapt1;<br />end if;<br /> when gapt1 => ---debut d'une fenetre trame---<br /> n<=n-1;<br /> st<='1';<br /> ft<='0';<br /> if n=490 then<br /> etat<= page;<br />end if;<br /> when page => ---trame à écrire ----<br /> n<=n-1;<br /> st<='1';<br /> ft<='1';<br /> if n=10 then<br /> etat<= gapt2;<br />end if;<br /> when gapt2 => ----fenetre trame (blanc aprés les lignes)----<br /> n<=n-1;<br /> st<='1';<br /> ft<='0';<br /> if n=0 then<br /> <br /> etat<= deb;<br />end if;<br />end case;<br /> end if;<br />end process;<br />end Behavioral;<br />Top module VGA<br />----------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer: <br />-- <br />-- Create Date: 13:13:09 04/09/2011 <br />-- Design Name: <br />-- Module Name: top - Behavioral <br />-- Project Name: <br />-- Target Devices: <br />-- Tool versions: <br />-- Description: <br />--<br />-- Dependencies: <br />--<br />-- Revision: <br />-- Revision 0.01 - File Created<br />-- Additional Comments: <br />--<br />----------------------------------------------------------------------------------<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--use IEEE.NUMERIC_STD.ALL;<br />-- Uncomment the following library declaration if instantiating<br />-- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br /> <br />entity top is port( <br /> uu0 : in std_logic_vector(3 downto 0);<br /> uu1 : in std_logic_vector(3 downto 0);<br /> uu2 : in std_logic_vector(3 downto 0);<br /> uu3 : in std_logic_vector(3 downto 0);<br /> uu4 : in std_logic_vector(3 downto 0);<br /> uu5 : in std_logic_vector(3 downto 0);<br /> uu6 : in std_logic_vector(3 downto 0);<br /> uu7 : in std_logic_vector(3 downto 0); <br /> clk_25MHZ: in std_logic;<br /> sl,st:out std_logic;<br /> final:out std_logic<br /> );<br />end top;<br />architecture top of top is<br /> COMPONENT ROM<br /> PORT(<br /> A : IN std_logic_vector(9 downto 0);<br /> data : OUT std_logic<br /> );<br /> END COMPONENT;<br /> COMPONENT RAM_VGA<br />port(<br /> A: in std_logic_vector(8 downto 0);<br /> R: in std_logic_vector(8 downto 0);<br /> Din,clk,WR:in std_logic;<br /> Dout:out std_logic<br /> );<br /> END COMPONENT; <br /> COMPONENT MUX_8_1<br />PORT(<br /> u0 : in STD_LOGIC_vector(3 downto 0); <br /> u1 : in STD_LOGIC_vector(3 downto 0);<br /> u2 : in STD_LOGIC_vector(3 downto 0);<br /> u3 : in STD_LOGIC_vector(3 downto 0);<br /> u4 : in STD_LOGIC_vector(3 downto 0);<br /> u5 : in STD_LOGIC_vector(3 downto 0);<br /> u6 : in STD_LOGIC_vector(3 downto 0);<br /> u7 : in STD_LOGIC_vector(3 downto 0);<br /> se : in STD_LOGIC_vector(2 downto 0); <br /> ds : out STD_LOGIC_vector(3 downto 0)); <br />END COMPONENT;<br /> COMPONENT MUX_2_1<br /> PORT(<br /> enter : in STD_LOGIC; <br /> mass : in STD_LOGIC;<br /> se : in std_logic; <br /> final : out STD_LOGIC);<br /> END COMPONENT; <br /> COMPONENT affichage<br /> PORT(<br /> clk : IN std_logic;<br /> ft : IN std_logic;<br /> fl : IN std_logic;<br /> nl : OUT std_logic_vector(2 downto 0);<br /> nc : OUT std_logic_vector(5 downto 0);<br /> noir : OUT std_logic<br /> );<br /> END COMPONENT;<br /> COMPONENT decoder<br /> PORT(<br /> st : IN std_logic;<br /> clk : IN std_logic;<br /> wr : OUT std_logic;<br /> sortie : OUT std_logic_vector(8 downto 0)<br /> );<br /> END COMPONENT; <br /> COMPONENT generateur_trame<br /> PORT(<br /> sl : IN std_logic;<br /> st : OUT std_logic;<br /> ft : OUT std_logic<br /> );<br /> END COMPONENT;<br /> COMPONENT generateur_ligne<br /> PORT(<br /> clk : IN std_logic;<br /> sl : OUT std_logic;<br /> fl : OUT std_logic<br /> );<br /> END COMPONENT;<br /> <br />signal ds1:std_logic_vector(3 downto 0);<br />signal sortie1:std_logic_vector(8 downto 0);<br />signal data1:std_logic;<br />signal WR1:std_logic;<br />signal DOUT1:std_logic; <br />signal noir1:std_logic;<br />signal nc1:std_logic_vector( 5 downto 0);<br />signal nl1:std_logic_vector( 2 downto 0);<br />signal ft1:std_logic;<br />signal fl1:std_logic;<br />signal st1:std_logic;<br />signal sl1:std_logic;<br />signal mass:std_logic;<br />begin <br />mass<='0';<br />a1:MUX_8_1 PORT MAP(<br />u0=>uu0,<br />u1=>uu1,<br />u2=>uu2,<br />u3=>uu3,<br />u4=>uu4,<br />u5=>uu5, <br />u6=>uu6,<br />u7=>uu7,<br />se=>sortie1(8 downto 6),<br />ds=>ds1<br />); <br /> <br />a11: MUX_2_1 PORT MAP (<br /> enter =>DOUT1,<br /> mass => mass,<br /> se => noir1,<br /> final=> final<br /> ); <br />a2:ROM PORT MAP (<br /> A(3 downto 0)=> ds1,<br /> A(9 downto 4)=>sortie1(5 downto 0),<br /> data => data1<br /> );<br />a3:RAM_VGA port MAP(<br /> A=>sortie1,<br /> R(8 downto 6)=>nc1(5 downto 3),<br /> R(5 downto 3)=>nl1,<br /> R(2 downto 0)=>nc1(2 downto 0), <br /> Din=>data1,<br /> clk=>clk_25MHZ,<br /> WR=>WR1,<br /> Dout=>DOUT1<br /> );<br /> <br />a4:affichage PORT MAP (<br /> clk => clk_25MHZ,<br /> ft => ft1,<br /> fl => fl1,<br /> nl => nl1,<br /> nc => nc1,<br /> noir => noir1<br /> );<br />a5:decoder PORT MAP (<br /> st => st1,<br /> clk => clk_25MHZ,<br /> wr => WR1,<br /> sortie => sortie1<br /> );<br />a6:generateur_trame PORT MAP (<br /> sl => sl1,<br /> st => st1,<br /> ft => ft1<br /> );<br />a7:generateur_ligne PORT MAP (<br /> clk => clk_25MHZ,<br /> sl => sl1,<br /> fl => fl1<br /> ); <br />sl<=sl1;<br />st<=st1;<br />end top;<br />Les scenarios de test (les tests bench):<br />Test MUX :<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 20:31:03 03/30/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_MUX.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: MUX_8_1<br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes: <br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee;<br />USE ieee.std_logic_1164.ALL;<br /> <br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY test_MUX IS<br />END test_MUX;<br /> <br />ARCHITECTURE behavior OF test_MUX IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT MUX_8_1<br /> PORT(<br /> u0 : IN std_logic_vector(3 downto 0);<br /> u1 : IN std_logic_vector(3 downto 0);<br /> u2 : IN std_logic_vector(3 downto 0);<br /> u3 : IN std_logic_vector(3 downto 0);<br /> u4 : IN std_logic_vector(3 downto 0);<br /> u5 : IN std_logic_vector(3 downto 0);<br /> u6 : IN std_logic_vector(3 downto 0);<br /> u7 : IN std_logic_vector(3 downto 0);<br /> se : IN std_logic_vector(2 downto 0);<br /> ds : OUT std_logic_vector(3 downto 0)<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs<br /> signal u0 : std_logic_vector(3 downto 0) := "1011";<br /> signal u1 : std_logic_vector(3 downto 0) := (others => '0');<br /> signal u2 : std_logic_vector(3 downto 0) := (others => '0');<br /> signal u3 : std_logic_vector(3 downto 0) := (others => '0');<br /> signal u4 : std_logic_vector(3 downto 0) := (others => '0');<br /> signal u5 : std_logic_vector(3 downto 0) := (others => '0'); <br /> signal u6 : std_logic_vector(3 downto 0) := (others => '0');<br /> signal u7 : std_logic_vector(3 downto 0) := (others => '0');<br /> signal se : std_logic_vector(2 downto 0) := "000";<br /> --Outputs<br /> signal ds : std_logic_vector(3 downto 0);<br /> -- No clocks detected in port list. Replace <clock> below with <br /> -- appropriate port name <br /> <br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: MUX_8_1 PORT MAP (<br /> u0 => u0,<br /> u1 => u1,<br /> u2 => u2,<br /> u3 => u3,<br /> u4 => u4,<br /> u5 => u5,<br /> u6 => u6,<br /> u7 => u7,<br /> se => se,<br /> ds => ds<br /> );<br />END;<br />Test ROM :<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 12:49:36 03/15/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/ROM_TEST.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: ROM<br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes: <br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee;<br />USE ieee.std_logic_1164.ALL;<br /> use IEEE.numeric_std.ALL;<br />use IEEE.STD_LOGIC_unsigned.ALL;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY ROM_TEST IS<br />END ROM_TEST;<br /> <br />ARCHITECTURE behavior OF ROM_TEST IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT ROM<br /> PORT(<br /> A : IN std_logic_vector(9 downto 0);<br /> data : OUT std_logic<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs<br /> signal A : std_logic_vector(9 downto 0) := "1111101111"; <br /> --Outputs<br /> signal data : std_logic;<br /> -- No clocks detected in port list. Replace <clock> below with <br /> -- appropriate port name <br /> <br /> <br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: ROM PORT MAP (<br /> A => A,<br /> data => data<br /> );<br />END;<br />Test decoder<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 22:19:06 03/30/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_decoder.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: decoder <br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes: <br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee;<br />USE ieee.std_logic_1164.ALL;<br /> <br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY test_decoder IS<br />END test_decoder;<br /> <br />ARCHITECTURE behavior OF test_decoder IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT decoder<br /> PORT(<br /> st : IN std_logic;<br /> clk : IN std_logic;<br /> wr : OUT std_logic;<br /> sortie : OUT std_logic_vector(8 downto 0)<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs<br /> signal st : std_logic := '0';<br /> signal clk : std_logic := '0';<br /> --Outputs<br /> signal wr : std_logic;<br /> signal sortie : std_logic_vector(8 downto 0);<br /> -- Clock period definitions<br /> constant clk_period : time := 0.002 ns;<br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: decoder PORT MAP (<br /> st => st,<br /> clk => clk,<br /> wr => wr,<br /> sortie => sortie<br /> );<br /> -- Clock process definitions<br /> clk_process :process<br /> begin<br />clk <= '0';<br />wait for clk_period/2;<br />clk <= '1';<br />wait for clk_period/2;<br /> end process;<br /> <br /> -- Stimulus process<br /> stim_proc: process<br /> begin<br /> -- hold reset state for 100 ns.<br /> wait for 100 ns;<br /> wait for clk_period*10;<br /> -- insert stimulus here <br /> wait;<br /> end process;<br />END;<br />Test afficher<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 22:26:36 03/29/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_affichage.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: affichage<br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes: <br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee;<br />USE ieee.std_logic_1164.ALL;<br /> <br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY test_affichage IS<br />END test_affichage;<br /> <br />ARCHITECTURE behavior OF test_affichage IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT affichage<br /> PORT(<br /> clk : IN std_logic;<br /> ft : IN std_logic;<br /> fl : IN std_logic;<br /> nl : OUT std_logic_vector(2 downto 0);<br /> nc : OUT std_logic_vector(5 downto 0);<br /> noir : OUT std_logic<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs <br /> signal clk : std_logic := '0';<br /> signal ft : std_logic := '1';<br /> signal fl : std_logic := '1';<br /> --Outputs<br /> signal nl : std_logic_vector(2 downto 0);<br /> signal nc : std_logic_vector(5 downto 0);<br /> signal noir : std_logic;<br /> -- Clock period definitions<br /> constant clk_period : time := 0.002 ns;<br />signal n:integer range 0 to 100;<br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: affichage PORT MAP (<br /> clk => clk,<br /> ft => ft,<br /> fl => fl,<br /> nl => nl,<br /> nc => nc,<br /> noir => noir<br /> );<br /> -- Clock process definitions<br /> clk_process :process<br /> begin<br /> fl<='1';<br />clk <= '0';<br />wait for clk_period/2;<br />clk <= '1';<br />wait for clk_period/2;<br /> <br />fl<='0'after 0.137 ns;<br /> end process;<br />END;<br />Test_ligne<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 22:51:19 03/17/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/tester_ligne.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: generateur_ligne<br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes: <br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee;<br />USE ieee.std_logic_1164.ALL;<br /> <br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY tester_ligne IS<br />END tester_ligne;<br /> <br />ARCHITECTURE behavior OF tester_ligne IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT generateur_ligne<br /> PORT(<br /> clk : IN std_logic;<br /> sl : OUT std_logic;<br /> fl : OUT std_logic<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs<br /> signal clk : std_logic := '0';<br /> --Outputs<br /> signal sl : std_logic;<br /> signal fl : std_logic;<br /> -- Clock period definitions<br /> constant clk_period : time := 0.002 ns;<br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: generateur_ligne PORT MAP (<br /> clk => clk,<br /> sl => sl,<br /> fl => fl<br /> );<br /> -- Clock process definitions<br /> clk_process :process<br /> begin<br />clk <= '0';<br />wait for clk_period/2;<br />clk <= '1';<br />wait for clk_period/2;<br /> end process;<br /> <br /> -- Stimulus process<br /> stim_proc: process<br /> begin<br /> -- hold reset state for 100 ns.<br /> wait for 100 ns;<br /> wait for clk_period*10;<br /> -- insert stimulus here <br /> wait;<br /> end process;<br />END;<br />Test_trame<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 14:19:18 03/29/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_trame.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: generateur_trame<br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes: <br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee;<br />USE ieee.std_logic_1164.ALL;<br /> <br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY test_trame IS<br />END test_trame;<br /> <br />ARCHITECTURE behavior OF test_trame IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT generateur_trame<br /> PORT(<br /> sl : IN std_logic;<br /> st : OUT std_logic;<br /> ft : OUT std_logic<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs<br /> signal sl : std_logic := '0';<br /> --Outputs<br /> signal st : std_logic;<br /> signal ft : std_logic;<br /> -- No clocks detected in port list. Replace <clock> below with <br /> -- appropriate port name <br /> <br /> constant clk : time := 0.002 ns;<br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: generateur_trame PORT MAP (<br /> sl => sl,<br /> st => st,<br /> ft => ft<br /> );<br /> -- Clock process definitions<br /> process<br /> begin<br />sl <= '0';<br />wait for clk/2;<br />sl <= '1';<br />wait for clk/2;<br /> end process;<br /> <br /> -- Stimulus process<br /> stim_proc: process<br /> begin<br /> -- hold reset state for 100 ns.<br /> wait for 100 ns; <br /> wait for clk*10;<br /> -- insert stimulus here <br /> wait;<br /> end process;<br />END<br />Test_VGA<br />--------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer:<br />--<br />-- Create Date: 14:42:38 04/10/2011<br />-- Design Name: <br />-- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_top.vhd<br />-- Project Name: VGA<br />-- Target Device: <br />-- Tool versions: <br />-- Description: <br />-- <br />-- VHDL Test Bench Created by ISE for module: top<br />-- <br />-- Dependencies:<br />-- <br />-- Revision:<br />-- Revision 0.01 - File Created<br />-- Additional Comments:<br />--<br />-- Notes:<br />-- This testbench has been automatically generated using types std_logic and<br />-- std_logic_vector for the ports of the unit under test. Xilinx recommends<br />-- that these types always be used for the top-level I/O of a design in order<br />-- to guarantee that the testbench will bind correctly to the post-implementation <br />-- simulation model.<br />--------------------------------------------------------------------------------<br />LIBRARY ieee ; <br />use std.textio.all; <br />USE ieee.std_logic_1164.all ; <br />LIBRARY std; <br />use IEEE.std_logic_textio.all;<br />-- Uncomment the following library declaration if using<br />-- arithmetic functions with Signed or Unsigned values<br />--USE ieee.numeric_std.ALL;<br /> <br />ENTITY test_top IS<br />END test_top;<br /> <br />ARCHITECTURE behavior OF test_top IS <br /> <br /> -- Component Declaration for the Unit Under Test (UUT)<br /> <br /> COMPONENT top<br /> PORT(<br /> uu0 : IN std_logic_vector(3 downto 0);<br /> uu1 : IN std_logic_vector(3 downto 0);<br /> uu2 : IN std_logic_vector(3 downto 0);<br /> uu3 : IN std_logic_vector(3 downto 0);<br /> uu4 : IN std_logic_vector(3 downto 0);<br /> uu5 : IN std_logic_vector(3 downto 0);<br /> uu6 : IN std_logic_vector(3 downto 0);<br /> uu7 : IN std_logic_vector(3 downto 0);<br /> clk_25MHZ : IN std_logic;<br /> sl : OUT std_logic;<br /> st : OUT std_logic;<br /> final : OUT std_logic<br /> );<br /> END COMPONENT;<br /> <br /> --Inputs<br /> signal uu0 : std_logic_vector(3 downto 0) := "1111";<br /> signal uu1 : std_logic_vector(3 downto 0) := "0001";<br /> signal uu2 : std_logic_vector(3 downto 0) := "0000";<br /> signal uu3 : std_logic_vector(3 downto 0) := "0000";<br /> signal uu4 : std_logic_vector(3 downto 0) := "0000";<br /> signal uu5 : std_logic_vector(3 downto 0) := "0000";<br /> signal uu6 : std_logic_vector(3 downto 0) := "0000";<br /> signal uu7 : std_logic_vector(3 downto 0) := "0000";<br /> signal clk_25MHZ : std_logic := '0';<br /> <br /> --Outputs<br /> signal sl : std_logic;<br /> signal st : std_logic;<br /> signal final : std_logic;<br /> -- Clock period definitions<br /> constant clk_25MHZ_period : time := 40 ps;<br />signal a:integer range 66 downto 0 :=0;<br /> signal b:integer range 2 downto 0 :=0;<br />signal deb1:integer range 1 downto 0 :=0;<br />signal deb2:integer range 1 downto 0 :=0;<br />signal deb3:integer range 1 downto 0 :=0;<br />signal deb4:integer range 1 downto 0 :=0;<br />signal deb5:integer range 1 downto 0 :=0;<br />signal deb6:integer range 1 downto 0 :=0;<br />signal deb7:integer range 1 downto 0 :=0;<br />signal deb8:integer range 1 downto 0 :=0;<br />signal d:integer range 8 downto 0 :=1;<br />type TAB is array(0 to 161) of bit;<br />signal T : TAB;<br /> <br />BEGIN<br /> <br />-- Instantiate the Unit Under Test (UUT)<br /> uut: top PORT MAP (<br /> uu0 => uu0,<br /> uu1 => uu1,<br /> uu2 => uu2,<br /> uu3 => uu3,<br /> uu4 => uu4,<br /> uu5 => uu5,<br /> uu6 => uu6,<br /> uu7 => uu7,<br /> clk_25MHZ => clk_25MHZ,<br /> sl => sl,<br /> st => st,<br /> final => final<br /> );<br /> <br /> -- Clock process definitions<br /> clk_25MHZ_process :process<br /> begin <br />clk_25MHZ <= '0';<br />wait for clk_25MHZ_period/2;<br />clk_25MHZ <= '1';<br />wait for clk_25MHZ_period/2;<br />--fixer les debut des ligne pour l'affichage dans notre fichier texte---<br />deb1<=1 after 293.280 ns;<br />deb2<=1 after 325.380 ns;<br />deb3<=1 after 357.460 ns;<br />deb4<=1 after 389.540 ns;<br />deb5<=1 after 421.620 ns;<br />deb6<=1 after 453.700 ns;<br />deb7<=1 after 485.780 ns;<br />deb8<=1 after 517.860 ns;<br /> end process;<br />--ecriture de resultat de notre controleur VGA dans une fichier TXT-----<br />ECRITURE: process(clk_25MHZ,d,deb1,deb2,deb3,deb4,deb5,deb6,deb7,deb8)<br /> variable L: line;<br /> file SORTIES: text open WRITE_MODE is "C:UsersyahyaDesktopresres.txt";<br />begin<br />if(clk_25MHZ' event and clk_25MHZ='1') then<br />if(deb1=1 and d=1)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> <br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=2;<br /> end if;<br /> end if;<br /> end if; <br /> if(deb2=1 and d=2)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> <br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=3;<br /> end if;<br /> end if;<br /> end if;<br /> <br /> if(deb3=1 and d=3)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> <br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=4;<br /> end if;<br /> end if;<br /> end if;<br /> <br /> if(deb4=1 and d=4)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> <br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=5;<br /> end if;<br /> end if;<br /> end if;<br /> if(deb5=1 and d=5)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=6;<br /> end if;<br /> end if;<br /> end if;<br /> if(deb6=1 and d=6)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=7;<br /> end if;<br /> end if;<br /> end if;<br /> <br /> if(deb7=1 and d=7)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if;<br /> <br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); -- écriture de la ligne dans le fichier<br /> d<=8;<br /> end if;<br /> end if;<br /> end if;<br /> if(deb8=1 and d=8)then<br /> if(final='0') then<br /> T(a)<='0';<br /> a<=a+1; <br /> end if; <br /> if(final='1') then<br /> T(a)<='1';<br /> a<=a+1;<br /> b<=1;<br /> end if;<br />if(a=66)then<br />a<=0;<br />if(b=1)then<br />b<=0;<br />for i in 0 to 66 loop<br /> write(L, T(i));<br /> end loop;<br /> writeline(SORTIES, L); <br /> end if;<br /> end if;<br /> end if;<br /> end if;<br />end process ECRITURE;<br />END;<br />Simulation<br />Fichier:<br />Simulation (0, 0, 0, 0, 0, 0, 0, 0):<br />Simulation (F, 1, 0, 0, 0, 0, 0, 0):<br />Rapport technique:<br />Outil de développement utilisé:<br />Logiciel :<br />Xilinx est une entreprise américaine de semi-conducteurs. Inventeur du FPGA, Xilinx fait partie des plus grandes entreprises spécialisées dans le développement et la commercialisation de composants logiques programmables, et des services associés tels que les logiciels de CAO électroniques ; blocs de propriété intellectuelle réutilisables et formation.<br />Langage :<br />VHDL est un langage de description matériel destiné à représenter le comportement ainsi que l'architecture d’un système électronique numérique. Son nom complet est VHSIC  Hardware Description Langage.<br />L'intérêt d'une telle description réside dans son caractère exécutable : une spécification décrite en VHDL peut être vérifiée par simulation, avant que la conception détaillée ne soit terminée. En outre, les outils de conception assistée par ordinateur permettant de passer directement d'une description fonctionnelle en VHDL à un schéma en porte logique ont révolutionné les méthodes de conception des circuits numériques, ASIC ou FPGA.<br />Conclusion:<br />Le but de ce projet est d’exploiter le FPGA Spartan 3 de Xilinx pour faire des applications basiques d’entrée sortie pour passer par la suite à des architectures relativement complexes rassemblant plusieurs composants qu’il faut synchroniser et gérer l’accès à la mémoire.<br />Au cours de ce projet, nous avons fait l’implantation en VHDL de circuits basiques, à savoir le module VGA et ces spécifications. Cependant, nous avons pu valider l’architecture de l’affichage sur écran VGA en utilisant des méthodes de simulations qui peuvent réaliser le même résultat qu’implémenter notre application sur carte. Mais nous sommes familiarisés avec les outils de développement hard.<br />Notre ROM ne contient pas tous les caractères que l'utilisateur peut saisir (restriction sur les HEXA) donc on peut penser à des modules intermédiaires de traitements qui peuvent jouer le rôle de constructeur de nouveaux caractères à partir de notre ROM suite à un nouveau codage que l'on peut définir également.<br />

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