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Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
Talk IT_ Agilent_최석근_111007
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Talk IT_ Agilent_최석근_111007

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  1. Debug your memory systemwith innovative oscilloscope tools Serial Data InfiniiSca Package n+ PrecisionProbe InfiniiSim
  2. Agenda Probing Challenges • De-embed probing effect for accurate measurement • PrecisionProbe for maximizing probe performance  DDR memory SI design phases and testing  Trigger and Measure • Read and Write Data • Eye Diagram measurement Analyze • Make measurement and verify against JEDEC spec. • Run automated measurement to save time.
  3. Key Memory Design ChallengesFaster Data Rate Compact/Small Board Design SI verification  Less probing space - stricter rule in platform design - Signal accessibility is Margin testing limited - System requires more system  Less probing options margin - Conventional probing limits Probe load signal insights - Probe load reduces system margin DDR Speed Transition 3200 SI testing is essential for High speed data rate DDR4Data rate(MT/s) 2133 DDR3 1866 1600 1333 DDR2 1066 800 DDR1 633 667 400 High density board design: 333 200 Where to probe?
  4. Agenda Probing Challenges • De-embed probing effect for accurate measurement • PrecisionProbe for maximizing probe performance  DDR memory SI design phases and testing  Trigger and Measure • Read and Write Data • Eye Diagram measurement Analyze • Make measurement and verify against JEDEC spec. • Run automated measurement to save time.
  5. Probing ChallengesProbing at transmission lines or surface mount components cause signalreflection and other SI issues Probing at the wrong location causes reflection, resulting in non-monotonic edges. This will cause error in your tests such slew rate, setup and hold time Midbus probing measurements. • Non ideal for SI test Load on probing affects the signals on your system as well as what you measure.
  6. How do I probe my memory signals? If vias are accessible: If vias are NOT accessible: For BGA package, probing at For embedded system with the via close to the balls of the tight board spaces and fully DDR DRAM generally gives you populated DIMMthe best results since the JEDEC configuration, BGA probes standard is defined at the balls provide signal access Fully populated DIMM of the DRAM. • No vias to probe BGA probe on DIMM configuration BGA probe on embedded board design Concern with BGA probing: Does BGA probe affects the SI of my board?
  7. BGA probe and Via probing Comparison – Beforede-embedding Flex wing BGA probe withScope optimized BGA probe adapter board Channel 1: Probing at VIA Channel 2: Probing at scope pad point on adapter board Channel 1: Probing at VIA (under the Decrease in DRAM) amplitude Channel 2: Probing at scope pad point Skew caused by delay Skew caused by delay Measurement distorted for SI check: Good for SI check: Signal performance is affected High bandwidth probe allows for using the BGA probe for SI check. How do I simulate an ideal probe?
  8. Oscilloscope de-embed tool - InfiniiSimPhysical layout of a board InfiniiMax probe head Memory Controller DRAM BGA probe Delay Memory Simulation DRAM InfiniiSim - General Purpose 9 Blocks Topology Controller BGA probe S parameter file InfiniiMax probe head s1p file Measurement
  9. Sub-circuit Modeling of DDR BGA probe
  10. Oscilloscope de-embed tool – After de-embeddingChannel 1: Probing at VIA (DQS strobe) Channel 1: At VIA (DQS strobe)Channel 2: Probing at scope pad point Channel 2: At scope adapter board Turn on Bandwidth Limit to 4G on Signal at BGA probe is identical to signal probing at the channel to reduce the ringing via. Measurement result is not compromised by the effect due to high frequency content. probing effect.
  11. DDR3 BGA Probe Optimum BandwidthDDR3 BGA probe is the most commonprobe used in DRAM probingConcerns:• DDR3/4 data rate is increasing to > 2GB/s• Probing effect affects SI measurement DRAM Nominal BW for BGA probe is between 1.5 and 2 GHz before probe correction DDR3 BGA probe DRAM soldered on to with scope pads for DDR3 BGA probe signal accessibility and system test
  12. DDR3 BGA Probe Correction Method1. Apply solder bumps to all of the ground (VSS)connections on the outer rows of the interposer.2. Planarize/Level the solder bumps with a large VSS Signal forpiece of ceramic. correction3. Cut out two pieces of z-axis connectionmaterial, elastomer contact.4. With a microscope, align the BGA probe VSSabove the thru fixture so that only the signal ballcontacts the transmission line and all of theground balls contact ground. DDR BGA probe Solder ball Elastomer Thru fixture Signal contacts VSS (ground) transmission line on contacts ground Signal of interest contacts transmission line on thru thru fixture on thru fixture through elastomer fixture through elastomer
  13. PrecisionProbe Fixture Setup5. Connect the thru fixture to the channelinput of the oscilloscope and feed CAL outfrom the oscilloscope to the thru fixture with Vina SMA cable.6. Solder the probe head to the oscilloscopepads on the BGA probe and connect to oneof the channel inputs.•Vin is defined as the signal at the BGAprobe point while the signal is being loadedby the BGA probe.•Vout is the signal that is output from theBGA probe.•Vout/Vin Correction, the signal at theoutput of the probe is an accuraterepresentation of the signal that currentlyexists, as it is being probed Thru fixture with BGA probe ready for calibration with the scope
  14. PrecisionProbe Calibration6. PrecisionProbe WizardPrecisionProbe and Cable provide an easy to follow guide with its wizard. The wizardtakes you step by step through the set up of the software and ensures that yourmeasurements are taken with the highest signal integrity. Bandwidth control allows you to remove unwanted high frequency noise by providing a filter. Save and Recall the PrecisionProbe calibration result.
  15. Corrected Probe Response Probe Input Impedance Knowing the impedance profile of the probe allows you to estimate the loading of the probe system. The BGA probe response corrected to close to 10GHz
  16. Real Time Eye Diagram MeasurementGDDR5 Write DQ Real Time Eye Diagram Unfold real time eye to find DQ mask violat Without de-embedding De-embed DQ cleared mask test Non de-embed With de-embedding DQ violated mask test
  17. Agenda Probing Challenges • De-embed probing effect for accurate measurement • PrecisionProbe for maximizing probe performance  DDR memory SI design phases and testing  Trigger and Measure • Read and Write Data • Eye Diagram measurement Analyze • Make measurement and verify against JEDEC spec. • Run automated measurement to save time.
  18. SI Measurement with OscilloscopeMemory Design Phases that requires SI testingPrototyping (alpha andbeta) Post Production•SI characterization to • Margin testing for checkingcompare results with compatibility issuesdesign simulation andspecification•Margin testing – varyingtemperature and voltagelevelsSI Validation Tasks (Trigger and Measure) •Read and write data parametric testing •Identify cross talk and ISI failures •Track infrequent events •Jitter characterization •Compliance as per JEDEC standard
  19. How do I trigger on a Read/Write Data DDR2/3 Read and Write Burst (DQS) with Data (DQ) Two distinctive read and write burst patterns DQ DQ Eye diagram S DQ0Idle Read and Writestate data Read and Write eye overlapping
  20. Oscilloscope Zone Qualify Trigger – InfiniiScan+ Zone 1 – Must not Intersect to eliminate Idle State Zone 2 – Must Intersect to trigger on Read DQS to get read Data Zone 2 DQS Zone 1 DQ0 Read DQS is edge aligned with Read DQ
  21. Eye Diagram Test after Read/Write Separation Eye Diagram Test • Allows measurement of eye height and width to measure Data eye height and width • User can also define own mask as per device specification
  22. Mask Test Failure Find failure edge and perform SI measurement DQ Mask Violation • Measure the timing relationship betweenUnfold Eye and navigate to failure position signals (such as Clock and DQS signals) • Measure signal integrity • Rise/fall time • Slew rate • Amplitude • Overshoot/Ringing • Find patterns on DQ signals for ISI related problems.
  23. How do I trigger on a read/write command? GDDR5 Command Truth Table GDDR5 Memory GDDR5 Memory Signals Signals CAS# WE# WCK/WCK# DQREAD: CAS# = Low, WE# = HighWRITE: CAS# = Low, WE# = Low There’s no distinctive read/write burstLoad FIFO, Deselect, Refresh, Self Refresh, patternsPower Down: CAS# = X, WE# = X
  24. Oscilloscope Zone Qualify Trigger – InfiniiScan+Trigger on Write command on GDDR5signals CAS#Trigger Steps:1. Trigger on falling edge of Zone1CAS WE#2. Zone 1 – Must Not Intersect Zone 2to trigger on first burst(CAS=Low) WCK/WCK#3. Zone 2– Must Intersect totrigger on WE = Low (writecommand) DQ4. Zone 3 – Must intersect to Zone 3trigger on Write data transitionand to eliminate Hi state ofdata caused by othercommands – Self refresh,Power Down..etc Use only 4 channels to do read/write command trigger
  25. Oscilloscope Zone Qualify Trigger – InfiniiScan+Determine the Write latency of the GDDR5 writecommand CAS# Zone1 WE# Zone 2 WCK/WCK# DQ Write Latency = 4 CK cycles Or 8 WCK cycles Zone 3 Quickly determine the read/write latencies of the DRAM with Command trigger
  26. Measurement – Eye DiagramGDDR5 eye diagram measurement to determine data validwindow A successful read/write separation enables data valid window measurement on multiple edges
  27. Trigger Signal Pattern On screen – InfiniiScan + Potential SI problem due to reflection DQ0 Concern: There’s only one signal, DQ0 available for probing, I can see the potential issue on screen, can I trigger?
  28. Measurement – Real Time Eye Diagram Turn on Real-Time eye to ensure Zone 1: Must data valid window spec is not intersect to compromised: trigger on signal with Reflection due to imperfect SI issue only termination found. DQ0 Eye Width and Height measurement
  29. Track Specific Pattern with InfiniiScan Zone Trigger Trigger data “010000101010” with InfiniiScan 1 2 Allows more robust data pattern test: • Measure SI (rise time, overshoot/undershoo t amplitude) during rigorous data 3 4 transitions. DQ = “010000101010” Group/Presentation Title Agilent RestrictedPage 29 Month ##, 200X
  30. Agenda Probing Challenges • De-embed probing effect for accurate measurement • PrecisionProbe for maximizing probe performance  DDR memory SI design phases and testing  Trigger and Measure • Read and Write Data • Eye Diagram measurement Analyze • Make measurement and verify against JEDEC spec. • Run automated measurement to save time.
  31. Analyze Make measurement and verify against JEDEC specification JEDEC spec: DDR3 Write Pre-amble width - tWPRE DDR3 Write Pre-amble width - tWPRE JEDEC spec: DDR3 Data Setup Time- tDS DDR3 Data Setup Time- tDSConcern with making manualmeasurements:Tedious and time consuming, repeatabilityissues
  32. Analyze with Automated Compliance TestPerform Electrical, Clock and Timing tests HTML Test Report with measurement details Automated tDS test with measurement result indicating pass/fail status as per JEDEC spec
  33. AC150/AC175 Levels Setup Automatically load AC level test limits for different speed grade Example: The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV JEDEC 3E tIS and tIH test limits
  34. Custom Derating Table for Characterization DDR Derated Command/Address and Data Tests Custom Derating table supportExample: tIS (total setup time) = tIS(base) + ΔtISNote: ΔtIS is determined from the derating table Editable DeratingAndBaseTable.dat
  35. Automated Threshold Settings for DDRCharacterization “Set” automatically calculate the Vref and VTT voltages Wizard for voltage threshold settings Measurement threshold applies to Single Ended/Differential Input/Output signals The intuitive GUI in the automated compliance app allows for measurement of non-standard DDR voltage levels. For example, 1.25V.
  36. Multi-Burst Measurement for Statistical Analysis 4 sets of bursts found in one single acquisition Multi-burst measurement allows measurement of multiple bursts in a single acquisition or multi acquisition for statistical analysis – Min, Max, Mean, Stdev
  37. Margin testing with Compliance TestCompliance test report enables margin reporting Check for compatibility and margin allowance • Use a standard measurement methodology for repetitive testing with variance of temperature and voltage. • Compile test result/report on margin for finding optimal performance.
  38. Testing eMMC with User Defined Application Create your own eMMC Compliance Test with UDA 1. Users Download the FREE development environment Processor Baseband + Application 2. User install the DE on their scope or PC and develop their UDA 3. Application is then generated and installed ROM RAM on the scope eMMC LPDDR2 4. Application then runs on the oscilloscope with “Run License” and test report is generated
  39. eMMC JEDEC spec as Reference Sequence of SCPI commands to perform Clock timing testseMCC spec from JESD84-A441
  40. SummaryProbing Technologies • DRAM BGA probe used when vias are not accessible • InfiniiSim and PrecisionProbe for maximizing probe performance SI Testing/Characterization withOscilloscope InfiniiScan+ • Read and Write Data for eye diagram measurement  DDR automated compliance app Run automated measurement to save time. Additional features to perform statistical analysis and margin testing for characterization purposes • Multi-burst measurement • Customized Derating table • Automated voltage threshold setting • UDA
  41. Memory Oscilloscope Measurement Tool DRAMDDR Compliance DDR Fixtures Software and Probes Packages(clock, electricaland timing tests) InfiniiScan InfiniiSim Serial Data PrecisionProbe + Package 9000/90000 series Oscilloscope

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