RMO3C-2  RFIC, 3-5 June 2007, Honolulu, Hawaii   Frequency Synthesizer & FSK Modulator for IEEE 802.15.4 Based Application...
Outline <ul><li>FSK Modulation Systems </li></ul><ul><li>System Design </li></ul><ul><ul><li>Modulation System </li></ul><...
FSK modulation with Fractionnal PLL FSK Modulation <ul><li>Compromise : lock time and spurious </li></ul><ul><li>For data ...
FSK Modulation 2 Combined PLL with mixer <ul><li>Output spurious </li></ul><ul><li>Lock time greater than single loop </li...
<ul><li>FSK Modulation </li></ul><ul><li>System Design </li></ul><ul><ul><li>Modulation system </li></ul></ul><ul><ul><li>...
<ul><li>Context </li></ul><ul><ul><li>Home RF application (IEEE 802.15.4 – based), WPAN  </li></ul></ul><ul><ul><li>STMicr...
<ul><li>Reception mode </li></ul><ul><ul><li>2.5 Volts supply </li></ul></ul><ul><ul><li>Bandwidth channels: 2.404GHz to 2...
Proposed FSK Modulation <ul><li>Transmission mode </li></ul><ul><ul><li>Open loop modulation     No  PLL   BW sensitivity...
VCO Design constraints  Single VCO  for lower cost <ul><li>VCO Requirements </li></ul><ul><ul><li>Phase noise  </li></ul><...
VCO Design  <ul><li>Multi-controlled Ring-VCO   </li></ul><ul><ul><li>Temperature control  </li></ul></ul><ul><ul><li>Freq...
<ul><li>FSK Modulation </li></ul><ul><li>System Design </li></ul><ul><ul><li>Modulation system </li></ul></ul><ul><ul><li>...
VCO - Performances  -12dBm -98dBc/Hz 73ppm/°C 0.13-µm CMOS VDD = 2.5 V Vctrl = 1.25 V F vco  = 2.487 GHz 1291ppm/°C VCO TE...
VCO - Performances  <ul><li>VCO Characteristics </li></ul><ul><ul><li>Technology = 0.13-µm CMOS </li></ul></ul><ul><ul><li...
<ul><li>Transient response </li></ul><ul><ul><li>Reception mode  (110-µs) </li></ul></ul><ul><ul><li>Transmission mode  </...
   Experimental results : Synthesizer  <ul><li>Measurement conditions  (Reception mode) </li></ul><ul><ul><li>VDD = 2.5V (...
0V    Sleep Mode 2.5V    Synthesizer  Mode Channel 10 Channel 5 Locking Time from sleep mode Max Locking Time from sleep...
PLL Measurements : Lock Time  <ul><li>Measurement conditions  (Reception mode) </li></ul><ul><ul><li>Input reference frequ...
Conclusion & Perspectives <ul><li>High performance VCO </li></ul><ul><li>Low phase noise VCO    -98 dBc/Hz at 1 MHz </li>...
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IEEE_RFIC 2007

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Presentation of the work published in RFIC 2007 Conference. PLL and FSK modulator design in 130nm-CMOS

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  • Good morning, I am happy to present you this work, titled A Fully Integrated 2.45GHz Freq Synthesizer &amp; FSK Modulator. This work is performed within the L2MP and the society STMicroelectronics. This collaboration project is dedicated to the design of STMicroelectronics Proprietary system belonging the IEEE 802.15.4 standard.
  • Transcript of "IEEE_RFIC 2007 "

    1. 1. RMO3C-2 RFIC, 3-5 June 2007, Honolulu, Hawaii Frequency Synthesizer & FSK Modulator for IEEE 802.15.4 Based Applications W. Rahajandraibe , L. Zaïd, V. Cheynet de Beaupré and G. Bas L2MP – University of Provence / STMicroelectronics FRANCE
    2. 2. Outline <ul><li>FSK Modulation Systems </li></ul><ul><li>System Design </li></ul><ul><ul><li>Modulation System </li></ul></ul><ul><ul><li>VCO Design </li></ul></ul><ul><li>Results & Discussion </li></ul><ul><li>Conclusion </li></ul>
    3. 3. FSK modulation with Fractionnal PLL FSK Modulation <ul><li>Compromise : lock time and spurious </li></ul><ul><li>For data rate of few Mbits/s </li></ul><ul><li> attenuation </li></ul><ul><li>Matching requirements </li></ul><ul><li> process variation </li></ul>Two points  FSK modulation <ul><li>No PLL attenuation </li></ul><ul><li>VCO variation </li></ul><ul><ul><li>Gain control & compensation </li></ul></ul><ul><ul><li>Temperature variation </li></ul></ul><ul><ul><li>Process variation </li></ul></ul>High Frequency DATA +
    4. 4. FSK Modulation 2 Combined PLL with mixer <ul><li>Output spurious </li></ul><ul><li>Lock time greater than single loop </li></ul><ul><li>High area & power consuming </li></ul><ul><li>Modulation flexibility </li></ul><ul><li>Complex architecture </li></ul><ul><li>High area </li></ul><ul><li>Power consuming </li></ul>I – Q Modulator
    5. 5. <ul><li>FSK Modulation </li></ul><ul><li>System Design </li></ul><ul><ul><li>Modulation system </li></ul></ul><ul><ul><li>VCO Design </li></ul></ul><ul><li>Results & Discussion </li></ul><ul><li>Conclusion </li></ul>
    6. 6. <ul><li>Context </li></ul><ul><ul><li>Home RF application (IEEE 802.15.4 – based), WPAN </li></ul></ul><ul><ul><li>STMicroelectronics proprietary system </li></ul></ul>Proposed FSK Modulation <ul><li>Design challenges </li></ul><ul><ul><li>Both frequency synthesizer & FSK modulator in transmission mode </li></ul></ul><ul><ul><li>Low cost  reduction of the area </li></ul></ul><ul><ul><li>Attractive solution with a decreased complexity </li></ul></ul><ul><ul><li>STMicroelectronics 130nm CMOS technology </li></ul></ul>Tx0 Rx Tx1 2 MHz 2 MHz 8MHz 10 transmission channels 2.406 GHz 2.478 GHz 8 MHz Channel
    7. 7. <ul><li>Reception mode </li></ul><ul><ul><li>2.5 Volts supply </li></ul></ul><ul><ul><li>Bandwidth channels: 2.404GHz to 2.488GHz (> 80MHz) </li></ul></ul><ul><ul><li>10 channels of 8 MHz </li></ul></ul><ul><ul><li>Short Time to Lock  150 µs </li></ul></ul>Proposed FSK Modulation <ul><li>Multi-function PLL : </li></ul><ul><li>Single conv. receiver : Fr. synth </li></ul><ul><li>Direct conv. transmit. : FSK </li></ul>
    8. 8. Proposed FSK Modulation <ul><li>Transmission mode </li></ul><ul><ul><li>Open loop modulation  No PLL BW sensitivity </li></ul></ul><ul><ul><li>2MHz step size  30 frequencies </li></ul></ul><ul><ul><li>VCO frequency drift !! </li></ul></ul>10pF 10pF 1 1 2 2 <ul><li>Modulation procedure </li></ul><ul><ul><li>Step 1 : Calibration phase (closed loop)  150µs </li></ul></ul><ul><ul><li>Step 2 : Modulation phase (open loop)  1 to 11ms </li></ul></ul>Data : 1Mbits/s Transmission cycle ≤ 10 ms Tx0 Rx Tx1 2 MHz 2 MHz
    9. 9. VCO Design constraints Single VCO for lower cost <ul><li>VCO Requirements </li></ul><ul><ul><li>Phase noise </li></ul></ul><ul><ul><ul><li>- 89dBc/Hz @ 1MHz offset (BER =10 -3 ) </li></ul></ul></ul><ul><ul><li>Use of low gain VCO  50 MHz/V </li></ul></ul><ul><ul><li>Cover the total Bandwidth </li></ul></ul><ul><ul><li>Temperature & process variation </li></ul></ul><ul><ul><li>Low power, low area </li></ul></ul>80 MHz BAND Required VCO input voltage (V) Output frequency (GHz) VCON VCO3 VCO2 VCO1 Single VCO ( 0 V to 2.5 V )
    10. 10. VCO Design <ul><li>Multi-controlled Ring-VCO </li></ul><ul><ul><li>Temperature control </li></ul></ul><ul><ul><li>Frequency operating range control </li></ul></ul><ul><ul><li>Multi-channel </li></ul></ul><ul><ul><li>Low gain </li></ul></ul>2.4 GHz Buffer 2.4 GHz VCO Delay #1 Delay #2
    11. 11. <ul><li>FSK Modulation </li></ul><ul><li>System Design </li></ul><ul><ul><li>Modulation system </li></ul></ul><ul><ul><li>VCO Design </li></ul></ul><ul><li>Results & Discussion </li></ul><ul><li>Conclusion </li></ul>
    12. 12. VCO - Performances -12dBm -98dBc/Hz 73ppm/°C 0.13-µm CMOS VDD = 2.5 V Vctrl = 1.25 V F vco = 2.487 GHz 1291ppm/°C VCO TEST CHIP VDD OFF CTRL OUTN OUTP C1 C2 C3 C4
    13. 13. VCO - Performances <ul><li>VCO Characteristics </li></ul><ul><ul><li>Technology = 0.13-µm CMOS </li></ul></ul><ul><ul><li>Supply = 2.5 V </li></ul></ul><ul><ul><li>Low area = 110µm×110 µm </li></ul></ul><ul><ul><li>Low phase noise = -98 dBc/Hz @ 1 MHz </li></ul></ul><ul><ul><li>Low frequency drift (best case) = 73 ppm/°C </li></ul></ul><ul><ul><li>Settling time = 7 ns </li></ul></ul>90MHz/V 30MHz/V 55MHz/V
    14. 14. <ul><li>Transient response </li></ul><ul><ul><li>Reception mode (110-µs) </li></ul></ul><ul><ul><li>Transmission mode </li></ul></ul><ul><ul><ul><li>TX0  120-µs </li></ul></ul></ul><ul><ul><ul><li>TX1  150-µs </li></ul></ul></ul>PLL - Performances lock signal Vctrl <ul><li>Modulation </li></ul><ul><ul><li>Mod. capacitor leakage </li></ul></ul><ul><ul><ul><li>12µV/ms ( Δ F=6 kHz << 510kHz) </li></ul></ul></ul>RX TX Tx0 Tx1 Rx Lock <ul><li>Power Saving </li></ul><ul><ul><li>Sleep mode : no consumption </li></ul></ul><ul><ul><li>RX : Energy = 308µAh </li></ul></ul><ul><ul><li>TX : Energy = 193µA ( gain of 37% ) </li></ul></ul>PLL + MOD CIRC PLL MOD CIRCUIT RX TX
    15. 15.   Experimental results : Synthesizer <ul><li>Measurement conditions (Reception mode) </li></ul><ul><ul><li>VDD = 2.5V (Tnom = 30°C) </li></ul></ul><ul><ul><li>Input reference frequency: 8.357MHz (process variation) </li></ul></ul><ul><li>Results </li></ul><ul><ul><li>Current consumption= 34mA </li></ul></ul><ul><ul><li>Minimum synthesized frequency = 2.459 GHz </li></ul></ul><ul><ul><li>Maximum synthesized frequency = 2.632 GHz  </li></ul></ul>Measured Synthesized Frequency 8MHz step Frequency synthesizer & FSK modulator 980µm 220µm BUF& FILTER Digital CAPACITOR (Loop Filter) VCO + CP MOD CIRC
    16. 16. 0V  Sleep Mode 2.5V  Synthesizer Mode Channel 10 Channel 5 Locking Time from sleep mode Max Locking Time from sleep mode 100µs PLL Measurements : Lock Time <ul><li>Measurement conditions (Reception mode) </li></ul><ul><ul><li>Input reference frequency: 8.357MHz </li></ul></ul><ul><ul><li>VDD = 2.5V </li></ul></ul><ul><ul><li>The RX signal is controlled by a 600Hz frequency </li></ul></ul>Synthesizer Mode Isupply = 34-mA Sleep Mode Isupply = 300-µA Sleep Mode Sleep Mode Synthesizer RX lock 215µs
    17. 17. PLL Measurements : Lock Time <ul><li>Measurement conditions (Reception mode) </li></ul><ul><ul><li>Input reference frequency: 8.357MHz </li></ul></ul><ul><ul><li>VDD = 2.5V </li></ul></ul>Lock time from channel 1 to 2   36 µs 36µs Worst case: ch1 to ch10 Channel 1 Channel 2 <ul><li>Results </li></ul><ul><ul><li>fast lock time between channels </li></ul></ul>
    18. 18. Conclusion & Perspectives <ul><li>High performance VCO </li></ul><ul><li>Low phase noise VCO  -98 dBc/Hz at 1 MHz </li></ul><ul><li>Low VCO drift  73 ppm/°C (best case) </li></ul><ul><li>Low VCO gain with frequency control  30 MHz/V to 55 MHz/V </li></ul><ul><li>Non linearity at high voltage control of the VCO (2  2.5 V) </li></ul><ul><li>VCO  Frequency Process Spread </li></ul><ul><li>Frequency Synthesizer and FSK modulator </li></ul><ul><li>Open Loop FSK modulator with a calibration phase </li></ul><ul><li>2.5 V - 2.45GHz synthesizer - 0.13 µm CMOS technology </li></ul><ul><li>Low cost, low power design (34 mA and 0.3 mA in sleep mode) </li></ul><ul><li>Simulated locking time (reception) 110 µs </li></ul><ul><li>Measured locking time (reception) : 215 µs (worst case) </li></ul><ul><li>Simulated locking time (transmission)  160 µs </li></ul>

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