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# IS 151 Lecture 10

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IS 151 Lecture 10 - UDSM - 2013/2014

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### IS 151 Lecture 10

1. 1. Flip-flops and Related Devices • Multivibrators are electronic circuits used to implement a variety of simple two-state systems such as oscillators, timers and flip-flops. • Multivibrators are applied in a variety of systems where square waves or timed intervals are required • Oscillators – systems that provide a repetitive variation (in time) of some measure about a central value. E.g. AC power, a swinging pendulum IS 151 Digital Circuitry 1
2. 2. Flip-flops and Related Devices • Multivibrator logic devices are of three categories: • Bistables – 2 stables states • Monostables – 1 stable state • Astables – no stable state IS 151 Digital Circuitry 2
3. 3. Flip-flops and Related Devices • Astable – the circuit is not stable in either state – it continuously oscillates from one state to the other. • Monostable – one of the states is stable, but the other is not – the circuit will flip into the unstable state for a determined period, but will eventually return to the stable state • Bistable – the circuit will remain in either state (stable or unstable) indefinitely. The circuit can be flipped from one state to the other by an external event or trigger. IS 151 Digital Circuitry 3
4. 4. Bistables • Bistables are of two types – The latch – The flip-flop • Bistables have two stable states – SET – RESET – They can retain either of these states indefinitely, which makes them useful for storage purposes • Latches and flip-flops differ in the way in which they change from one state to another IS 151 Digital Circuitry 4
5. 5. Latches • A type of bistable storage device, can be in either of two states (SET, RESET) • The S-R (SET-RESET) latch – An active-HIGH input S-R latch is formed with 2 cross-coupled NOR gates IS 151 Digital Circuitry 5
6. 6. Latches • An active-LOW input S-R latch – Is formed with two cross-couples NAND gates – The output of each gate is connected to an input of the opposite gate – Produces the regenerative feedback – characteristic of all multivibrators IS 151 Digital Circuitry 6
7. 7. Latches • The S’-R’ latch (with negative OR equivalents used for the NAND gates) IS 151 Digital Circuitry 7
8. 8. Latches • Assumption: – Both inputs and the Q output are HIGH – Q is connected as input to G2, and when R’ input it HIGH, the output of G2 (Q’) is LOW; which is input to G1, ensuring that its output (Q) is HIGH – When Q is HIGH, the latch is in the SET state – When R’ input is LOW and S’ is HIGH, the output of G2 is HIGH – Q’ output (HIGH) is coupled back to the input of G1, since S’ is HIGH, the output of G1 is LOW – When the Q output is LOW, the latch is in the RESET state, and the latch remains there until a LOW is applied to the S’ input IS 151 Digital Circuitry 8
9. 9. Latches • The outputs of a latch are always complements of each other; when Q = HIGH, Q’ = LOW and vice versa • Invalid condition: occurs when LOWs are applied to both S’ and R’ at the same time • As long as the LOW levels are simultaneously held in the inputs, both Q and Q’ outputs are forced HIGH, violating the basic complementary operation of the output IS 151 Digital Circuitry 9
10. 10. Latches • Modes of the S-R latch (SET, RESET, No Change, Invalid Condition) Inputs Outputs Comments S’ R’ Q Q’ 1 1 NC NC No change 0 1 1 0 Latch SET 1 0 0 1 Latch RESET 0 0 1 1 Invalid condition IS 151 Digital Circuitry 10
11. 11. Latches • Logic symbols for the S-R latch S Q S’ S Q R Q’ R’ R Q’ Active-HIGH input S-R Latch Active-LOW input S’-R’ Latch IS 151 Digital Circuitry 11
12. 12. Latches – Examples • If the S’-R’ waveforms are applied to the inputs of the latch, determine the waveform that will be observed on the Q output. Assume that Q is initially LOW S’ R’ Q IS 151 Digital Circuitry 12
13. 13. Latches – Examples • How to obtain the output (Q) waveform – use the latch’s truth table to obtain Q for the given S’ and R’ inputs • Initially, Q is 0 • S’R’ • 11 = No change • 10 = Reset • 01 = Set R’ Q 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 1 IS 151 Digital Circuitry S’ 1 1 13
14. 14. The Gated S-R latch • Requires an ENABLE, EN, input • The S and R inputs control the state to which the latch will go when a HIGH level is applied to the EN input • The latch will not change until EN is HIGH, but as long as it remains HIGH, the output is controlled by the state of S and R inputs • Invalid state occurs when both S and R are simultaneously HIGH – as opposed to the normal S-R where invalid state occurs when both S and R inputs are LOW at the same time IS 151 Digital Circuitry 14
15. 15. The Gated S-R latch • Logic diagram • Logic symbol S Q EN Q’ R IS 151 Digital Circuitry 15
16. 16. The Gated S-R latch • Example: determine the Q output waveform if the inputs shown are applied to the gated S-R latch that is initially RESET (Q = 0) S R EN Q IS 151 Digital Circuitry 16
17. 17. The Gated S-R latch • Anytime S is HIGH and R is LOW, a HIGH on the EN SETS the latch (Q = 1) • Anytime S is LOW and R is HIGH, a HIGH on the EN RESETS the latch (Q = 0) – S R Q – 1 1 Invalid – 0 1 Reset (0) – 1 0 Set (1) – 0 0 No Change R EN Q 1 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 0 1 IS 151 Digital Circuitry S 0 1 1 17
18. 18. The Gated S-R latch • Exercise – Determine the Q output of the gated S-R latch if the S and R inputs are inverted. The latch is initially RESET IS 151 Digital Circuitry 18
19. 19. • End of lecture IS 151 Digital Circuitry 19
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