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VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
 

VLSI Physical Design Flow(http://www.vlsisystemdesign.com)

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  • Tphl need not be equal to tplh …… highlight this factTo make this equal we may tweak the Pmos width in std cell design … Lp ~ 2 Ln
  • Show the ckt before and after ECO and highlight the change !!

VLSI Physical Design Flow(http://www.vlsisystemdesign.com) VLSI Physical Design Flow(http://www.vlsisystemdesign.com) Presentation Transcript

  • Kunal Promode Ghosh M.Tech (IIT Bombay)9/11/2012 http://www.vlsisystemdesign.com/ 1
  • Physical Design (PD) Flow• Physical Design Flowchart (What to do ?, Why to do ? And How to do ? in Physical Design)• Physical Design Learning Methodology1. Physical Design Flow (What to do?)2. Fundamentals Related to Flow (Why to do?)3. PD Tools Introduction (How to do?) 9/11/2012 www.vlsisystemdesign.com 2
  • Physical Design (PD) Flow9/11/2012 www.vlsisystemdesign.com 3
  • 9/11/2012 www.vlsisystemdesign.com 4
  • What to do?1. A core is the section of the chip where the fundamental logic of Hcore Hdie the design is placed.2. A ‘die’, is small semiconductor material specimen on which the fundamental circuit is fabricated. Die Wcore Core Wdie Define Width & Height of Core & Die 9/11/2012 www.vlsisystemdesign.com 5
  • What to do?1. The preplaced cells are the critical cells, related to clocks, viz. Clock Mux clock buffers, clock mux, etc. and Output also few other cells such as Clock RAMs, ROMs etc. Buffer Input2. These cells are placed into core Clock before placement and routing Buffer Die stage, and hence are called preplaced cells. Core Define Locations of Pre-Placed cells 9/11/2012 www.vlsisystemdesign.com 6
  • What to do? Decap Decap Decap1. A decoupling capacitor is used to decouple the critical cells from Clock Mux Decap main power supply, in order to Decap Decap Output protect the cells from the Decap Clock disturbance occurring in the Decap Buffer power distribution lines and Decap Decap Decap Input source Clock Buffer Die2. The purpose of using decoupling Decap capacitors is to deliver required current to the gates during Core switching De-Coupling Capacitors surrounding Pre-placed Cells 9/11/2012 www.vlsisystemdesign.com 7
  • What to do? Decap Decap Decap1. While drawing any circuit Clock Mux Decap on paper, we have only one Decap Decap vdd at the top and one Decap Output Clock vss at the bottom Decap Buffer Decap Decap Decap2. But on a chip, it becomes Input necessary to have a grid Clock Buffer Die structure of power, with Decap more than one vdd and vss Core Power Planning 9/11/2012 www.vlsisystemdesign.com 8
  • What to do? Decap Decap Decap1. While drawing any circuit Clock Mux Decap on paper, we have only one Decap Decap vdd at the top and one Decap Output Clock vss at the bottom Decap Buffer Decap Decap Decap2. But on a chip, it becomes Input necessary to have a grid Clock Buffer Die structure of power, with Decap more than one vdd and vss Core Power Planning Vdd Vss 9/11/2012 www.vlsisystemdesign.com 9
  • What to do? Decap Decap Decap1. While drawing any circuit Clock Mux Decap on paper, we have only one Decap Decap vdd at the top and one Decap Output Clock vss at the bottom Decap Buffer Decap Decap Decap2. But on a chip, it becomes Input necessary to have a grid Clock Buffer Die structure of power, with Decap more than one vdd and vss Core Power Planning Vdd Vss 9/11/2012 www.vlsisystemdesign.com 10
  • What to do? X X X X X Decap X X X X X Decap Decap1. While drawing any circuit X X Clock Mux X X X Decap on paper, we have only one Decap Decap X X X X X vdd at the top and one Decap Output X X X X X Clock vss at the bottom X DecapX X Buffer X X Decap Decap Decap2. But on a chip, it becomes X Input X X X X necessary to have a grid Clock X X X X X Buffer Die structure of power, with X X X X X Decap more than one vdd and X X X X X vss Core Vdd Power Planning Vss 9/11/2012 www.vlsisystemdesign.com 11
  • What to do?1. The space between core and die is reserved for pin placement. For eg. an 8085 has around 40 pins viz. reset, AD0, AD1, etc.2. The clock pins are wider compared to other pins on the chip, as it drives most of the logic inside the chip. 9/11/2012 www.vlsisystemdesign.com 12
  • What to do?1. To avoid the placement of cells by placement tools, in the area between core and die (which is reserved for pin placement), it needs to be blocked by logical cell placement blockages 9/11/2012 www.vlsisystemdesign.com 13
  • What to do?1. The ‘Clk’ should be distributed to all flops in such a way that the skew is minimal2. ‘Skew’ is the relative delay between clocks reaching at each flop on chip. 9/11/2012 www.vlsisystemdesign.com 14
  • What to do?9/11/2012 www.vlsisystemdesign.com 15
  • What to do?9/11/2012 www.vlsisystemdesign.com 16
  • What to do?9/11/2012 www.vlsisystemdesign.com 17
  • What to do?9/11/2012 www.vlsisystemdesign.com 18
  • What to do? 1. Engineering Change Order (ECO) is the process of modifying the PNR netlist in order to meet timing (i.e. setup, hold, transition and max_capacitance) requirements 2. For eg. if theres a setup violation in the design, it implies that a combinational path has large delay than required. In this case, we need to reduce the delay by upsizing cell, which reduces resistance, in turn, reduces RC delay of the path. 3. Refer to diagrams in following slides to understand how to modify delay of cells. Inverter has been taken as an example.9/11/2012 www.vlsisystemdesign.com 19
  • What to do?9/11/2012 www.vlsisystemdesign.com 20
  • What to do?9/11/2012 www.vlsisystemdesign.com 21
  • What to do?9/11/2012 www.vlsisystemdesign.com 22
  • What to do? Propagation Delay of inverter TPHL need not be equal to TPLH9/11/2012 www.vlsisystemdesign.com 23
  • What to do?9/11/2012 www.vlsisystemdesign.com 24
  • What to do?9/11/2012 www.vlsisystemdesign.com 25
  • What to do?9/11/2012 www.vlsisystemdesign.com 26
  • What to do?9/11/2012 www.vlsisystemdesign.com 27
  • 9/11/2012 www.vlsisystemdesign.com 28
  • Why to do?1. The abstract level behavioral description of the processor is written using an RTL program.2. Large designs (e.g. microprocessor in our case) are usually synthesized into small modules.3. These modules are the basic building blocks of a microprocessor e.g. memory unit, adder/subtractor (ALU) unit, multiplexer unit, etc. 9/11/2012 www.vlsisystemdesign.com 29
  • Why to do?1. The arrangement shown in left occupies minimum area, whereas the one on the right occupies larger area on chip, and hence facilitates the user to add more blocks (i.e. additional functionality) in to the chip.2. If, the specifications demands for minimum area, the left arrangement is selected, whereas, if the specification demands decent area as well as additional functionality, the second arrangement is selected. 9/11/2012 www.vlsisystemdesign.com 30
  • Why to do?1. Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit.2. Noise margin does makes sure that any signal which is logic 1 with finite noise added to it, is still recognised as logic 1 and not logic 0. 9/11/2012 www.vlsisystemdesign.com 31
  • Why to do? NML (NOISE MARGIN low) = VIL - VOL = Vss - 0 = Vss‘ NMH (NOISE MARGIN high) = VOH - VIH = Vdd - Vdd9/11/2012 www.vlsisystemdesign.com 32
  • Why to do?1. If the wires were ideal, i.e. zero resistance, zero inductance and infinitely short, thus no issue of power distribution 9/11/2012 www.vlsisystemdesign.com 33
  • Why to do?1. Consider capacitance to be zero for the discussion. Rdd, Rss, Ldd and Lss are well defined values.2. During switching operation, the circuit demands switching current i.e. peak current (IPEAK).3. Now, due to the presence of Rdd and Ldd, there will be a voltage drop across them and the voltage at Node A would be Vdd instead of Vdd. 9/11/2012 www.vlsisystemdesign.com 34
  • Why to do? Switching Activity of CMOS Circuit.9/11/2012 www.vlsisystemdesign.com 35
  • Why to do?9/11/2012 www.vlsisystemdesign.com 36
  • Why to do?1. When input of the inverter switches from logic 1 to logic 0, output of inverter should switch from logic 0 to logic 1.2. This essentially means that the output capacitance of inverter should charge till the supply voltage Vdd.3. But if Vdd goes below the noise margin, due to Rdd and Ldd, the logic 1 at the output of inverter wont be detected Vdd - Vdd = Ipeak*Rdd + Ldd * (dI/dt) as logic 1 at the input of the circuit following the inverter. 9/11/2012 www.vlsisystemdesign.com 37
  • Why to do?Solution1. Keep Rdd and Rss minimum by increasing width of wire.2. Keep peak current Ipeak and change in current (dI/dt) as small as possible.Icap = CL * dV / dtIpeak = CL * (Vdd – 0) / (tr - 0)Ipeak = CL * (Vdd) / (tr )dI/dt = CL * Vdd / tr23. Limit the rise time (tr). If a circuit could run at 500 ps, its unnecessary to run the circuit at 300 ps. The largest possible value of tr should be Vdd - Vdd = Ipeak*Rdd + Ldd * (dI/dt) selected. 9/11/2012 www.vlsisystemdesign.com 38
  • Why to do?1. Addition of Decoupling Capacitor in parallel with the circuit2. Everytime the critical cell (in above daigram,an inverter) switches, it draws current from Cd , whereas, the RL network is used to replenish the charge into Cd 9/11/2012 www.vlsisystemdesign.com 39
  • Why to do?1. The ‘Clk’ should be distributed to all flops in such a way that the skew is minimal2. ‘Skew’ is the relative delay between clocks reaching at each flop on chip. 9/11/2012 www.vlsisystemdesign.com 40
  • Why to do?9/11/2012 www.vlsisystemdesign.com 41
  • Why to do?9/11/2012 www.vlsisystemdesign.com 42
  • Why to do?9/11/2012 www.vlsisystemdesign.com 43
  • Why to do?9/11/2012 www.vlsisystemdesign.com 44
  • Why to do?9/11/2012 www.vlsisystemdesign.com 45
  • Why to do?9/11/2012 www.vlsisystemdesign.com 46
  • Why to do?9/11/2012 www.vlsisystemdesign.com 47
  • Why to do?9/11/2012 www.vlsisystemdesign.com 48
  • Why to do?In deep sub-micron technology (i.e. <130nm) and below, the lateral capacitancebetween nets/wires on silicon, becomes much more dominant than the interlayercapacitance.9/11/2012 www.vlsisystemdesign.com 49
  • Why to do?9/11/2012 www.vlsisystemdesign.com 50
  • Why to do?9/11/2012 www.vlsisystemdesign.com 51
  • Why to do?1. The disturbance at A can potentially cause a disturbance at V, because of the mutual coupling capacitance.2. If the disturbance at V crosses noise threshold of the receiving gate R, then it may change the logic at the output of R 9/11/2012 www.vlsisystemdesign.com 52
  • Why to do?9/11/2012 www.vlsisystemdesign.com 53
  • Why to do?1. If both A and V nodes have signal switching event at the same time interval, then, due to noise induced by signal transition at agressor A, a change in the timing instant of the signal transition occurs at V‘2. Due to this, the propagation delay of the driver D increases by dt amount of time, thus increasing the overall propagation delay of the circuit, which might lead to potential setup violation. 9/11/2012 www.vlsisystemdesign.com 54
  • Why to do? Crosstalk Modeling and Analysis9/11/2012 www.vlsisystemdesign.com 55
  • Why to do? Crosstalk Modeling and Analysis9/11/2012 www.vlsisystemdesign.com 56
  • Why to do? Crosstalk Modeling and Analysis9/11/2012 www.vlsisystemdesign.com 57
  • Why to do? Crosstalk Modeling and Analysis9/11/2012 www.vlsisystemdesign.com 58
  • Why to do? Crosstalk Modeling and Analysis9/11/2012 www.vlsisystemdesign.com 59
  • Why to do? Crosstalk Modeling and Analysis Therefore, we have 3 solution. 1) Controlling Peak Voltage (Vp)9/11/2012 www.vlsisystemdesign.com 60
  • Why to do? Crosstalk Modeling and Analysis 2) Tuning Pulse Width9/11/2012 www.vlsisystemdesign.com 61
  • Why to do? Crosstalk Modeling and Analysis 3) Shielding9/11/2012 www.vlsisystemdesign.com 62
  • Why to do? The common component between the flip-flops X, Y and Z is the clock.9/11/2012 www.vlsisystemdesign.com 63
  • Why to do?1. Correctness of the system can be judged by tracing each Sender - Receiver pair.2. Assume, identical clock goes to both and theres some delay between Sender and Receiver3. This delay will not be fixed as the effective load capacitance seen by each gate in the design is different4. Other factors that affect the delay of a gate such as input transition, threshold voltage, drive strength, etc. 9/11/2012 www.vlsisystemdesign.com 64
  • Why to do?9/11/2012 www.vlsisystemdesign.com 65
  • Why to do? Setup time (S) = Data input ‘D’ must be valid before clock transition Hold time (H) = Data input ‘D’ must remain valid after clock edge9/11/2012 www.vlsisystemdesign.com 66
  • Why to do? Setup time (S) = Data input ‘D’ must be valid before clock transition Hold time (H) = Data input ‘D’ must remain valid after clock edge9/11/2012 www.vlsisystemdesign.com 67
  • Why to do? Mux2 Mux1 D Q 0 1 Q F/F 1 0 QM DCLK CLK Positive Edge Triggered ‘D’ F/F Setup time (S) = Data input ‘D’ must be valid before clock transition Hold time (H) = Data input ‘D’ must remain valid after clock edge 9/11/2012 www.vlsisystemdesign.com 68
  • Why to do? Mux2 Mux1 0 1 Q 1 0 QM DCLK Positive Edge Triggered ‘D’ F/F Hence Setup Time => Time required (before clk edge) for ‘D’ to reach QM i.e. internal delay of Mux1 Hence Hold Time => Time required (after clock edge) for QM to reach ‘Q’ i.e. internal delay of Mux2 9/11/2012 www.vlsisystemdesign.com 69
  • Why to do?m > H i.e. Minimum propagation delay of the combinational logic should be greater thanHold Margin 9/11/2012 www.vlsisystemdesign.com 70
  • Why to do?1. If m < H , it results into timing violation, called as Hold violation.2. This means, that the combinational logic delay is very less and hence data change is very fast.3. To satisfy the hold requirement, the combinational logic delay should be increased. 9/11/2012 www.vlsisystemdesign.com 71
  • Why to do?M < Tclk - S i.e. Maximum propagation delay of the combinational logic should be lessthan Clock period (Tclk) minus the Seup Margin9/11/2012 www.vlsisystemdesign.com 72
  • Why to do?1. If M > Tclk - S , it results into timing violation, called as Setup violation.2. This means, that the combinational logic delay is very large and hence data change is very slow.3. To satisfy the setup requirement, the combinational logic delay should be decreased. 9/11/2012 www.vlsisystemdesign.com 73
  • Why to do? m > H + Δ1 i.e. Minimum propagation delay of the combinational logic should be greater than Hold Margin + the clock network delay for sender9/11/2012 www.vlsisystemdesign.com 74
  • Why to do?M < (Tclk - S) + Δ2 i.e. Maximum propagation delay of the combinational logic should be lessthan Clock period (Tclk - Setup Margin ) + clock network delay for receiver i.e. Δ2 9/11/2012 www.vlsisystemdesign.com 75
  • Why to do?9/11/2012 www.vlsisystemdesign.com 76
  • Why to do?9/11/2012 www.vlsisystemdesign.com 77
  • 9/11/2012 www.vlsisystemdesign.com 78
  • How to do?General Tools Used for Placement and Routing1. Synopsys ICC2. Magma Talus3. Cadence First Encounter4. Mentor GraphicsGeneral Tools Used for RC parasitics Extraction1. Synopsys StarXTGeneral Tools Used for STA and noise Analysis1. Synopsys Primetime2. Synopsys Primetime SI 9/11/2012 www.vlsisystemdesign.com 79
  • Thank You For queries mail us: vsd@vlsisystemdesign.com9/11/2012 www.vlsisystemdesign.com 80