Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer,AND, OR gates, buffers) on silicon chip.
Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It ...
Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It ...
Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It ...
Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It ...
Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It ...
Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It ...
• We have defined the Width and Height of the core.•   Also defined the locations of pre-placed cells
Block a         Block bPre-placed   Cells                   Block c        H                                           Die...
• We have defined the Width and Height of the core.•   Also defined the locations of pre-placed cells•   We need to encaps...
Decoupling capacitor encapsulate the Pre-placed Cells•    A decoupling capacitor is used to decouple     the pre-placed ce...
DECAP1             Block a         Block bPre-placed   Cells                   Block c                                    ...
DECAP1             Block a         Block bPre-placed                  DECAP2   Cells                   Block c            ...
DECAP1             Block a         Block bPre-placed                  DECAP2   Cells                   Block c            ...
DECAP1                      D             Block a     Block b                      4Pre-placed                  DECAP2   C...
Upcoming SlideShare
Loading in...5
×

Place decap

746

Published on

https://www.udemy.com/vlsi-academy
http://vlsisystemdesign.com/place_decap.php

Once the critical cells are placed on the chip, it becomes necessary to surround the critical cells by decoupling capacitors. The placement of de-coupling capacitors surrounding the pre-placed cells improves the reliability and efficiency of the chip.

Published in: Education
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
746
On Slideshare
0
From Embeds
0
Number of Embeds
3
Actions
Shares
0
Downloads
4
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Place decap

  1. 1. Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer,AND, OR gates, buffers) on silicon chip.
  2. 2. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Partition and synthesize larger designs into smaller modules consisting of IP’s and std cells
  3. 3. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Define width and Height of ‘core’ and ‘Die’ using the physical area of synthesized netlist, utilization factor and aspect ratio
  4. 4. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Define locations of pre-placed cells
  5. 5. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Place de-coupling capacitors surrounding pre-placed cells
  6. 6. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Power Planning
  7. 7. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• IO Pin/Pad placement
  8. 8. • We have defined the Width and Height of the core.• Also defined the locations of pre-placed cells
  9. 9. Block a Block bPre-placed Cells Block c H Die Core W
  10. 10. • We have defined the Width and Height of the core.• Also defined the locations of pre-placed cells• We need to encapsulate the Pre-placed Cells by Decoupling capacitor .
  11. 11. Decoupling capacitor encapsulate the Pre-placed Cells• A decoupling capacitor is used to decouple the pre-placed cells from main power supply, in order to protect the cells from the disturbance occurring in the power distribution lines and source• The purpose of using decoupling capacitors is to deliver required current to the gates during switching 3/2/2013 11
  12. 12. DECAP1 Block a Block bPre-placed Cells Block c Die Core
  13. 13. DECAP1 Block a Block bPre-placed DECAP2 Cells Block c Die Core
  14. 14. DECAP1 Block a Block bPre-placed DECAP2 Cells Block c DECAP3 Die Core
  15. 15. DECAP1 D Block a Block b 4Pre-placed DECAP2 Cells Block c DECAP3 Die Core
  1. A particular slide catching your eye?

    Clipping is a handy way to collect important slides you want to go back to later.

×